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MAX3420EETG+T
USB Peripheral Controller with SPI Interface
General DescriptionThe MAX3420E contains the digital logic and
analog circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A built-
in full-speed transceiver features ±15kV ESD protection
and programmable USB connect and disconnect. An
internal serial-interface engine (SIE) handles low-level USB
protocol details such as error checking and bus retries.
The MAX3420E operates using a register set accessed
by an SPI interface that operates up to 26MHz. Any SPI
master (microprocessor, ASIC, DSP, etc.) can add USB
functionality using the simple 3- or 4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with interrupts
provided at completion so an SPI master does not need
timers to meet USB timing requirements. The MAX3420E
includes four general-purpose inputs and outputs so any
microprocessor that uses I/O pins to implement the SPI
interface can reclaim the I/O pins and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
LQFP package (7mm x 7mm) and a space-saving 24-pin
TQFN package (4mm x 4mm).
Applications●Cell Phones●PC Peripherals●Microprocessors and DSPs●Custom USB Devices●Cameras●Desktop Routers●PLCs●Set-Top Boxes●PDAs●MP3 Players●Instrumentation
Beneits and Features●Simplifies Adding USB to Any SystemMicroprocessor-Independent USB SolutionComplies with USB Speciication Revision 2.0
(Full-Speed Operation)Integrated Full-Speed USB TransceiverFirmware/Hardware Control of an Internal D+
Pullup ResistorProgrammable 3 or 4-Wire 26MHz SPI InterfaceIntelligent USB Serial-Interface Engine (SIE)Automatically Handles USB Flow Control and
Double BufferingHandles Low-Level USB Signaling DetailsIncludes Timers for USB Time-Sensitive Operations,
So SPI Master Does Not Need to Time EventsFour General-Purpose Inputs and Four General-
Purpose Outputs●Internal Comparator Detects VBUS for Self-Powered
Applications●Interrupt Output Pin (Level or Programmable Edge)
Allows Polled or Interrupt-Driven SPI Interface●Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to Transfer
Data Concurrently with USB Transfers Over the
Same EndpointBuilt-In Endpoint FIFOsEP0: CONTROL (64 Bytes)EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)EP3: IN, Bulk or Interrupt (64 Bytes)●SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware●ESD Protection on D+, D-, and VBCOMP Improves
System Reliability
MAX3420EUSB Peripheral Controller with SPI Interface
EVALUATION KIT AVAILABLE
GPIN3
RGPIN1V TO 3V
VBCOMP
VCC
GPIN2GPIN1GPIN0GPOUT3
GPOUT2
GPOUT1
GPOUT0
VBUS
COMP
MISO
SCLK
INT
SPI SLAVE
INTERFACE
USB SIE
(SERIAL-INTERFACE ENGINE)
FULL-SPEED
USB
TRANSCEIVER
RESET
LOGIC
1.5kΩ
INTERNAL
POR
RESXIVLXO
POWER
DOWN
OSC
AND
PLL 4x
48MHz
ESD
PROTECTION
ESD
PROTECTION
GPX
VBUS_DET
OPERATESOFBUSACT
MUX123
MOSI
VBUS_DET
ENDPOINT
BUFFERS
MAX3420E
GND
Functional DiagramMAX3420EUSB Peripheral Controller with SPI Interface
(All voltages referenced to GND, unless otherwise noted.)
VCC ....................................................................... -0.3V to +4V
VL ...........................................................................-0.3V to +4V
VBCOMP ................................................................-0.3V to +6V
D+, D-, XI, XO .........................................-0.3V to (VCC + 0.3V)
SCLK, MOSI, MISO, SS, RES, GPOUT3–GPOUT0,
GPIN3–GPIN0, GPX, INT ........................-0.3V to (VL + 0.3V)
Continuous Power Dissipation (TA = +70°C)
24-Pin TQFN (derate 20.8mW/°C above +70°C) ......1667mW
32-Pin LQFP (derate 20.7mW/°C above +70°C) ......1653mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VCC = +3V to +3.6V, VL = +1.71V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V,
VL = +2.5V, TA = +25°C.) (Note 1)
Electrical CharacteristicsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Absolute Maximum Ratings
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC CHARACTERISTICSSupply Voltage VCCVCC3.03.33.6V
Logic-Core Supply and Logic-
Interface Voltage VLVL1.713.60V
VCC Supply CurrentICC
Continuously transmitting on D+ and D- at
12Mbps, CL = 50pF on D+ and D- to GND,
CONNECT = 030mA
VL Supply CurrentILSCLK toggling at 20MHz, SS = low,
GPIN3–GPIN0 = 0620mA
VCC Supply Current During IdleICCIDD+ = high, D- = low1.55mA
VCC Suspend Supply CurrentICCSUSCONNECT = 0, PWRDOWN = 133100µA
VL Suspend Supply Current ILSUSCONNECT = 0, PWRDOWN = 11550µA
LOGIC-SIDE I/OMISO, GPOUT3–GPOUT0, GPX,
INT Output High VoltageVOH
ILOAD = +5mA, VL < 2.5VVL - 0.45ILOAD = +10mA, VL ≥ 2.5VVL - 0.4
MISO, GPOUT3–GPOUT0, GPX,
INT Output Low VoltageVOLILOAD = -20mA, VL < 2.5V0.6V
ILOAD = -20mA, VL ≥ 2.5V0.4
SCLK, MOSI, GPIN3–GPIN0, SS,
RES Input High VoltageVIH2/3 x VLV
SCLK, MOSI, GPIN3–GPIN0, SS,
RES Input Low VoltageVIL0.4V
SCLK, MOSI, SS, RES Input
Leakage CurrentIIL1µA
GPIN3–GPIN0 Pullup Resistor to VLRGPIN102030kΩ
TRANSCEIVER SPECIFICATIONSDifferential-Receiver Input
Sensitivity|VD+ - VD-|0.2V
Differential-Receiver Common-
MAX3420EUSB Peripheral Controller with SPI Interface
(VCC = +3V to +3.6V, VL = +1.71V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V,
VL = +2.5V, TA = +25°C.) (Note 1)
Electrical Characteristics (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSingle-Ended Receiver Input Low
VoltageVIL0.8V
Single-Ended Receiver Input High
VoltageVIH2.0V
Single-Ended Receiver Hysteresis
Voltage0.2V
D+, D- Input Impedance300kΩ
D+, D- Output Low VoltageVOLRL = 1.5kΩ from D+ to 3.6V0.3V
D+, D- Output High VoltageVOHRL = 15kΩ from D+ and D- to GND2.83.6V
Driver Output Impedance
Excluding External Resistor(Note 2)2711Ω
D+ Pullup ResistorREXT = 33Ω1.4251.51.575kΩ
ESD PROTECTION (D+, D-, VBCOMP)Human Body Model1µF ceramic capacitors from VBCOMP and
VCC to GND±15kV
IEC61000-4-2 Air-Gap Discharge1µF ceramic capacitors from VBCOMP and
VCC to GND±12kV
IEC61000-4-2 Contact Discharge1µF ceramic capacitors from VBCOMP and
VCC to GND±8kV
THERMAL SHUTDOWNThermal-Shutdown Low-to-High+160°C
Thermal-Shutdown High-to-Low+140°C
CRYSTAL OSCILLATOR SPECIFICATIONS (XI, XO)XI Input High Voltage 2/3 x VCCVCCV
XI Input Low Voltage 0.4V
XI Input Current 10µA
XI, XO Input Capacitance 3pF
VBCOMP COMPARATOR SPECIFICATIONSVBCOMP Comparator ThresholdVTH1.02.03.0V
VBCOMP Comparator HysteresisVHYS375mV
VBCOMP Comparator Input
ImpedanceRIN100kΩ
MAX3420EUSB Peripheral Controller with SPI Interface
Note 1: Parameters are 100% production tested at TA = +25°C, and guaranteed by correlation over temperature.
Note 2: Design guaranteed by bench testing. Limits are not production tested.
Note 3: At VL = 1.71V to 2.5V, derate all of the SPI timing characteristics by 50%. Not production tested.
Note 4: The minimum period is derived from SPI timing parameters.
Note 5: Time-to-exit suspend is dependent on the crystal used.
(VCC = +3V to +3.6V, VL = +1.71V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +3.3V,
VL = +2.5V, TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
USB TRANSMITTER TIMING CHARACTERISTICSD+, D- Rise TimetRISECL = 50pF, Figures 6 and 7420ns
D+, D- Fall TimetFALLCL = 50pF, Figures 6 and 7420ns
Rise/Fall-Time MatchingCL = 50pF, Figures 6 and 7 (Note 2)90110%
Output-Signal Crossover VoltageCL = 50pF, Figures 6 and 7 (Note 2)1.32.0V
SPI BUS TIMING CHARACTERISTICS (VL = 2.5V) (Figures 8 and 9) (Note 3)Serial Clock (SCLK) Period (Note 4)tCPVL = 1.71V77.0ns
VL = 2.5V38.4
SCLK Pulse-Width HightCH17ns
SCLK Pulse-Width LowtCL17ns
SS Fall to MISO ValidtCSS20ns
SS Leading Time Before the First
SCLK EdgetL30ns
SS Trailing Time After the Last
SCLK EdgetT30ns
Data-In Setup TimetDS5ns
Data-In Hold TimetDH10ns
SS Pulse HightCSW200ns
SCLK Fall to MISO Propagation
DelaytDO14.2ns
SCLK Fall to MOSI Propagation
DelaytDI14.2ns
SCLK Fall to MOSI DrivetON3.5ns
SS High to MOSI High ImpedancetOFF20ns
SUSPEND TIMING CHARACTERISTICSTime-to-Enter SuspendPWRDOWN = 1 to oscillator stop5µs
Time-to-Exit SuspendPWRDOWN = 1 to 0 to OSCOKIRQ (Note 5)3ms
Timing CharacteristicsMAX3420EUSB Peripheral Controller with SPI Interface
The MAX3420E connects to any microprocessor using 3
or 4 interface pins (Figure 1). On a simple microprocessor
without SPI hardware, these can be bit-banged general-
purpose I/O pins. Four GPIN and four GPOUT pins on
the MAX3420E more than replace the µP pins necessary
to implement the interface. Although the MAX3420E SPI
hardware includes separate data-in (MOSI, (master-out,
slave-in)) and data-out (MISO, (master-in, slave-out))
pins, the SPI interface can also be configured for the
MOSI pin to carry bidirectional data, saving an interface
pin. This is referred to as half-duplex mode.
Two MAX3420E features make it easy to connect to large,
fast chips such as ASICs and DSPs (see Figure 2). First,
the SPI interface can be clocked up to 26MHz. Second,
a VL pin and internal level translators allow running the
system interface at a lower voltage than the 3.3V required
for VCC.
The MAX3420E provides an ideal method for electrically
isolating a USB interface (Figure 3). USB employs flow
control in which the device automatically answers host
requests with a NAK handshake, until the microprocessor
completes its data-transfer operations over the SPI port.
This means that the SPI interface can run at any frequen-
cy up to 26MHz. Therefore, the designer is free to choose
the interface operating frequency and to make opto-
isolator choices optimized for cost or performance.
Figure 2. The MAX3420E Connected to a Large Chip
Figure 1. The MAX3420E Connects to Any Microprocessor Using 3 or 4 Interface Pins
Typical Application Circuits3.3V
REGULATOR
MISO
LOCAL
GND
LOCAL
POWER
INT
MAX3420E
SCLK
MOSI
MICRO
ASIC
DSPSOLATORS
USB
3.3V
REGULATORPOWER RAIL
ASIC,
DSP,
ETC.
SPI
3, 4
INTMAX3420EUSB
3.3V
REGULATOR
SPI
3, 4
INT
USBµPMAX3420E
MAX3420EUSB Peripheral Controller with SPI Interface
Pin Description
PINNAMEINPUT/
OUTPUTFUNCTIONTQFN-EPLQFP1GPOUT0
Output
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.22GPOUT13, 4VLInput
Level-Translator Reference Voltage. Connect VL to the system’s 1.71V to 3.6V
logic-level power supply. Bypass VL to ground with a 0.1µF capacitor as close to
the VL pin as possible.
4, 145, 6, 18, 19GNDInputGround7GPOUT2
Output
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on VL. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.68GPOUT310RESInput
Device Reset. Drive RES low to clear all of the internal registers except for
PINCTL (R17), USBCTL (R15), and SPI logic. See the Device Reset section for a
description of resets available on the MAX3420E. Note: The MAX3420E is
internally reset if either VCC of VL is not present. The register file is not
accessible under these conditions.11SCLKInput
SPI Serial-Clock Input. An external SPI master supplies this clock with
frequencies up to 26MHz. The logic level is referenced to the voltage on VL.
Data is clocked into the SPI slave interface on the positive edge of SCLK. Data
Is clocked out of the SPI slave interface on the falling edge of SCLK.12SSInput
SPI Slave-Select Input. The SS logic level is referenced to the voltage on VL.
When SS is driven high, the SPI slave interface is not selected and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition
and ends with a low-to-high SS transition.
Pin Conigurations
TQFNMAX3420E
*EP234
*CONNECT EXPOSED PAD TO GND.61716151413
GPOUT0
GPOUT1GPOUT3
SCLK
RES
MISO
MOSI
GPX
GPIN3
GPIN2
GPIN0
GPOUT2
GND
VBCOMPD+VINTGND
GPIN1
TOP VIEW
MAX3420E
LQFPTOP VIEW
GPIN2
GPIN1
GPIN0
N.C.
GPIN3
N.C.N.C.
SCLK
RES
MISO
GPX
MOSI
N.C.181920212223
VBCOMPVD-GNDGNDINT345678
GPOUT3GPOUT2
GNDGND
GPOUT1
GPOUT0
MAX3420EUSB Peripheral Controller with SPI Interface
Pin Description (continued)
PINNAMEINPUT/
OUTPUTFUNCTIONTQFN-EPTQFN-EP13MISOOutput
SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO
is three-stated in half-duplex mode or when SS = 1. The MISO logic level is
referenced to the voltage on VL. 14MOSI
Input or
Input/
Output
SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is
referenced to the voltage on VL. MOSI can also be configured as a bidirectional
MOSI/MISO input and output. 15GPXOutput
General-Purpose Multiplexed Output. The internal MAX3420E signal that
Appears on GPX is programmable by writing to the GPXB and GPXA bits of the
PINCTL (R17) register. GPX indicates one of four signals: OPERATE (00,
default), VBUS_DET (01), BUSACT (10), and SOF (11). 17INTOutput
Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage
on VL. In edge mode, INT is a push-pull output with programmable polarity. In
level mode, INT is open-drain and active low. Set the IE bit in the CPUCTL
(R16) register to enable INT.20D-Input/
Output
USB D- Signal. Connect D- to a USB “B” connector through a 33Ω ±1% series
resistor.21D+Input/
Output
USB D+ Signal. Connect D+ to a USB “B” connector through a 33Ω ±1% series
resistor. The 1.5kΩ D+ pullup resistor is internal to the device.22, 23VCCInput
USB Transceiver Power-Supply Input. Connect VCC to a positive 3.3V power
supply. Bypass VCC to ground with a 1.0µF ceramic capacitor as close to the
VCC pin as possible. 24VBCOMPInput
VBUS Comparator Input. VBCOMP is internally connected to a voltage
comparator to allow the SPI master to detect (through an interrupt or checking a
register bit) the presence or loss of power on VBUS. Bypass VBCOMP to ground
with a 1.0µF ceramic capacitor.26XIInput
Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz
±0.25% crystal and a capacitor to GND. XI can also be driven by an external
Clock referenced to VCC.27XOOutput
Crystal Oscillator Output. Connect XO to the other side of a parallel resonant
12MHz ±0.25% crystal and a capacitor to GND. Leave XO unconnected if XI is
driven with an external source. 29GPIN0
Input
General-Purpose Inputs. GPIN3–GPIN0 are connected to VL with internal pullup
resistors. GPIN3–GPIN0 logic levels are referenced to the voltage on VL. The
SPI master samples GPIN3–GPIN0 states by reading bit 7 through bit 4 of the
IOPINS (R20) register. Writing to these bits has no effect. 30GPIN131GPIN232GPIN39, 16, 25,N.C.—No Internal Connection—EPInputExposed Paddle (TQFN only). Connect EP to GND.
MAX3420EUSB Peripheral Controller with SPI Interface
Register DescriptionThe SPI master controls the MAX3420E by reading and
writing 21 registers (Table 1). For a complete description
of register contents, please refer to the “MAX3420E
Programming Guide.” A register access consists of the
SPI master first writing an SPI command byte, followed
by reading or writing the contents of the addressed
register. All SPI transfers are MSB first. The command
byte contains the register address, a direction bit (read
= 0, write = 1), and the ACKSTAT bit (Figure 4). The
SPI master addresses the MAX3420E registers by writing
the binary value of the register number in the Reg4
through Reg0 bits of the command byte. For example,
to access the IOPINS (R20) register, the Reg4 through
Reg0 bits would be as follows: Reg4 = 1, Reg3 = 0,
Reg2 = 1, Reg1 = 0, Reg0 = 0. The DIR (direction) bit
determines the direction for the data transfer. DIR = 1
means the data byte(s) will be written to the register,
and DIR = 0 means the data byte(s) will be read from
the register. The ACKSTAT bit sets the ACKSTAT bit in
the EPSTALLS (R9) register. The SPI master sets this
bit to indicate that it has finished servicing a CONTROL
transfer. Since the bit is frequently used, having it in the
SPI command byte improves firmware efficiency. In SPI
full-duplex mode, the MAX3420E clocks out eight USB
status bits as the command byte is clocked in (Figure 5).
In half-duplex mode, these status bits are accessed
in the normal way, as register bits.
The first five registers (R0–R4) access endpoint FIFOs.
To access a FIFO, an initial command byte sets the regis-
ter address and then consecutive reads or writes keep the
same register address to access subsequent FIFO bytes.
The remaining registers (R5–R20) control the operation
of the MAX3420E. Once a register address above R4
is set in the command byte, successive byte reads or
writes in the same SPI access cycle (SS low) increment
the register address after every byte read or written. This
incrementing operation continues until R20 is accessed.
Subsequent byte reads or writes continue to access R20.
Note that this autoincrementing action stops with the next
SPI cycle, which establishes a new register address.
Addressing beyond R20 is ignored.
The MAX3420E register map is depicted in Table 1. For a
complete description of all register contents, please refer
to the MAX3420E Programming Guide.
Figure 5. USB Status Bits Clocked Out as First Byte of Every Transfer (Full-Duplex Mode Only)
Figure 4. SPI Command Byte
b6b5b4b3b2b1b0SUSPIRQURESIRQSUDAVIRQIN3BAVIRQIN2BAVIRQOUT1DAVIRQOUT0DAVIRQIN0BAVIRQ
b6b5b4b3b2b1b0Reg4Reg3Reg2Reg1Reg00DIRACKSTAT
MAX3420EUSB Peripheral Controller with SPI Interface
Note: The acc (access) column indicates how the SPI master can access the register.R = read, RC = read or clear, RSC = read, set, or clear.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.
Table 1. MAX3420E Register Map
REGNAMEb7b6b5b4b3b2b1b0accEP0FIFOb7b6b5b4b3b2b1b0RSC
EP1OUTFIFOb7b6b5b4b3b2b1b0RSC
EP2INFIFOb7b6b5b4b3b2b1b0RSC
EP3INFIFOb7b6b5b4b3b2b1b0RSC
SUDFIFOb7b6b5b4b3b2b1b0RSC
EP0BC0b6b5b4b3b2b1b0RSC
EP1OUTBC0b6b5b4b3b2b1b0RSC
EP2INBC0b6b5b4b3b2b1b0RSC
EP3INBC0b6b5b4b3b2b1b0RSC
EPSTALLS0ACKSTATSTLSTATSTLEP3INSTLEP2INSTLEP1OUTSTLEP0OUTSTLEP0INRSC
R10
CLRTOGSEP3DISABEP2DISABEP1DISABCTGEP3INCTGEP2INCTGEP1OUT00RSC
R11
EPIRQ00SUDAVIRQIN3BAVIRQIN2BAVIRQOUT1DAVIRQOUT0DAVIRQIN0BAVIRQRC
R12
EPIEN00SUDAVIEIN3BAVIEIN2BAVIEOUT1DAVIEOUT0DAVIEIN0BAVIERSC
R13
USBIRQURESDNIRQVBUSIRQNOVBUSIRQSUSPIRQURESIRQBUSACTIRQRWUDNIRQOSCOKIRQRC
R14
USBIENURESDNIEVBUSIENOVBUSIESUSPIEURESIEBUSACTIERWUDNIEOSCOKIERSC
R15
USBCTLHOSCSTENVBGATECHIPRESPWRDOWNCONNECTSIGRWU00RSC
R16
CPUCTL0000000IERSC
R17
PINCTLEP3INAKEP2INAKEP0INAKFDUPSPIINTLEVELPOSINTGPXBGPXARSC
R18
REVISION00000100R
R19
FNADDR0b6b5b4b3b2b1b0R
R20
IOPINSGPIN3GPIN2GPIN1GPIN0GPOUT3GPOUT2GPOUT1GPOUT0RSC
MAX3420EUSB Peripheral Controller with SPI Interface
Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))
Figure 7. Load for D+/D- AC MeasurementsFigure 6. Rise and Fall Times
Test Circuits and Timing DiagramsSCLK
MOSI
MISO
NOTES:
1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS
FOR FULL-DUPLEX MODE.
2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.
3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-RISING EDGE, THE MAX3420E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN
OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.
tDS
tDH
tCLtCH
tDItOFF
HI-Z1291016
tCSW
tON
tCP
HIGH IMPEDANCEHIGH IMPEDANCE
SCLK
MOSI
MISO
tDS
tDH
tCL
tDO
tCHtT
HIGH
IMPEDANCE1291016
tCSStCSW
tCP
HIGH
IMPEDANCE
MAX3420E
D+ OR D-
TEST
POINT
33Ω
15kΩCL
VOL
VOH
tRISEtFALL
90%
10%
MAX3420EUSB Peripheral Controller with SPI Interface
(VCC = +3.3V, VL = +3.3V, TA = +25°C.)
Detailed DescriptionThis device contains the digital logic and analog circuitry
necessary to implement a full-speed USB peripheral that
complies with the USB specification rev 2.0. ESD protec-
tion of ±15kV is provided on D+, D-, and VBCOMP. The
MAX3420E features an internal USB transceiver and an
internal 1.5kΩ resistor that connects between D+ and
VCC under the control of a register bit (CONNECT). This
allows a USB peripheral to control the logical connection
to the USB host. Any SPI master can communicate with
the device through the SPI slave interface that operates
in SPI mode (0,0) or (1,1). An SPI master accesses the
MAX3420E by reading and writing to internal registers.
A typical data transfer consists of writing a first byte that
sets a register address and direction with additional bytes
reading or writing data to the register or internal FIFO.
The MAX3420E contains 384 bytes of endpoint buffer
memory, implementing the following endpoints:●EP0: 64-byte bidirectional CONTROL endpoint●EP1: 2 x 64-byte double-buffered BULK/INT
OUT endpoint●EP2: 2 x 64-byte double-buffered BULK/INT IN
endpoint●EP3: 64-byte BULK/INT IN endpoint
The choice to use EP1, EP2, EP3 as BULK or INTERRUPT
endpoints is strictly a function of the endpoint descriptors
that the SPI master returns to the USB host during enu-
meration.
The MAX3420E register set and SPI interface is optimized
to reduce SPI traffic. An interrupt output pin, INT, notifies
the SPI master when USB service is required: when a
packet arrives, a packet is sent, or the host suspends
or resumes bus activity. Double-buffered endpoints help
sustain bandwidth by allowing data to move concurrently
over USB and the SPI interface.
VCCPower the USB transceiver by applying a positive 3.3V
supply to VCC. Bypass VCC to GND with a 1.0µF ceramic
capacitor as close to the VCC pin as possible.
The MAX3420E digital core is powered though the VL pin.
VL also acts as a reference level for the SPI interface and
all other inputs and outputs. Connect VL to the system’s
logic-level power supply. Internal level translators and VL
allow the SPI interface and all general-purpose inputs and
outputs to operate at a system voltage between 1.71V
and 3.6V.
VBCOMPThe MAX3420E features a USB VBUS detector input,
VBCOMP. The VBCOMP pin can withstand input voltag-
es up to 6V. Bypass VBCOMP to GND with a 1.0µF
ceramic capacitor. According to USB specification rev
2.0, a self-powered USB device must not power the
1.5kΩ pullup resistor on D+ if the USB host turns off
VBUS. VBCOMP is internally connected to a voltage
comparator so that the SPI master can detect the loss
Typical Operating Characteristics
EYE DIAGRAMMAX3420E toc011020304050607080
TIME (ns)
D+ AND D- (V)
MAX3420EUSB Peripheral Controller with SPI Interface
