MAX3272AETP ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersApplicationsMAX3272EGP -40°C to +85°C 20 QFN G2044-3Gigabit Ethernet Optical ReceiversMAX3272E/D -4 ..
MAX3272AETP+ ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V = +3.3V ..
MAX3272AETP+T ,+3.3V, 2.5Gbps Low-Power Limiting Amplifiersfeatures include power detectors ♦ 5ps Deterministic Jitterwith programmable loss-of-signal (LOS) i ..
MAX3272AETP+T ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersFeaturesThe MAX3272/MAX3272A 2.5Gbps limiting amplifiers♦ Single +3.3V Power Supplyaccept a wide ra ..
MAX3272EGP ,+3.3V, 2.5Gbps Low-Power Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V = +3.3V ..
MAX3273 ,+3.3V, 2.5Gbps Low-Power Laser DriverApplications(4mm 4mm) SONET OC-48 and SDH STM-1624 Thin QFN MAX3273ETG+ -40°C to +85°C T2444-2 T ..
MAX693ACSE ,Microprocessor Supervisory CircuitsFeaturesThe MAX691A/MAX693A/MAX800L/MAX800M micro-' 200ms Power-OK/Reset Timeout Periodprocessor (µ ..
MAX693ACSE ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/MAX800L/MAX800M19-0094; Rev 7a; 12/96Microprocessor Supervisory Circuits___________ ..
MAX693ACSE+ ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/ Microprocessor Supervisory CircuitsMAX800L/MAX800M
MAX693ACWE ,Microprocessor Supervisory CircuitsFeatures include write pro-™ ™' MaxCap or SuperCap Compatibletection of CMOS RAM or EEPROM, separat ..
MAX693ACWE ,Microprocessor Supervisory CircuitsApplications______________Ordering InformationComputersControllersPART TEMP. RANGE PIN-PACKAGEMAX69 ..
MAX693ACWE ,Microprocessor Supervisory CircuitsFeatures include write pro-™ ™' MaxCap or SuperCap Compatibletection of CMOS RAM or EEPROM, separat ..
MAX3272AETP-MAX3272EGP
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers
General DescriptionThe MAX3272/MAX3272A 2.5Gbps limiting amplifiers
accept a wide range of input voltages and provide a
constant-level output voltage with controlled edge
speeds. Additional features include power detectors
with programmable loss-of-signal (LOS) indication, an
optional squelch function that mutes the data output sig-
nal when the input voltage falls below a programmable
threshold, and an output polarity selector. These parts
exhibit excellent jitter performance and have low power
dissipation.
The MAX3272/MAX3272Afeature current-mode logic
(CML) data outputs that are tolerant of inductive con-
nectors, and are available in a 4mm ✕4mm QFN pack-
age or in die form (MAX3272 only). Along with the
MAX3271, the MAX3272/MAX3272Aare ideal for low-
power, compact optical receivers.
ApplicationsGigabit Ethernet Optical Receivers
Fibre Channel Optical Receivers
System Interconnects
2.5Gbps Optical Receivers
SONET/SDH Receivers
FeaturesSingle +3.3V Power Supply33mA Supply Current5ps Deterministic Jitter90ps Edge SpeedOutput Squelch FunctionProgrammable Loss-of-Signal FunctionCML Output Interface20-Pin 4mm ✕4mm QFN or Thin QFN PackageSelectable Output Polarity
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Ordering Information
Typical Operating Circuit
Pin Configuration appears at end of data sheet.Denotes Lead-Free Package.
*Dice are designed and guaranteed to operate from -40°C to
+85°C, but are tested only at TA= +25°C.
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +6.0V
Voltage at IN+, IN-..........................(VCC- 2.4V) to (VCC+ 0.5V)
Voltage at SQUELCH, CAZ1, CAZ2,
TH, CLOS...............................................-0.5V to (VCC+ 0.5V)
Voltage at LOS, LOS(MAX3272)...........................-0.5V to +6.0V
Voltage at LOS, LOS(MAX3272A).............-0.5V to (VCC+ 0.5V)
Voltage at LEVEL...................................................-0.5V to +2.0V
Voltage at OUTPOL...............................................-0.5V to +6.0V
Current into LOS, LOS..........................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-).................................2.5VP-P
Continuous Current at IN+, IN-...........................................50mA
Continuous Current at
CML Outputs (OUT+, OUT-).........................-25mA to +25mA
Continuous Power Dissipation at +85°C
20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ......1.1W
20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W
Storage Ambient Temperature
Range (TSTG).................................................-55°C to +150°C
Operating Junction Temperature
Range (TJ).....................................................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
ABSOLUTE MAXIMUM RATINGS
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.)
Note 1:Dice are designed and guaranteed from -40°C to +85°C but are tested only at TA= +25°C.
Note 2:Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1, Power-Supply
Current Measurement.
Note 3:Guaranteed by design and characterization.
Note 4:Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum
data rate.
Note 5:Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak
deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A.
Note 6:Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peak-
to-peak random jitter is 14.1 times the RMS random jitter.
Note 7:Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (∆VCC/(∆VOUT)), where ∆VOUTis the
change in differential output voltage due to the power-supply noise, ∆VCC. See Power-Supply Noise Rejection vs.
Frequency in the Typical Operating Characteristics.
Note 8:Hysteresis is defined as: 20 ✕log(VLOS-DEASSERT/VLOS-ASSERT).
Note 9:Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back
and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two
hysteresis thresholds.
Note 10:All power-detect AC parameters are guaranteed with a 223- 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID.
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Typical Operating Characteristics (continued)(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Pin Description
Typical Operating Characteristics (continued)(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3272/MAX3272A
Detailed DescriptionFigure 2 is a functional diagram of the MAX3272/
MAX3272A, comprising a CML input buffer, power
detector and loss-of- signal indicators, gain stage, offset-
correction loop, and CML output buffer.
CML Input BufferThe input buffer (Figure 3) provides 100Ωinput imped-
ance between IN+ and IN-. DC-coupling the inputs is
not recommended; this prevents the DC offset-correc-
tion circuitry from functioning properly.
Power Detect and
Loss-of-Signal IndicatorThe MAX3272/MAX3272A are equipped with loss-of-sig-
nal (LOS) circuitry that indicates when the input signal is
below a programmable threshold, set by resistor RTHat
the TH pin (see the Typical Operating Characteristicsfor
appropriate resistor selection). An averaging peak-
power detector compares the input signal amplitude
with this threshold and feeds the signal-detect informa-
tion to the LOS outputs, which are internally terminated
to 8kΩ(Figure 4).
+3.3V, 2.5Gbps Low-Power
Limiting AmplifiersFigure 1. Power-Supply Current Measurement
Figure 2. Functional Diagram
Two control voltages VASSERT, and VDEASSERT, define
the LOS assert and deassert levels. To prevent LOS
chatter in the region of the programmed threshold,
approximately 3.3dB of hysteresis is built into the LOS
assert/deassert function. Once asserted, LOS is not
deasserted until the input amplitude rises to the
required level (VDEASSERT).
To facilitate interfacing with +5V modules, the LOS and
LOSpins on the MAX3272 do not have internal ESD
protection. If ESD protection is desired, a low-capaci-
tance Schottky diode or diode array structure, such as
the MAX3202E, is recommended (see the Typical
Operating Circuits).
The LOS and LOSpins on the MAX3272A include ESD
protection and, as a result, cannot be interfaced with
+5V modules.
Gain StageThe high-bandwidth gain stage provides approximately
42dB of gain.
Offset-Correction LoopDue to the high gain of the amplifier, the MAX3272/
MAX3272A are susceptible to DC offsets in the signal
path. In communications systems using NRZ data with
a 50% duty cycle, pulse-width distortion present in the
signal or generated by the transimpedance amplifier
appears as input offset and is removed by the offset-
cancellation loop. An external capacitor is required
between CAZ1 and CAZ2 to decouple the offset-can-
cellation loop and determine the lower 3dB frequency
of the signal path.
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Interface Schematics
