MAX3272AEGP-T ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersELECTRICAL CHARACTERISTICS (continued)(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are a ..
MAX3272AETP ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersApplicationsMAX3272EGP -40°C to +85°C 20 QFN G2044-3Gigabit Ethernet Optical ReceiversMAX3272E/D -4 ..
MAX3272AETP+ ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V = +3.3V ..
MAX3272AETP+T ,+3.3V, 2.5Gbps Low-Power Limiting Amplifiersfeatures include power detectors ♦ 5ps Deterministic Jitterwith programmable loss-of-signal (LOS) i ..
MAX3272AETP+T ,+3.3V, 2.5Gbps Low-Power Limiting AmplifiersFeaturesThe MAX3272/MAX3272A 2.5Gbps limiting amplifiers♦ Single +3.3V Power Supplyaccept a wide ra ..
MAX3272EGP ,+3.3V, 2.5Gbps Low-Power Limiting AmplifierELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, T = -40°C to +85°C. Typical values are at V = +3.3V ..
MAX693ACPE ,Microprocessor Supervisory CircuitsFeaturesThe MAX691A/MAX693A/MAX800L/MAX800M micro-' 200ms Power-OK/Reset Timeout Periodprocessor (µ ..
MAX693ACSE ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/MAX800L/MAX800M19-0094; Rev 7a; 12/96Microprocessor Supervisory Circuits___________ ..
MAX693ACSE ,Microprocessor Supervisory CircuitsFeaturesThe MAX691A/MAX693A/MAX800L/MAX800M micro-' 200ms Power-OK/Reset Timeout Periodprocessor (µ ..
MAX693ACSE ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/MAX800L/MAX800M19-0094; Rev 7a; 12/96Microprocessor Supervisory Circuits___________ ..
MAX693ACSE+ ,Microprocessor Supervisory CircuitsMAX691A/MAX693A/ Microprocessor Supervisory CircuitsMAX800L/MAX800M
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MAX3272AEGP-T-MAX3272AETP+-MAX3272AETP+T
+3.3V, 2.5Gbps Low-Power Limiting Amplifiers
General DescriptionThe MAX3272/MAX3272A 2.5Gbps limiting amplifiers
accept a wide range of input voltages and provide a
constant-level output voltage with controlled edge
speeds. Additional features include power detectors
with programmable loss-of-signal (LOS) indication, an
optional squelch function that mutes the data output sig-
nal when the input voltage falls below a programmable
threshold, and an output polarity selector. These parts
exhibit excellent jitter performance and have low power
dissipation.
The MAX3272/MAX3272Afeature current-mode logic
(CML) data outputs that are tolerant of inductive con-
nectors, and are available in a 4mm ✕4mm QFN pack-
age or in die form (MAX3272 only). Along with the
MAX3271, the MAX3272/MAX3272Aare ideal for low-
power, compact optical receivers.
ApplicationsGigabit Ethernet Optical Receivers
Fibre Channel Optical Receivers
System Interconnects
2.5Gbps Optical Receivers
SONET/SDH Receivers
FeaturesSingle +3.3V Power Supply33mA Supply Current5ps Deterministic Jitter90ps Edge SpeedOutput Squelch FunctionProgrammable Loss-of-Signal FunctionCML Output Interface20-Pin 4mm ✕4mm QFN or Thin QFN PackageSelectable Output Polarity
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Ordering Information+3.3V
+3.3V
+3.3V
CAZ
CAZ1
OUTPOL
CAZ2VCC
0.1μF
0.1μFSQUELCH
CCLOS
CLOS
100Ω
IN-
IN+OUT+SDI+SDO+
VCC
SDO-
SCLKO-
SCLKO+
SDI-GND
CDROUT-
MAX3271
MAX3272/
MAX3272A
MAX3873
LOSGND
LOSS
SIGNAL
LOS
RTH
LEVEL
Typical Operating Circuit19-2269; Rev 3; 11/04
Pin Configuration appears at end of data sheet.Typical Operating Circuits continue at end of data sheet.
PARTTEMP RANGEPIN-
PACKAGE
PACKAGE
CODE
MAX3272EGP-40°C to +85°C20 QFNG2044-3
MAX3272E/D-40°C to +85°CDice*—
MAX3272AETP+-40°C to +85°C20 Thin QFNT2044-3
MAX3272AEGP-40°C to +85°C20 QFNG2044-3Denotes Lead-Free Package.
*Dice are designed and guaranteed to operate from -40°C to
+85°C, but are tested only at TA= +25°C.
EVALUATION KIT
AVAILABLE
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +6.0V
Voltage at IN+, IN-..........................(VCC- 2.4V) to (VCC+ 0.5V)
Voltage at SQUELCH, CAZ1, CAZ2,
TH, CLOS...............................................-0.5V to (VCC+ 0.5V)
Voltage at LOS, LOS(MAX3272)...........................-0.5V to +6.0V
Voltage at LOS, LOS(MAX3272A).............-0.5V to (VCC+ 0.5V)
Voltage at LEVEL...................................................-0.5V to +2.0V
Voltage at OUTPOL...............................................-0.5V to +6.0V
Current into LOS, LOS..........................................-1mA to +9mA
Differential Input Voltage (IN+ - IN-).................................2.5VP-P
Continuous Current at IN+, IN-...........................................50mA
Continuous Current at
CML Outputs (OUT+, OUT-).........................-25mA to +25mA
Continuous Power Dissipation at +85°C
20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ......1.1W
20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W
Storage Ambient Temperature
Range (TSTG).................................................-55°C to +150°C
Operating Junction Temperature
Range (TJ).....................................................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply CurrentICC(Note 2)3344mA
Input Data Rate2.5Gbps
Input Voltage RangeVINDifferential151200mVP-P
Output Deterministic Jitter(Notes 3, 4, 5)527psP-P
Random Jitter(Notes 4, 6)3psRMS
15mVP-P < VIN ≤ 30mVP-P90130Data Output Edge Speed
(20% to 80%)(Notes 3, 4)30mVP-P ≤ VIN ≤ 1200mVP-P90115ps
Differential Input ResistanceRININ+ to IN-95100105Ω
Input-Referred Noise220µVRMS
CML Output VoltageVOUTLEVEL open, RLOAD = 50Ω5507501200mVP-P
Output Signal when SquelchedOutputs AC-coupled2.2mVP-P
Power-Supply Noise RejectionPSNRf ≤ 2MHz (Note 7)30dB
CAZ = open0.9MHzLow Frequency CutofffOCCAZ = 0.1µF1.5kHz
Output ResistanceROUTSingle ended to VCC42.55057.5Ω
≤ 2.5GHz10Single-Ended Output Return
Loss2.5GHz to 4.0GHz9dB
Differential Input Return Loss4.0GHz10dB
VIL0.8OUTPOL Input LimitsVIH2.4V
LOS Hysteresis(Notes 3, 4, 8)23.3dB
CCLOS = open (Notes 3, 9, 10)1LOS Assert/Deassert TimeCCLOS = 0.01µF (Notes 3, 9, 10)2.350100µs
Low LOS Assert LevelRTH = 20kΩ (Notes 3, 10)4.56.5mVP-P
Low LOS Deassert LevelRTH = 20kΩ (Notes 3, 10)9.512.7mVP-P
Medium LOS Assert LevelRTH = 1kΩ (Notes 3, 10)7.812.9mVP-P
Medium LOS Deassert LevelRTH = 1kΩ (Notes 3, 10)17.422.4mVP-P
High LOS Assert LevelRTH = 80Ω (Notes 3, 10)24.348mVP-P
ABSOLUTE MAXIMUM RATINGS
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V and TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSHigh LOS Deassert LevelRTH = 80Ω (Notes 3, 10)73124.7mVP-P
LOS Output High VoltageSinking 30µA2.4V
LOS Output Low VoltageSourcing 1.2mA0.4V
Squelch Input Current400µA
Note 1:Dice are designed and guaranteed from -40°C to +85°C but are tested only at TA= +25°C.
Note 2:Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1, Power-Supply
Current Measurement.
Note 3:Guaranteed by design and characterization.
Note 4:Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum
data rate.
Note 5:Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak
deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A.
Note 6:Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peak-
to-peak random jitter is 14.1 times the RMS random jitter.
Note 7:Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (∆VCC/(∆VOUT)), where ∆VOUTis the
change in differential output voltage due to the power-supply noise, ∆VCC. See Power-Supply Noise Rejection vs.
Frequency in the Typical Operating Characteristics.
Note 8:Hysteresis is defined as: 20 ✕log(VLOS-DEASSERT/VLOS-ASSERT).
Note 9:Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back
and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two
hysteresis thresholds.
Note 10:All power-detect AC parameters are guaranteed with a 223- 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID.
Typical Operating Characteristics(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
OUTPUT AMPLITUDE
vs. INPUT AMPLITUDE
MAX3272 toc01
VIN (mVP-P)
OUT
(mV
P-P
LEVEL = GND
LEVEL = OPEN
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
MAX3272 toc02
AMBIENT TEMPERATURE (°C)
SUPPLY CURRENT (mA)
110100100010,000
DETERMINISTIC JITTER
vs. INPUT AMPLITUDEMAX3272 toc03
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER (ps
P-P
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Typical Operating Characteristics (continued)(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
110100100010,000
RANDOM JITTER vs. INPUT AMPLITUDEMAX3272 toc04
INPUT AMPLITUDE (mVp-p)
RANDOM JITTER (ps
RMS
CCLOS = 0.01μF
VOUT
VIN
LOSS-OF-SIGNAL WITH SQUELCHMAX3272 toc06
20μs/div
VLOS
LOSS OF SIGNAL TRESHOLD vs. RTHXXXXXXXX
RTH (Ω)
LOS ASSERT (mV)
100k10k1k1001M
DATA OUTPUT EYE DIAGRAM
(MINIMUM INPUT)MAX3272 toc08
2.5Gbps
223 -1 PRBS
15mVP-P INPUT
100ps/div
150mV/
div
DATA OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)MAX3272 toc09
100ps/div
150mV/
div
2.5Gbps
223 -1 PRBS
1200mVP-P INPUT100k10k1M10M
POWER-SUPPLY NOISE REJECTION
vs. FREQUENCYMAX3272 toc10
FREQUENCY (Hz)
POWER-SUPPLY NOISE REJECTION (dB)
10M100M1G10G
INPUT RETURN LOSS vs. FREQUENCYMAX3272 toc11
FREQUENCY (Hz)
INPUT RETURN LOSS (dB)
LOS HYSTERESIS
vs. AMBIENT TEMPERATURE
MAX3272 toc05
AMBIENT TEMPERATURE (°C)
HYSTERESIS (dB)-153560
RTH = 80Ω
RTH = 20kΩ
RTH = 1kΩ
10M100M1G10G
OUTPUT RETURN LOSS vs. FREQUENCYMAX3272 toc12
FREQUENCY (Hz)
OUTPUT RETURN LOSS (dB)
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Pin Description
Typical Operating Characteristics (continued)(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
100k1M10M100M
COMMON-MODE REJECTION RATIO
vs. FREQUENCYMAX3272 toc13
FREQUENCY (Hz)
COMMON-MODE REJECTION RATIO (dB)
PINNAMEFUNCTION1, 4, 17GNDSupply GroundIN+Noninverted Input SignalIN-Inverted Input Signal
5THLoss-of-Signal Threshold Pin. Resistor to ground sets the LOS threshold.
6, 12, 15, 20VCCPower SupplyCLOSLO S Ti m e- C onstant C ap aci tor C onnecti on. For S ON E T ap p l i cati ons, C C L OS = 0.01µF i s r ecom m end ed .SQUELCH
Squelch Input. The squelch function is disabled when SQUELCH is not connected or set to TTL low
level. When SQUELCH is set to TTL high level and LOS is asserted, the data outputs (OUT+, OUT-)
are forced to static levels.LOS
Noninverted Loss-of-Signal Output. LOS is asserted TTL high when the signal drops below the assert
threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The
MAX3272A has ESD protection on this pin.LOS
Inverted Loss-of-Signal Output. LOS is asserted TTL low when the signal drops below the assert
threshold set by the TH input. The MAX3272 does not have ESD protection on this pin. The
MAX3272A has ESD protection on this pin.LEVELOutput Current Level. When this pin is not connected, the CML output current is approximately
16mA. When this pin is connected to ground, the output current increases to about 20mA.OUT-Inverted Data OutputOUT+Noninverted Data OutputOUTPOLOutput Polarity Control Input. Connect to GND for an inversion of polarity through the limiting
amplifier and connect to VCC for normal operation.CAZ2Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ1
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF.CAZ1Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ2
extends the time constant of the offset correction loop. Typical value of CAZ is 0.1µF.EXPOSED
PADConnect the exposed paddle to board ground for optimal electrical and thermal performance.2500
LOS ASSERT AND DEASSERT LEVELS
vs. DATA RATEMAX3272 toc14
DATA RATE (Mbps)
(mV
P-P
223 - 1 PRBS PATTERN
RTH = 20kΩ
CIN = 0.1μF
DEASSERT
ASSERT
MAX3272/MAX3272A
Detailed DescriptionFigure 2 is a functional diagram of the MAX3272/
MAX3272A, comprising a CML input buffer, power
detector and loss-of- signal indicators, gain stage, offset-
correction loop, and CML output buffer.
CML Input BufferThe input buffer (Figure 3) provides 100Ωinput imped-
ance between IN+ and IN-. DC-coupling the inputs is
not recommended; this prevents the DC offset-correc-
tion circuitry from functioning properly.
Power Detect and
Loss-of-Signal IndicatorThe MAX3272/MAX3272A are equipped with loss-of-sig-
nal (LOS) circuitry that indicates when the input signal is
below a programmable threshold, set by resistor RTHat
the TH pin (see the Typical Operating Characteristicsfor
appropriate resistor selection). An averaging peak-
power detector compares the input signal amplitude
with this threshold and feeds the signal-detect informa-
tion to the LOS outputs, which are internally terminated
to 8kΩ(Figure 4).
+3.3V, 2.5Gbps Low-Power
Limiting AmplifiersCML SUPPLY CURRENT (ICC)
VCC
ICC
IOUT
50Ω
RTH
50Ω
CONTROL
SQUELCH
OPEN
LEVEL
OPEN
MAX3272/
MAX3272A
Figure 1. Power-Supply Current Measurement
MAX3272/
MAX3272ATTL
TTL
CONTROL
POWER
DETECTOR
IN+
IN-
100Ω
POWER DETECTOR AND
LOS INDICATOR
CML
INPUT
BUFFER
CML
OUTPUT
BUFFER
OFFSET
CORRECTION0.1μF
LOWPASS
FILTER
LOS
SQUELCH
OUT+
OUT-
LEVEL
OUTPOL
LOS
CAZ1CAZ2CLOS
Figure 2. Functional Diagram
Two control voltages VASSERT, and VDEASSERT, define
the LOS assert and deassert levels. To prevent LOS
chatter in the region of the programmed threshold,
approximately 3.3dB of hysteresis is built into the LOS
assert/deassert function. Once asserted, LOS is not
deasserted until the input amplitude rises to the
required level (VDEASSERT).
To facilitate interfacing with +5V modules, the LOS and
LOSpins on the MAX3272 do not have internal ESD
protection. If ESD protection is desired, a low-capaci-
tance Schottky diode or diode array structure, such as
the MAX3202E, is recommended (see the Typical
Operating Circuits).
The LOS and LOSpins on the MAX3272A include ESD
protection and, as a result, cannot be interfaced with
+5V modules.
Gain StageThe high-bandwidth gain stage provides approximately
42dB of gain.
Offset-Correction LoopDue to the high gain of the amplifier, the MAX3272/
MAX3272A are susceptible to DC offsets in the signal
path. In communications systems using NRZ data with
a 50% duty cycle, pulse-width distortion present in the
signal or generated by the transimpedance amplifier
appears as input offset and is removed by the offset-
cancellation loop. An external capacitor is required
between CAZ1 and CAZ2 to decouple the offset-can-
cellation loop and determine the lower 3dB frequency
of the signal path.
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
Interface SchematicsIN+
IN-
110Ω
GND
ESD
STRUCTURES
VCC
540Ω540Ω
0.25pF
0.25pF
Figure 3. Input Circuit
GND
ESD
STRUCTURE
VCC
LOS
8kΩ
Figure 4a. LOS Output Circuit for MAX3272
GND
ESD
STRUCTURE
VCC
LOS
8kΩ
Figure 4b. LOS Output Circuit for MAX3272A
