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MAX3207EAUT-T
Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
General DescriptionThe MAX3205E/MAX3207E/MAX3208E low-capaci-
tance, ±15kV ESD-protection diode arrays with an inte-
grated transient voltage suppressor (TVS) clamp are
suitable for high-speed and general-signal ESD protec-
tion. Low input capacitance makes these devices ideal
for ESD protection of signals in HDTV, PC monitors
(DVI™, HDMI™), PC peripherals (FireWire®, USB 2.0),
server interconnect (PCI Express™, Infiniband®),
datacom, and interchassis interconnect. Each channel
consists of a pair of diodes that steer ESD current puls-
es to VCCor GND.
The MAX3205E/MAX3207E/MAX3208E protect against
ESD pulses up to ±15kV Human Body Model, ±8kV
Contact Discharge, and ±15kV Air-Gap Discharge, as
specified in IEC 61000-4-2. An integrated TVS ensures
that the voltage rise seen on VCCduring an ESD event
is clamped to a known voltage. These devices have a
2pF input capacitance per channel, and a channel-to-
channel capacitance variation of only 0.05pF, making
them ideal for use on high-speed, single-ended, or dif-
ferential signals.
The MAX3207E is a two-channel device suitable for
USB 1.1, USB 2.0 (480Mbps), and USB OTG applica-
tions. The MAX3208E is a four-channel device for
Ethernet and FireWire applications. The MAX3205E is a
six-channel device for cell phone connectors and
SVGA video connections.
The MAX3205E is available in 9-bump, tiny chip-scale
(UCSP™), and 16-pin, 3mm x 3mm, thin QFN pack-
ages. The MAX3207E is available in a small 6-pin
SOT23 package. The MAX3208E is available in 10-pin
µMAX®and 16-pin, 3mm x 3mm TQFN packages. All
devices are specified for the -40°C to +125°C automo-
tive operating temperature range.
ApplicationsDVI Input/Output Protection
Set-Top Boxes
PDAs/Cell Phones
Graphics Controller Cards
Displays/Projectors
High-Speed, Full-Speed and Low-Speed USB
Port Protection
FireWire IEEE 1394 Ports
Consumer Equipment
High-Speed Differential Signal Protection
FeaturesLow Input Capacitance of 2pF TypicalLow Channel-to-Channel Variation of 0.05pF
from I/O to I/OHigh-Speed Differential or Single-Ended ESD
Protection
±15kV–Human Body Model
±8kV–IEC 61000-4-2, Contact Discharge
±15kV–IEC 61000-4-2, Air-Gap DischargeIntegrated Transient Voltage Suppressor (TVS)Optimized Pinout for Minimized Stub Instances on
Controlled-Impedance Differential-Transmission
Line Routing-40°C to +125°C Automotive Operating
Temperature RangeUCSP Packaging Available
MAX3205E/MAX3207E/MAX3208E
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Ordering Information19-3361; Rev 2; 3/05
*EP = Exposed pad.
FireWire is a registered trademark of Apple Computer, Inc.
PCI Express is a trademark of PCI-SIG Corporation.
DVI is a trademark of Digital Display Working Group.
HDMIis a trademark of HDMILicensing, LCC.
InfiniBand is a registered trademark of InfiniBand Trade
Association.
UCSP is a trademark and µMAX is a registered trademark of
Maxim Integrated Products, Inc.
Typical Operating Circuit and Pin Configurations appear at
end of data sheet.
MAX3205E/MAX3207E/MAX3208E
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:Idealized clamp voltages. See the Applications Informationsection for more information.
Note 3:Guaranteed by design, not production tested.
VCCto GND...........................................................-0.3V to +6.0V
I/O_ to GND................................................-0.3V to (VCC+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
6-Pin SOT23 (derate 8.7mW/°C above +70°C)............696mW
9-Pin UCSP (derate 4.7mW/°C above +70°C).............379mW
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
16-Pin Thin QFN (derate 20.8mW/°C above +70°C).1667mW
Operating Temperature Range.........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Bump Temperature (soldering)
Infrared (15s)...............................................................+220°C
Vapor Phase (60s).......................................................+215°C
MAX3205E/MAX3207E/MAX3208E
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
CLAMP VOLTAGE
vs. DC CURRENTMAX3205E toc01
DC CURRENT (mA)
CLAMP VOLTAGE (V)
LEAKAGE CURRENT
vs. TEMPERATURE
MAX3205E toc02
TEMPERATURE (°C)
LEKAGE CURRENT (pA)400
10,000
INPUT CAPACITANCE
vs. INPUT VOLTAGE
MAX3205E toc03
INPUT VOLTAGE (V)
INPUT CAPACITANCE (pF)321
Typical Operating Characteristics(VCC= +5V, TA = +25°C, unless otherwise noted.)
MAX3205E/MAX3207E/MAX3208E
Detailed DescriptionThe MAX3205E/MAX3207E/MAX3208E low-capacitance,
±15kV ESD-protection diode arrays with an integrated
transient voltage suppressor (TVS) clamp are suitable for
high-speed and general-signal ESD protection. Low
input capacitance makes these devices ideal for ESD
protection of signals in HDTV, PC monitors (DVI, HDMI),
PC peripherals (FireWire, USB 2.0), Server Interconnect
(PCI Express, Infiniband), Datacom, and Inter-Chassis
Interconnect. Each channel consists of a pair of diodes
that steer ESD current pulses to VCCor GND. The
MAX3205E, MAX3207E, and MAX3208E are two, four,
and six channels (see the Functional Diagram).
The MAX3205E/MAX3207E/MAX3208E are designed to
work in conjunction with a device’s intrinsic ESD pro-
tection. The MAX3205E/MAX3207E/MAX3208E limit the
excursion of the ESD event to below ±25V peak voltage
when subjected to the Human Body Model waveform.
When subjected to the IEC 61000-4-2 waveform, the
peak voltage is limited to ±60V when subjected to
Contact Discharge. The peak voltage is limited to
±100V when subjected to Air-Gap Discharge. The
device protected by the MAX3205E/MAX3207E/
MAX3208E must be able to withstand these peak volt-
ages, plus any additional voltage generated by the par-
asitic of the board.
A TVS is integrated into the MAX3205E/MAX3207E/
MAX3208E to help clamp ESD to a known voltage. This
helps reduce the effects of parasitic inductance on the
VCCrail by clamping VCCto a known voltage during an
ESD event. For the lowest possible clamp voltage dur-
ing an ESD event, placing a 0.1µF capacitor as close to
VCCas possible is recommended.
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Functional Diagram
Applications Information
Design ConsiderationsMaximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section). A good layout reduces the parasitic series
inductance on the ground line, supply line, and protect-
ed signal lines. The MAX3205E/MAX3207E/MAX3208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
VCC. In an ideal circuit, the clamping voltage (VC) is
defined as the forward voltage drop (VF) of the protec-
tion diode, plus any supply voltage present on the cath-
ode.
For positive ESD pulses:= VCC+ VF
For negative ESD pulses:=-VF
The effect of the parasitic series inductance on the
lines must also be considered (Figure 1).
For positive ESD pulses:
For negative ESD pulses:
where, IESDis the ESD current pulse.
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 2). For example,
in a 15kV IEC-61000 Air-Gap Discharge ESD event, the
pulse current rises to approximately 45A in 1ns (di/dt =
45 x 109). An inductance of only 10nH adds an addi-
tional 450V to the clamp voltage, and represents
approximately 0.5in of board trace. Regardless of the
device’s specified diode clamp voltage, a poor layout
with parasitic inductance significantly increases the
effective clamp voltage at the protected signal line.
Minimize the effects of parasitic inductance by placing
the MAX3205E/MAX3207E/MAX3208E as close to the
connector (or ESD contact point) as possible.
A low-ESR 0.1µF capacitor is recommended between
VCCand GND in order to get the maximum ESD protec-
tion possible. This bypass capacitor absorbs the
charge transferred by a positive ESD event. Ideally, the
supply rail (VCC) would absorb the charge caused by a
positive ESD strike without changing its regulated
value. All power supplies have an effective output
impedance on their positive rails. If a power supply’s
effective output impedance is 1Ω, then by using V = I x
R, the clamping voltage of VCincreases by the equa-
tion VC= IESDx ROUT. A +8kV IEC 61000-4-2 ESD
event generates a current spike of 24A. The clamping
voltage increases by VC= 24A x 1Ω, or VC= 24V.
Again, a poor layout without proper bypassing increas-
es the clamping voltage. A ceramic chip capacitor
mounted as close as possible to the MAX3205E/
MAX3207E/MAX3208E VCCpin is the best choice for
this application. A bypass capacitor should also be
placed as close to the protected device as possible.
MAX3205E/MAX3207E/MAX3208E
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
MAX3205E/MAX3207E/MAX3208E
±15kV ESD ProtectionESD protection can be tested in various ways. The
MAX3205E/MAX3207E/MAX3208E are characterized
for protection to the following limits:±15kV using the Human Body Model±8kV using the Contact Discharge Method specified
in IEC 61000-4-2±15kV using the IEC 61000-4-2 Air-Gap Discharge
Method
ESD Test ConditionsESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
Human Body ModelFigure 3 shows the Human Body Model, and Figure 4
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩresistor.
IEC 61000-4-2The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX3205E/
MAX3207E/MAX3208E help users design equipment
that meets Level 4 of IEC 61000-4-2. The main differ-
ence between tests done using the Human Body Model
and IEC 61000-4-2 is higher peak current in IEC 61000-
4-2. Because series resistance is lower in the IEC
61000-4-2 ESD test model (Figure 5), the ESD-
withstand voltage measured to this standard is general-
ly lower than that measured using the Human Body
Model. Figure 2 shows the current waveform for the
±8kV, IEC 61000-4-2 Level 4, ESD Contact Discharge
test. The Air-Gap Discharge test involves approaching
the device with a charged probe. The Contact
Discharge method connects the probe to the device
before the probe is energized.
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Layout RecommendationsProper circuit-board layout is critical to suppress ESD-
induced line transients (See Figure 6). The MAX3205E/
MAX3207E/MAX3208E clamp to 100V; however, with
improper layout, the voltage spike at the device can be
much higher. A lead inductance of 10nH with a 45A
current spike results in an additional 450V spike on the
protected line. It is essential that the layout of the PC
board follows these guidelines:Minimize trace length between the connector or
input terminal, I/O_, and the protected signal line.Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.Ensure short low-inductance ESD transient return
paths to GND and VCC.Minimize conductive power and ground loops.Do not place critical signals near the edge of the PC
board.Bypass VCCto GND with a low-ESR ceramic capaci-
tor as close to VCCas possible.Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
UCSP Applications InformationFor the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile, as well as the latest infor-
mation on reliability testing results, go to the Maxim
website at /ucsp for the Application
Note, UCSP—A Wafer-Level Chip-Scale Package.
Chip InformationDIODE COUNT:
MAX3205E: 7
MAX3207E: 3
MAX3208E: 5
PROCESS: BiCMOS
MAX3205E/MAX3207E/MAX3208E
Dual, Quad, and Hex High-Speed
Differential ESD-Protection ICs
Typical Operating Circuit
