MAX3111EEWI ,SPI/MICROWIRE-Compatible UART and 【15kV ESDProtected RS-232 Transceivers with Internal CapacitorsELECTRICAL CHARACTERISTICS—MAX3110E(V = +4.5V to +5.5V, T = T to T , unless otherwise noted. Typica ..
MAX3111EEWI-T ,SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal Capacitorsapplications. The MAX3110E/MAX3111E also®feature an SPI/QSPI™/MICROWIRE -compatible serial• Interna ..
MAX311CPE ,CMOS RF/Video MultiplexerslVI/l X I [VI
CMOS RF/Video Multiplexers
MAX311CPE+ ,8-Channel, CMOS RF Video MultiplexerELECTRICAL CHARACTERISTICS
(Over Temperature. V+ = +15V, v- = -15V, GND = 0V unless otherwise in ..
MAX311CWN+ ,8-Channel, CMOS RF Video MultiplexerGeneral Description
Maxim's MAX31O and MAX311 are CMOS monolithic
analog multiplexer/demultiple ..
MAX311EWN ,CMOS RF/Video MultiplexersApplications
Video Switching and Crosspoint Systems
Automatic Test Equipment
Medical Ultrasoun ..
MAX6367LKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingApplicationsM A X6 36 7 LK A_ _-T -40°C to +85°C 8 SOT23Critical µP/µC Power Portable/Battery-M A ..
MAX6367PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX6368LKA26+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingMAX6365–MAX6368 19-1658; Rev 5; 10/11SOT23, Low-Power µP Supervisory Circuitswith Battery Backup an ..
MAX6368LKA29+ ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable Gatingfeatures.MAX6365Devices are available in both leaded and lead(Pb)-free packaging.GND 3 6 OUTSpecify ..
MAX6368PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX6368PKA31+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingMAX6365–MAX6368 19-1658; Rev 5; 10/11SOT23, Low-Power µP Supervisory Circuitswith Battery Backup an ..
MAX3111ECWI-MAX3111EEWI
SPI/MICROWIRE-Compatible UART and 【15kV ESDProtected RS-232 Transceivers with Internal Capacitors
General DescriptionThe MAX3110E/MAX3111E combine a full-featured uni-
versal asynchronous receiver/transmitter (UART) with
±15kV ESD-protected RS-232 transceivers and inte-
grated charge-pump capacitors into a single 28-pin
package for use in space-, cost-, and power-con-
strained applications. The MAX3110E/MAX3111E also
feature an SPI™/QSPI™/MICROWIRE™-compatible
serial interface to save additional board space and
microcontroller (µC) I/O pins.
A proprietary low-dropout output stage enables the
2-driver/2-receiver interface to deliver true RS-232 per-
formance down to VCC= +3V (+4.5V for MAX3110E)
while consuming only 600µA. The receivers remain
active in a hardware/software-invoked shutdown, allow-
ing external devices to be monitored while consuming
only 10µA. Each device is guaranteed to operate at up
to 230kbps while maintaining true EIA/TIA-232 output
voltage levels.
The MAX3110E/MAX3111E’s UART includes a crystal
oscillator and baud-rate generator with software-pro-
grammable divider ratios for all common baud rates
from 300baud to 230kbaud. The UART features an 8-
word-deep receive FIFO that minimizes processor over-
head and provides a flexible interrupt with four
maskable sources. Two control lines (one input and
one output) are included for hardware handshaking.
The UART and RS-232 functions can be used together
or independently since the two functions share only
supply and ground connections (the MAX3110E/
MAX3111E are hardware- and software-compatible
with the MAX3100 and MAX3222E).
________________________ApplicationsPoint-of-Sale (POS) Devices
Handy-Terminals
Telecom/Networking Diagnostic Ports
Industrial Front-Panel Interfaces
Hand-Held/Battery-Powered Equipment
FeaturesIntegrated RS-232 Transceiver and UART in a
Single 28-Pin PackageSPI/QSPI/MICROWIRE-Compatible µC InterfaceInternal Charge-Pump Capacitors—
No External Components Required!True RS-232 Operation Down to VCC= +3V
(MAX3111E)ESD Protection for RS-232 I/O Pins
±15kV—Human Body Model
±8kV—IEC 1000-4-2, Contact Discharge
±15kV—IEC 1000-4-2, Air-Gap DischargeSingle-Supply Operation
+5V (MAX3110E)
+3.3V (MAX3111E)Low Power
600µA Supply Current
10µA Shutdown Supply Current with
Receiver Interrupt ActiveGuaranteed 230kbps Data RateHardware/Software-Compatible with MAX3100
and MAX3222E
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors19-1494; Rev 0; 7/99
Typical Application Circuit
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIREis a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Pin Configuration appears at end of data sheet.†Covered by U.S. Patent numbers 4,636,930; 4,679,134;
4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and
other patents pending.
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX3110E(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and function-
al operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND (MAX3110E)........................................-0.3V to +6V
VCCto GND (MAX3111E).........................................-0.3V to +4V
V+ to GND (Note 1)..................................................-0.3V to +7V
V- to GND (Note 1)...................................................+0.3V to -7V
V+ to V- (Note 1)..................................................................+13V
Input Voltages to GND
CS, X1, CTS, RX, DIN, SCLK..................-0.3V to (VCC + 0.3V)
T_IN, SHDN...........................................................-0.3V to +6V
R_IN..................................................................................±25V
Output Voltage to GND
DOUT, RTS, TX, X2 .................................-0.3V to (VCC + 0.3V)
IRQ.......................................................................-0.3V to +6V
T_OUT ...........................................................................±13.2V
R_OUT.....................................................-0.3V to (VCC+ 0.3V)
TX, RTSOutput Current....................................................100mA
Short-Circuit Duration
X2, DOUT, IRQ(to VCCor GND).............................Continuous
T_OUT (to GND) .....................................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-pin Wide SO (derate 12.5mW/°C above +70°C) ...........1W
28-pin Plastic DIP (derate 14.3mW/°C above +70°C)....1.14W
Operating Temperature Ranges
MAX311_EC_ _ ..................................................0°C to +70°C
MAX311_EE_ _ ................................................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
Note 1:V+ and V- can have maximum magnitudes of 7V, but their absolute difference should not exceed 13V.
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3110E (continued)(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3110E (continued)(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
MAX3110E/MAX3111E
ELECTRICAL CHARACTERISTICS—MAX3111E(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3111E (continued)(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3111E (continued)(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)
Note 2:All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground unless otherwise noted.
Note 3:ICCSHDN(H)represents a hardware-only shutdown. In hardware shutdown, the UART is in normal operation and the charge
pumps for the RS-232 transmitters are shut down.
Note 4:ICCSHDN(H+S)represents a simultaneous software and hardware shutdown in which the UART and charge pumps are
shut down.
Note 5:Transmitter skew is measured at the transmitter zero cross points.
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Pin Description
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Detailed DescriptionThe MAX3110E/MAX3111E contain an SPI/QSPI/MICROWIRE-
compatible UART and an RS-232 transceiver with two
drivers and two receivers. The UART is compatible with
SPI and QSPI for CPOL = 0 and CPHA = 0. The UART
supports data rates up to 230kbaud for standard UART
bit streams as well as IrDA and includes an 8-word
receive FIFO. Also included is a 9-bit-address recogni-
tion interrupt.
The RS-232 transceiver has electrostatic discharge
(ESD) protection on the transmitter outputs and the
receiver inputs. The internal charge-pump capacitors
minimize the number of external components required.
The RS-232 transceivers meet EIA/TIA-232 specifica-
tions for VCCdown to the minimum supply voltage and
are guaranteed to operate for data rates up to 250kbps.
The UART and RS-232 functions operate as one device
or independently since the two functions share only
supply and ground connections.
UARTThe universal asynchronous receiver transmitter
(UART) interfaces the SPI/QSPI/MICROWIRE-compati-
ble synchronous serial data from a microprocessor (µP)
to asynchronous, serial-data communication ports (RS-
232, IrDA). Figure 1 shows the MAX3110E/MAX3111E
functional diagram. Included in the UART function is an
SPI/QSPI/MICROWIREinterface, a baud-rate generator,
and an interrupt generator.
Figure 1. MAX3110E/MAX3111E Functional Diagram
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
MAX3110E/MAX3111E
SPI InterfaceThe MAX3110E/MAX3111E are compatible with SPI,
QSPI (CPOL = 0, CPHA = 0), and MICROWIREserial-
interface standards (Figure 2). The MAX3110E/
MAX3111E have a unique full-duplex-only architecture
that expects a 16-bit word for DIN and simultaneously
produces a 16-bit word for DOUT regardless of which
read/write register is used. The DIN stream is moni-
tored for its first two bits to tell the UART the type of
data transfer being executed (see the Write
Configuration Register, Read Configuration Register,
Write Data Register, and Read Data Register sections).
DIN (MOSI) is latched on SCLK’s rising edge. DOUT
(MISO) should be read into the µP on SCLK’s rising
edge. The first bit (bit 15) of DOUT transitions on CS’s
falling edge, and bits 14–0 transition on SCLK’s falling
edge. Figure 3 shows the detailed serial timing specifi-
cations for the synchronous SPI port.
Only 16-bit words are expected. If CSgoes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on CS’s
rising edge. Every time CSgoes low, a new 16-bit
stream is expected. An example of using the Write
Configuration Register is shown in Figure 4.
Table 1 describes the bits located in the Write Config-
uration, Read Configuration, Write Data, and Read
Data Registers. This table also describes whether the
bit is a read or a write bit and the power-on reset state
(POR) of the bits. Figure 5 shows an example of parity
and word-length control.
Figure 2. Compatible CPOL and CPHA Timing Modes
Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal CapacitorsFigure 4. Write Configuration Register Example
Figure 5. Parity and Word-Length Control
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 1. Bit Descriptions
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Notice to High-Level Programmers:The UART follows
the SPI convention of providing a bidirectional data path
for writes and reads. Whenever the data is written, data
is also read back. This speeds operation over the SPI
bus, and the UART needs this speed advantage when
operating at high baud rates. In most high-level lan-
guages, such as C, there are commands for writing and
reading stream I/O devices such as the console or serial
port. In C specifically, there is a “PUTCHAR” command
that transmits a character and a “GETCHAR” command
that receives a character. If programmers were to write
direct write and read commands in C with no underlying
driver code, they would notice that a PUTCHAR com-
mand is really a PUTGETCHAR command. These C
commands assume some form of BIOS-level support for
these commands. The proper way to implement these
commands is to write driver code, usually in the form of
an assembly-language interrupt-service routine and a
callable routine used by high-level routines. This driver
handles the interrupts and manages the receive and
transmit buffers for the MAX3110E/MAX3111E. When a
PUTCHAR executes, this driver is called and it safely
buffers any characters received when the current
character is transmitted. When a GETCHAR executes, it
checks its own receive buffer before getting data from
the UART. See the C-language Outline of a MAX3110E/
MAX3111E Software Driver in Listing 1, which appears at
the end of this data sheet.
Listing 1 is a C-language outline of an interrupt-driven
software driver that interfaces to a MAX3110E/
MAX3111E, providing an intermediate layer between
the bit-manipulation subroutine and the familiar
PUTCHAR/GETCHARsubroutines.
The user must supply code for managing the transmit
and receive queues as well as the low-level hardware
interface itself. The interrupt control hardware must be
initialized before this driver is called.
Table 1. Bit Descriptions (continued)
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Write Configuration Register (D15, D14 = 1, 1)Configure the UART by writing a 16-bit word to the write
configuration register, which programs the baud rate,
data word length, parity enable, and enable of the 8-
word receive FIFO. In this mode, bits 15 and 14 of the
DIN configuration word are both required to be 1 in
order to enable the write configuration mode. Bits 13–0
of the DIN configuration word set the configuration of
the UART. Table 2 shows the bit assignment for the
write configuration register. The write configuration reg-
ister allows selection between normal UART timing and
IrDA timing, provides shutdown control, and contains
four interrupt mask bits.
Using the write configuration register clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed (T = 0), the
registers are updated when the transmission is over.
The write configuration register bits (FEN, SHDNi, IR,
ST, PE, L, B3–B0) take effect after the current transmis-
sion is over. The mask bits (TM, RM, PM, RAM) take
effect immediately after SCLK’s 16th rising edge.
Bits 15 and 14 of the DOUT write configuration (R and
T) are sent out of the MAX3110E/MAX3111E along with
14 trailing zeros. The use of the R and T bits is optional,
but ignore the 14 trailing zeros.
Warning!The UART requires stable crystal oscillator
operation before configuration (typically ~25ms after
power-up). Upon power-up, compare the write configu-
ration bits with the read configuration bits in a software
loop until both match. This ensures that the oscillator is
stable and that the UART is configured correctly.
Read Configuration Mode (D15, D14 = 0, 1)The read configuration mode is used to read back the
last configuration written to the UART. In this mode, bits
15 and 14 of the DIN configuration word are required to
be 0 and 1, respectively, to enable the read configura-
tion mode. Bits 13–1 of the DIN word should be zeros,
and bit 0 is the test bit to put the UART in test mode
(see the Test Modesection). Table 3 shows the bit
assignment for the read configuration register.
Test ModeThe device enters a test mode if bit 0 of the DIN config-
uration word equals one when doing a read configura-
tion. In this mode, if CS= 0, the RTSpin transmits a
clock that is 16-times the baud rate. The TX pin is low
as long as CSremains low while in test mode. Table 3
shows the bit assignment for the read configuration
register.
Write Data Register (D15, D14 = 1, 0)Use the write data register for transmitting to the TX-
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register, the DIN and
DOUT write data words are used simultaneously, and
bits 13–11 for both the DIN and DOUT write data words
are meaningless zeros. The DIN write data word con-
tains the data that is being transmitted, and the DOUT
write data word contains the data that is being received
from the RX FIFO. Table 4 shows the bit assignment for
the write data mode. To change the RTSpin’s output
state without transmitting data, set the TEbit high. If
performing a write data operation, the R bit will clear on
the falling edge of SCLK’s 16th clock pulse if no new
data is available.
Read Data Register (D15, D14 = 0, 0)Use the read data register for receiving data from the
RX FIFO. When using this register, bits 15 and 14 of
DIN are both required to be 0. Bits 13–0 of the DIN
read-data word should be zeros. Table 5 shows the bit
assignments for the read data mode. Reading data
clears the R bit and interrupt IRQ. If performing a read
data operation, the R bit will clear on the falling edge of
SCLKs 16th clock pulse if no new data is available.
MAX3110E/MAX3111E
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 2. WriteConfiguration (D15, D14 = 1, 1)
Notes:
bit 15: DOUTR = 1, Data is available to be read or is being read from the
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUTT = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bits 13–0: DOUTZeros
bits 15, 14: DIN1,1 = Write Configuration
bit 13: DINFEN= 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DINSHDNi = 1, Enter software shutdown.
SHDNi = 0, Exit software shutdown.
bit 11: DIN= 1, Transmit buffer empty interrupt is enabled.= 0, Transmit buffer empty interrupt is disabled.
bit 10: DIN= 1, Data available in the receive register or FIFO interrupt
is enabled.= 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DIN= 1, Parity bit high received interrupt is enabled.= 0, Parity bit received interrupt is disabled.
bit 8: DINRAM= 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM= 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DINIR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DINST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DINPE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DINL = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DINB3–B0 = XXXX, Baud-Rate Divisor Select Bits (see Table 6)
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
