MAX3110ECWI+G36 ,SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal Capacitorsfeatures an 8-word-deep receive FIFO that minimizes processor over-Ordering Informationhead and pro ..
MAX3110EENI+G36 ,SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal CapacitorsApplicationsPoint-of-Sale (POS) DevicesMAX3110EMAX3111EHandy-TerminalsSPIRS-232Telecom/Networking D ..
MAX3111ECWI ,SPI/MICROWIRE-Compatible UART and 【15kV ESDProtected RS-232 Transceivers with Internal CapacitorsApplicationsPoint-of-Sale (POS) Devices Typical Application CircuitHandy-TerminalsMAX3110ETelecom/N ..
MAX3111ECWI+G36 ,SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal CapacitorsFeaturesThe MAX3110E/MAX3111E combine a full-featured uni- • Integration Reduces Cost and Board Spa ..
MAX3111ECWI-T ,SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal CapacitorsElectrical Characteristics—MAX3110E(V = +4.5V to +5.5V, T = T to T , unless otherwise noted. Typica ..
MAX3111EEWI ,SPI/MICROWIRE-Compatible UART and 【15kV ESDProtected RS-232 Transceivers with Internal CapacitorsELECTRICAL CHARACTERISTICS—MAX3110E(V = +4.5V to +5.5V, T = T to T , unless otherwise noted. Typica ..
MAX6365PKA31+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX6366LKA29+ ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingApplicationsM A X6 36 7 LK A_ _-T -40°C to +85°C 8 SOT23Critical µP/µC Power Portable/Battery-M A ..
MAX6366LKA46-T ,4.75 V, SOT23, low-power, mP supervisory circuit with battery backup and chip-enable gatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify Low +1.2V Operating Supply Voltage (V or ..
MAX6366PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingELECTRICAL CHARACTERISTICS(V = +2.4V to +5.5V, V = +3.0V, CE IN = V , reset not asserted, T = -40°C ..
MAX6367LKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingApplicationsM A X6 36 7 LK A_ _-T -40°C to +85°C 8 SOT23Critical µP/µC Power Portable/Battery-M A ..
MAX6367PKA29+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingFeaturesThe MAX6365–MAX6368 supervisory circuits simplify ♦ Low +1.2V Operating Supply Voltage (V o ..
MAX3110ECWI+G36-MAX3110EENI+G36-MAX3111ECWI+G36-MAX3111ECWI-T-MAX3111EEWI-T
SPI/MICROWIRE-Compatible UART and ±15kV ESD-Protected RS-232 Transceivers with Internal Capacitors
General DescriptionThe MAX3110E/MAX3111E combine a full-featured uni-
versal asynchronous receiver/transmitter (UART) with
±15kV ESD-protected RS-232 transceivers and inte-
grated charge-pump capacitors into a single 28-pin
package for use in space-, cost-, and power-con-
strained applications. The MAX3110E/MAX3111E also
feature an SPI/QSPI™/MICROWIRE®-compatible serial
interface to save additional board space and microcon-
troller (µC) I/O pins.
A proprietary low-dropout output stage enables the
2-driver/2-receiver interface to deliver true RS-232 per-
formance down to VCC= +3V (+4.5V for MAX3110E)
while consuming only 600µA. The receivers remain
active in a hardware/software-invoked shutdown, allow-
ing external devices to be monitored while consuming
only 10µA. Each device is guaranteed to operate at up
to 230kbps while maintaining true EIA/TIA-232 output
voltage levels.
The MAX3110E/MAX3111E’s UART includes a crystal
oscillator and baud-rate generator with software-pro-
grammable divider ratios for all common baud rates
from 300baud to 230kbaud. The UART features an 8-
word-deep receive FIFO that minimizes processor over-
head and provides a flexible interrupt with four
maskable sources. Two control lines (one input and
one output) are included for hardware handshaking.
The UART and RS-232 functions can be used together
or independently since the two functions share only
supply and ground connections (the MAX3110E/
MAX3111E are hardware- and software-compatible
with the MAX3100 and MAX3222E).
ApplicationsPoint-of-Sale (POS) Devices
Handy-Terminals
Telecom/Networking Diagnostic Ports
Industrial Front-Panel Interfaces
Hand-Held/Battery-Powered Equipment
Benefits and FeaturesIntegration Reduces Cost and Board SpaceIntegrated RS-232 Transceiver and UART in a
Single 28-Pin Package
Guaranteed 230kbps Data Rate
SPI/QSPI/MICROWIRE-Compatible µC InterfaceInternal Charge-Pump Capacitors—No External
Components Required
Low-Power Operation Reduces Thermal DissipationTrue RS-232 Operation Down to VCC= +3V
(MAX3111E)Single-Supply Operation
+5V (MAX3110E)
+3.3V (MAX3111E)600µA Supply Current10µA Shutdown Supply Current with Receiver
Interrupt Active
Hardware/Software-Compatible with MAX3100 and
MAX3222E
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors8
RS-232
DB-9
SCLK
SPI
DIN
DOUT9345
IRQ
MAX3110E
MAX3111E
Typical Application Circuit
Ordering InformationQSPI is a trademark of Motorola, Inc.
MICROWIREis a registered trademark of National
Semiconductor Corp.
Ordering Information continued at end of data sheet.
Pin Configuration appears at end of data sheet.†Covered by U.S. Patent numbers 4,636,930; 4,679,134;
4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and
other patents pending.
PART
MAX3110ECWIMAX3110ECNI0°C to +70°C
0°C to +70°C
TEMP.
RANGE
PIN-
PACKAGE28 Wide SO
28 Plastic DIP
VCC
(V)MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Absolute Maximum Ratings
Electrical Characteristics—MAX3110E(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND (MAX3110E)........................................-0.3V to +6V
VCCto GND (MAX3111E).........................................-0.3V to +4V
V+ to GND (Note 1)..................................................-0.3V to +7V
V- to GND (Note 1)...................................................+0.3V to -7V
V+ to V- (Note 1)..................................................................+13V
Input Voltages to GND
CS, X1, CTS, RX, DIN, SCLK..................-0.3V to (VCC + 0.3V)
T_IN, SHDN...........................................................-0.3V to +6V
R_IN..................................................................................±25V
Output Voltage to GND
DOUT, RTS, TX, X2 .................................-0.3V to (VCC + 0.3V)
IRQ.......................................................................-0.3V to +6V
T_OUT ...........................................................................±13.2V
R_OUT.....................................................-0.3V to (VCC+ 0.3V)
TX, RTSOutput Current....................................................100mA
Short-Circuit Duration
X2, DOUT, IRQ(to VCCor GND).............................Continuous
T_OUT (to GND) .....................................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-pin Wide SO (derate 12.5mW/°C above +70°C) ...........1W
28-pin Plastic DIP (derate 14.3mW/°C above +70°C)....1.14W
Operating Temperature Ranges
MAX311_EC_ _ ..................................................0°C to +70°C
MAX311_EE_ _ ................................................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow)
PDIP lead(Pb)-free........................................................+225°C
PDIP containing lead(Pb)..............................................+240°C
Wide SO lead(Pb)-free..................................................+225°C
Wide SO containing lead(Pb).......................................+240°C
Note 1:V+ and V- can have maximum magnitudes of 7V, but their absolute difference should not exceed 13V.
SHDNi bit = 1
SHDNi bit = 0Input CurrentIIN125µAVX1= 0 or 5.5V
PARAMETERSYMBOLMINTYPMAXUNITSInput Low VoltageVIL10.2VCCV
Input High VoltageVIH10.7VCCV
Supply Current with Hardware
and Software ShutdownICCSHDN(H+ S)320µA
Input CapacitanceCIN15pF
Input High VoltageVIH20.7VCCV
Input Low VoltageVIL20.3VCCV
Supply CurrentICC0.62mA
Supply Current with Hardware
ShutdownICCSHDN(H)0.481mA
Input HysteresisVHYST2250mV
Input Leakage CurrentILKG1±1µA
Input CapacitanceCIN25pF
Input High VoltageVIH32.4
Input Low VoltageVIL30.8V
Transmitter Input HysteresisVHYST3500mV
CONDITIONSSHDN= GND, SHDNi bit = 1 (Note 4)
VCC= 5V
SHDN= VCC, no load
SHDN= GND (Note 3)
DC CHARACTERISTICS (VCC= +5V, TA= +25°C)
UARTOSCILLATOR INPUT (X1)
UARTLOGICINPUTS(DIN, SCLK, CS,CTS, RX))
RS-232 LOGICINPUTS(T_IN, SHDN))
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
±25
Electrical Characteristics—MAX3110E (continued)(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER500VHYST4Input Hysteresis0.8VIL4Input Low Voltage2.4VIH4Input High Voltage= +25°CkΩ357RINInput Resistance= +25°C, VCC= 5V= +25°C, VCC= 5V-25+25Input Voltage Range
0.9ISINK= 25mA; TX onlyOutput Low VoltageVOL20.4VISINK = 4mA; DOUT, RTS
VCC - 0.5ISOURCE= 10mA; TX only
IEC 1000-4-2 Contact Discharge
±15IEC 1000-4-2 Air Discharge
SCLK Fall to DOUT ValidtDO100nsCLOAD= 100pFto SCLK Hold TimetCSH0ns
Output Low VoltageVOL10.4V
Output High VoltageVOH1VCC- 0.6V±0.05±10µA
Output Voltage Swing5±5.4V
Output ResistanceRO30010MΩ
Output Short-Circuit Current±60mA
Output Leakage CurrentILKG2±25µA
ESD Protection
±15
Output Leakage CurrentILKG3±1µA
Output High VoltageVOH2VCC - 0.5V
Output CapacitanceCOUT15pF
Output Leakage CurrentILKG4±1µA
Output Low VoltageVOL30.4V
Output CapacitanceCOUT25pFLow to DOUT ValidtDV100nsHigh to DOUT Tri-StatetTR100nsto SCLK Setup TimetCSS 100ns
DOUT only, CS= VCC
ISINK= 1.6mA
ISOURCE= 1mA
3kΩload on all transmitter outputs
VCC = V+ = V- = 0, VOUT= ±2V
ISOURCE= 5mA; DOUT, RTS
VCC= 0 or 5.5V, VOUT= ±12V,
transmitters disabled
VIRQ= 5.5V
ISINK= 4mA
Human Body Model
CLOAD= 100pF
CLOAD= 100pF, RCS= 10kΩ
RS-232 RECEIVER INPUTS (R_IN)
RS-232 ESDPROTECTION (R_IN, T_OUT)
RS-232 RECEIVER OUTPUTS (R_OUT)
RS-232 TRANSMITTER OUTPUTS (T_OUT)
UARTOUTPUTS (DOUT, TX, RTS)
UARTIRQ
OUTPUTS (IRQ= open drain)
UARTACTIMING
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Electrical Characteristics—MAX3110E (continued)(VCC= +4.5V to +5.5V, TA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +5V, TA= +25°C.) (Note 2)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER0tDHDIN to SCLK Hold Time100tDSDIN to SCLK Setup Time238tCPSCLK Period100tCLSCLK Low Time100tCHSCLK High Time100tCS0SCLK Rising Edge to CSFalling
TX, RTS, DOUT; CL= 100pFns10trOutput Rise Time200tCSWCS High Pulse Width200tCS1CSRising Edge to SCLK Rising
Edge
TX, RTS, DOUT, IRQ; CL= 100pFns10tfOutput Fall Time= 150pF to
2500pF430
V/µs
Receiver Skew|tPHL- tPLH| 50ns= 150pF to
1000pF
Transmitter Skew|tPHL- tPLH| 100ns
tPLH150ns
Transition-Region Slew Rate
Maximum Data Rate250kbps
Receiver Propagation DelaytPHL150
(Note 5)= 150pF
VCC= 5V,= 3kΩto 7kΩ,= +25°C,
measured from
+3V to -3V or
-3V to +3V= 3kΩ, CL= 1000pF,
one transmitter switching
Receiver input to receiver output
RS-232 ACTIMING
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Human Body Model
SHDN= GND (Note 3)
SHDN= VCC, no load
SHDN= GND SHDNi bit = 1 (Note 4)
CONDITIONS5CIN2Input Capacitance±1ILKG1Input Leakage Current165VHYST2Input Hysteresis0.180.4ICCSHDN(H)Supply Current with Hardware
Shutdown0.451.4ICCSupply Current0.3VCCVIL2Input Low Voltage0.7VCCVIH2Input High Voltage5CIN1120ICCSHDN(H+ S)Supply Current with Hardware
and Software Shutdown0.7VCCVIH1Input High Voltage0.2VCCVIL1Input Low Voltage
UNITSMINTYPMAXSYMBOLPARAMETERVX1= 0 or 3.6VµA25IIN1Input Current2
SHDNi bit = 0
SHDNi bit = 1
Electrical Characteristics—MAX3111E(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)= +25°C, VCC= 3.3V
VCC= 3.3V500VHYST4Input Hysteresis0.6VIL4Input Low Voltage2.4VIH4Input High Voltage±0.01±1IIN3Input Leakage Current500VHYST3Transmitter Input Hysteresis0.8VIL3Input Low Voltage2.0VIH3Input High Voltage= +25°CkΩ357RINInput Resistance= +25°C, VCC= 3.3V-25+25Input Voltage Range
±15
ESD Protection IEC 1000-4-2 Air Discharge±15
IEC 1000-4-2 Contact Discharge±8
Input Capacitance
DC CHARACTERISTICS (VCC= 3.3V, TA= +25°C)
UARTOSCILLATOR INPUT (X1)
UART LOGICINPUTS(DIN, SCLK, CS, RX))
RS-232 LOGICINPUTS(T_IN, SHDN)
RS-232 RECEIVER INPUTS (R_IN)
RS-232 ESDPROTECTION (R_IN, T_OUT)
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Electrical Characteristics—MAX3111E (continued)(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)
Output Fall Timetf10nsTX, RTS, DOUT, IRQ; CLOAD= 100pFRising Edge to SCLK Rising
EdgetCS1200nsHigh Pulse WidthtCSW200ns
Output Rise Timetr10nsTX, RTS, DOUT; CLOAD= 100pF
SCLK Rising Edge to CSFallingtCS0100ns
SCLK High TimetCH100ns
SCLK Low TimetCL100ns
SCLK PeriodtCP238ns
SCLK Fall to DOUT ValidtDO100ns
DIN to SCLK Setup TimetDS100ns
DIN to SCLK Hold TimetDH0ns
CLOAD= 100pFto SCLK Hold TimetCSH0nsLow to DOUT ValidtDV100nsHigh to DOUT Tri-StatetTR100nsto SCLK Setup TimetCSS 100ns
CLOAD= 100pF
CLOAD= 100pF, RCS= 10kΩ
0.9ISINK= 25mA, TX onlyOutput Low VoltageVOL20.4V
±25
VCC - 0.5
ISINK = 4mA; DOUT, RTS
Output Low VoltageVOL10.4V
Output High VoltageVOH1VCC- 0.6V
Output Voltage Swing±5±5.4V
Output ResistanceRO30010MΩ
Output Short-Circuit Current±60mA
Output Leakage CurrentILKG2µA
ISOURCE= 10mA, TX only
PARAMETERSYMBOLMINTYPMAXUNITSOutput Leakage CurrentILKG3±1µA
Output High VoltageVOH2VCC - 0.5V
Output CapacitanceCOUT15pF
Output Leakage CurrentILKG4±1µA
Output Low VoltageVOL30.4V
Output CapacitanceCOUT25pF
DOUT only; CS= VCC
ISINK= 1.6mA
ISOURCE= 1mA
3kΩload on all transmitter outputs
VCC = V+ = V- = 0, VOUT= ±2V
ISOURCE= 5mA; DOUT, RTS
VCC= 0 or 3.6V, VOUT= ±12V,
transmitters disabledIRQ= 3.6V
ISINK= 4mA
CONDITION
RS-232 RECEIVER OUTPUTS (R_OUT)
RS-232 TRANSMITTER OUTPUTS (T_OUT)
UARTOUTPUTS (DOUT, TX, RTS)
UARTIRQ OUTPUT (IRQ= open drain)
UARTACTIMING
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Electrical Characteristics—MAX3111E (continued)(VCC= +3.0V to +3.6V, VA = TMINto TMAX, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
VCC= +3.3V, TA= +25°C.) (Note 2)
Note 2:All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground unless otherwise noted.
Note 3:ICCSHDN(H)represents a hardware-only shutdown. In hardware shutdown, the UART is in normal operation and the charge
pumps for the RS-232 transmitters are shut down.
Note 4:ICCSHDN(H+S)represents a simultaneous software and hardware shutdown in which the UART and charge pumps are
shut down.
Note 5:Transmitter skew is measured at the transmitter zero cross points.
Receiver input to receiver output= 3kΩ, CL= 1000pF,
one-transmitter switching
VCC= 3.3V,= 3kΩto 7kΩ,= +25°C,
measured from
+3V to -3V or
-3V to +3V= 150pF
(Note 5)
150tPHLReceiver Propagation Delay
kbps250Maximum Data Rate
V/µs
Transition-Region Slew Rate150tPLH= 150pF to
1000pF200|tPHL- tPLH| Transmitter Skew100|tPHL- tPLH| Receiver Skew
430CL= 150pF to
2500pF
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
RS-232 ACTIMING
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors10002000
250kbps
RS-232 TRANSCEIVER SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX3110E/TOC09
SUPPLY CURRENT (mA)
TRANSMITTER 1 AT DATA RATE
TRANSMITTER 2 AT DATA RATE
3kΩ + CL16
120kbps
20kbps10002000300040005000
RS-232 TRANSMITTER SLEW RATE
vs. LOAD CAPACITANCEMAX3110E/TOC11
SLEW RATE (V/
TRANSMITTER 1 AT 250kbps
3kΩ + CL
-SLEW
+SLEW
RS-232 TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
MAX3110E/TOC07
LOAD CAPACITANCE (pF)
TRANSMITTER OUTPUT VOLTAGE (V)
TRANSMITTER 1 AT 250kbps
TRANSMITTER 2 AT 15.6kbps
3kΩ + CL
VOUT-
VOUT+
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
UART SUPPLY CURRENT vs. TEMPERATURE
MAX3110E-01
TEMPERATURE (°C)
SUPPLY CURRENT (
MAX3110E, VCC = +5V
MAX3111E, VCC = +3.3V
1.8432MHz CRYSTAL
TRANSMITTING AT 115.2kbps
UART SHUTDOWN CURRENT
vs. TEMPERATURE
MAX3110E-02
TEMPERATURE (°C)
SHUTDOWN CURRENT (
1.8432MHz CRYSTAL
MAX3110E, VCC = +5V
MAX3111E, VCC = +3.3V
10010k1000100k1M
UART SUPPLY CURRENT
vs. BAUD RATEMAX3110E-03
BAUD RATE (bps)
SUPPLY CURRENT (
1.8432MHz
CRYSTAL
MAX3110E
MAX3111E
+5V
STANDBY
+5V
TRANSMITTING
+3V
TRANSMITTING
+3V
STANDBY
UART SUPPLY CURRENT vs.
EXTERNAL CLOCK FREQUENCY
MAX3110E-04
EXTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT (
MAX3110E
VCC = +5V
MAX3111E
VCC = +3.3V0.20.10.60.70.81.0
MAX3111E
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = +3.3V)MAX3110E-05
VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
RTS
DOUT
MAX3110E
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = +5V)
MAX3110E-06
VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
RTS
DOUT
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Pin DescriptionPositive terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.C2+24
Negative terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.C2-25
-5.5V generated by the internal charge pump. Do not make any connection to this terminal.V-26
GroundGND27
RS-232 Transmitter Output 2T2OUT28
UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.IRQ19
Hardware Shutdown Input. Drive SHDN low to shut down the RS-232 transmitters and charge pump. Drive
high for normal operation.SHDN20
+5.5V generated by the internal charge pump. Do not make any connection to this terminal.V+21
Positive terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to
this terminal.C1+22
Negative terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to
this terminal.C1-23
SPI/MICROWIRESerial-Data Input. Schmitt-trigger Input.DIN15
SPI/MICROWIRESerial-Data Output. High impedance when CSis high.DOUT16
SPI/MICROWIRESerial-Clock Input. Schmitt-trigger input.SCLK17
UART Active-Low Chip-Select Input. DOUT goes high impedance when CSis high. IRQ, TX, and RTSare
always active. Schmitt-trigger input.CS18
UART Asynchronous Serial-Data (transmitter) OutputTX14
UART Crystal Connection. Leave X2 unconnected when using an external CMOS clock. See the Crystals,
Oscillators, and Ceramic Resonatorssection.X29
UART Crystal Connection. X1 also serves as an external CMOS clock input. See theCrystals, Oscillators,
and Ceramic Resonatorssection.X110
UART Clear-to-Send Active-Low Input. Read via the CTS bit. CTS11
UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Also used to control the driver enable
in RS-485 networks.RTS12
UART Asynchronous Serial-Data (receiver) Input. The serial information received from the RS-232 receiver.
A transition on RX while in shutdown generates an interrupt (Table 1).RX13
RS-232 Receiver Output 1, TTL/CMOSR1OUT5
RS-232 Receiver Input 1R1IN6
RS-232 Transmitter Output 1T1OUT7
Positive Supply VoltageVCC8
RS-232 Transmitter lnput 1, TTL/CMOST1IN4
RS-232 Transmitter lnput 2, TTL/CMOST2IN3
PINRS-232 Receiver Output 2, TTL/CMOSR2OUT2
RS-232 Receiver Input 2R2IN1
FUNCTIONNAME
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Detailed DescriptionThe MAX3110E/MAX3111E contain an SPI/QSPI/MICROWIRE-
compatible UART and an RS-232 transceiver with two
drivers and two receivers. The UART is compatible with
SPI and QSPI for CPOL = 0 and CPHA = 0. The UART
supports data rates up to 230kbaud for standard UART
bit streams as well as IrDA and includes an 8-word
receive FIFO. Also included is a 9-bit-address recogni-
tion interrupt.
The RS-232 transceiver has electrostatic discharge
(ESD) protection on the transmitter outputs and the
receiver inputs. The internal charge-pump capacitors
minimize the number of external components required.
The RS-232 transceivers meet EIA/TIA-232 specifica-
tions for VCCdown to the minimum supply voltage and
are guaranteed to operate for data rates up to 250kbps.
The UART and RS-232 functions operate as one device
or independently since the two functions share only
supply and ground connections.
UARTThe universal asynchronous receiver transmitter
(UART) interfaces the SPI/QSPI/MICROWIRE-compati-
ble synchronous serial data from a microprocessor (µP)
to asynchronous, serial-data communication ports (RS-
232, IrDA). Figure 1 shows the MAX3110E/MAX3111E
functional diagram. Included in the UART function is an
SPI/QSPI/MICROWIREinterface, a baud-rate generator,
SPI
INTERFACE
INTERRUPT
LOGICRX SHIFT REGISTERTX SHIFT REGISTER
T2OUTT2INRX BUFFERTX BUFFERRX FIFO9
INTERNAL5k5k
INTERNAL
INTERNAL
INTERNAL
T1OUT
R2IN
T1IN
R2OUT
R1IN
GND
SHDN
IRQ
R1OUT
C1+
C1-
C2+
C2-
VCC
CTS
RTS
BAUD-RATE
GENERATOR
DOUT
SCLK
DIN
I/O
CHARGE
PUMP
MAX3110E/MAX3111E
Figure 1. MAX3110E/MAX3111E Functional Diagram
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
SPI InterfaceThe MAX3110E/MAX3111E are compatible with SPI,
QSPI (CPOL = 0, CPHA = 0), and MICROWIREserial-
interface standards (Figure 2). The MAX3110E/
MAX3111E have a unique full-duplex-only architecture
that expects a 16-bit word for DIN and simultaneously
produces a 16-bit word for DOUT regardless of which
read/write register is used. The DIN stream is moni-
tored for its first two bits to tell the UART the type of
data transfer being executed (see the Write
Configuration Register, Read Configuration Register,
Write Data Register, and Read Data Register sections).
DIN (MOSI) is latched on SCLK’s rising edge. DOUT
(MISO) should be read into the µP on SCLK’s rising
edge. The first bit (bit 15) of DOUT transitions on CS’s
falling edge, and bits 14–0 transition on SCLK’s falling
edge. Figure 3 shows the detailed serial timing specifi-
cations for the synchronous SPI port.
Only 16-bit words are expected. If CSgoes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on
CS’s rising edge. Every time CSgoes low, a new 16-bit
stream is expected. An example of using the Write
Configuration Register is shown in Figure 4.
Table 1 describes the bits located in the Write Config-
uration, Read Configuration, Write Data, and Read
Data Registers. This table also describes whether the
bit is a read or a write bit and the power-on reset state
(POR) of the bits. Figure 5 shows an example of parity
and word-length control.
SCLK
SCLK
SCLK
SCLK
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
COMPATIBLE
WITH MAX3110E/MAX3111E
NOT COMPATIBLE
WITH MAX3110E/MAX3111E
DINMSB1314121110987654321LSB
DOUTMSB1314121110987654321LSB
Figure 2. Compatible CPOL and CPHA Timing Modes
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSOtCSStCL
tDS
tDH
tDV
tCH
tDOtTR
tCSHtCS1
Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
SCLK
DIN
DOUT131211109876543210
DATA
UPDATED1FENSHDNTMRMPMRAMIRSTPELB3B2B1B000000000000000
Figure 4. Write Configuration Register Example
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIMESTARTD1D2D3D4D5D6PtSTOPSTOPIDLE
IDLE
PE = 1, L = 0STARTD1D2D3D4D5D6D7PtSTOPSTOPIDLE
IDLE
PE = 0, L = 1STARTD1D2D3D4D5D6STOPSTOPIDLE
IDLE
PE = 0, L = 0STARTD1D2D3D4D5D6D7STOPSTOPIDLE
Figure 5. Parity and Word-Length Control
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Table 1. Bit DescriptionsPE
POR
STATEwrite
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit
as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be
received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3110E/MAX3111E
do not calculate parity.PEreadReads the value of the Parity-Enable bit.PMwriteMask for Pr bit. IRQis asserted if PM= 1 and Pr = 1 (Table 7).
DESCRIPTION0000Prread
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data
(see the 9-Bit Networkssection).readReads the value of the IR bit.
BIT
TYPEwrite
B0–B3writeBaud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
B0–B3readBaud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
BIT
NAMEBit to set the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1).readReads the value of the L bit.write
Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit net-
works, the MAX3110E/MAX3111E do not calculate parity. If PE = 0, then this bit (Pt) is ignored
in transmit mode (see the 9-Bit Networkssection).
D0r–D7rreadEight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is
always 0.
FENwriteFIFO Enable. Enables the receive FIFO when FEN= 0. When FEN= 1, FIFO is disabled.
FENreadFIFO-Enable Readback. FEN’s state is read.writeEnables the IrDA timing mode when IR = 1.
change
XXXXXXXX
CTSreadClear-to-Send-Input. Records the state of the CTSpin (CTS bit = 0 implies CTSpin = logic
high).
D0t–D7twriteTransmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.PMreadReads the value of the PMbit (Table 7).Rread
Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being
read from the receive register or FIFO. If performing a Read Data or Write Data operation, the R
bit will clear on the falling edge of SCLK's 16th pulse if no new data is available.RMwriteMask for R bit. IRQis asserted if RM= 1 and R = 1 (Table 7).RMreadReads the value of the RMbit (Table 7).RAMwriteMask for RA/FE bit. IRQis asserted if RAM= 1 and RA/FE = 1 (Table 7).RAMreadReads the value of the RAMbit (Table 7).RTSwriteRequest-to-Send Bit. Controls the state of the RTSoutput. This bit is reset on power-up (RTS
bit = 0 sets the RTSpin = logic high).
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Notice to High-Level Programmers:The UART follows
the SPI convention of providing a bidirectional data path
for writes and reads. Whenever the data is written, data
is also read back. This speeds operation over the SPI
bus, and the UART needs this speed advantage when
operating at high baud rates. In most high-level lan-
guages, such as C, there are commands for writing and
reading stream I/O devices such as the console or serial
port. In C specifically, there is a “PUTCHAR” command
that transmits a character and a “GETCHAR” command
that receives a character. If programmers were to write
direct write and read commands in C with no underlying
driver code, they would notice that a PUTCHAR com-
mand is really a PUTGETCHAR command. These C
commands assume some form of BIOS-level support for
these commands. The proper way to implement these
commands is to write driver code, usually in the form of
an assembly-language interrupt-service routine and a
callable routine used by high-level routines. This driver
handles the interrupts and manages the receive and
transmit buffers for the MAX3110E/MAX3111E. When a
PUTCHAR executes, this driver is called and it safely
buffers any characters received when the current
character is transmitted. When a GETCHAR executes, it
checks its own receive buffer before getting data from
the UART. See the C-language Outline for a MAX3110E/
MAX3111E Software Driver in Listing 1, which appears
at the end of this data sheet.
Listing 1 is a C-language outline of an interrupt-driven
software driver that interfaces to a MAX3110E/
MAX3111E, providing an intermediate layer between
the bit-manipulation subroutine and the familiar
PUTCHAR/GETCHARsubroutines.
The user must supply code for managing the transmit
and receive queues as well as the low-level hardware
interface itself. The interrupt control hardware must be
initialized before this driver is called.
Table 1. Bit Descriptions (continued)
POR
STATEDESCRIPTIONBIT
TYPE
BIT
NAMESHDNiwrite
Software-Shutdown Bit. Enter software shutdown with a WriteConfiguration where SHDNi = 1.
Software shutdown takes effect after CSgoes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a WriteConfiguration where SHDNi = 0. The
oscillator restarts typically within 50ms of CSgoing high. RTS and CTS are unaffected. Refer
to the Pin Description for hardware shutdown (SHDNinput).SHDNoread
Shutdown Read-Back Bit. The ReadConfiguration register outputs SHDNo = 1 when the
UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is
sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This
bit is also set immediately when the device is shut down through the SHDNpin.RA/FEread
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next prop-
erly framed character independent of the FIFO being enabled. When the device wakes up, it
is likely that a framing error will occur. This error is cleared with a WriteConfiguration. The FE
bit is not cleared on a ReadDataoperation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit. STwriteTransmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.STreadReads the value of the ST bit.TMwriteMask for T Bit. IRQis asserted if TM= 1 and T = 1 (Table 7).TMreadReads the value of the TMbit (Table 7).TreadTransmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.TEwriteTransmit-Enable Bit. If TE= 1, then only the RTSpin is updated on CS’s rising edge. The con-
tents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE= 0.
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
Write Configuration Register (D15, D14 = 1, 1)Configure the UART by writing a 16-bit word to the write
configuration register, which programs the baud rate,
data word length, parity enable, and enable of the 8-
word receive FIFO. In this mode, bits 15 and 14 of the
DIN configuration word are both required to be 1 in
order to enable the write configuration mode. Bits 13–0
of the DIN configuration word set the configuration of
the UART. Table 2 shows the bit assignment for the
write configuration register. The write configuration reg-
ister allows selection between normal UART timing and
IrDA timing, provides shutdown control, and contains
four interrupt mask bits.
Using the write configuration register clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed (T = 0), the
registers are updated when the transmission is over.
The write configuration register bits (FEN, SHDNi, IR,
ST, PE, L, B3–B0) take effect after the current transmis-
sion is over. The mask bits (TM, RM, PM, RAM) take
effect immediately after SCLK’s 16th rising edge.
Bits 15 and 14 of the DOUT write configuration (R and
T) are sent out of the MAX3110E/MAX3111E along with
14 trailing zeros. The use of the R and T bits is optional,
but ignore the 14 trailing zeros.
Warning!The UART requires stable crystal oscillator
operation before configuration (typically ~25ms after
power-up). Upon power-up, compare the write configu-
ration bits with the read configuration bits in a software
loop until both match. This ensures that the oscillator is
stable and that the UART is configured correctly.
Read Configuration Register (D15, D14 = 0, 1)The read configuration register is used to read back the
last configuration written to the UART. In this register,
bits 15 and 14 of the DIN configuration word are
required to be 0 and 1, respectively, to enable the read
configuration mode. Bits 13–1 of the DIN word should
be zeros, and bit 0 is the test bit to put the UART in test
mode (see the Test Modesection). Table 3 shows the
bit assignment for the read configuration register.
Test ModeThe device enters a test mode if bit 0 of the DIN config-
uration word equals one when doing a read configura-
tion. In this mode, if CS= 0, the RTSpin transmits a
clock that is 16-times the baud rate. The TX pin is low
as long as CSremains low while in test mode. Table 3
shows the bit assignment for the read configuration
register.
Write Data Register (D15, D14 = 1, 0)Use the write data register for transmitting to the TX-
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register, the DIN and
DOUT write data words are used simultaneously, and
bits 13–11 for both the DIN and DOUT write data words
are meaningless zeros. The DIN write data word con-
tains the data that is being transmitted, and the DOUT
write data word contains the data that is being received
from the RX FIFO. Table 4 shows the bit assignment for
the write data mode. To change the RTSpin’s output
state without transmitting data, set the TEbit high. If
performing a write data operation, the R bit will clear on
the falling edge of SCLK’s 16th clock pulse if no new
data is available.
Read Data Register (D15, D14 = 0, 0)Use the read data register for receiving data from the
RX FIFO. When using this register, bits 15 and 14 of
DIN are both required to be 0. Bits 13–0 of the DIN
read-data word should be zeros. Table 5 shows the bit
assignments for the read data mode. Reading data
clears the R bit and interrupt IRQ. If performing a read
data operation, the R bit will clear on the falling edge of
SCLKs 16th clock pulse if no new data is available.
MAX3110E/MAX3111ESPI/MICROWIRE-Compatible UART
and ±15kV ESD-Protected RS-232
Transceivers with Internal Capacitors
RAM
SHDNi
FEN
14DIN1
DOUTR
BIT
Table 2. Write Configuration (D15, D14 = 1, 1)
Notes:
bit 15: DOUTR = 1, Data is available to be read or is being read from the
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUTT = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bits 13–0: DOUTZeros
bits 15, 14: DIN1,1 = Write Configuration
bit 13: DINFEN= 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DINSHDNi = 1, Enter software shutdown.
SHDNi = 0, Exit software shutdown.
bit 11: DIN= 1, Transmit buffer empty interrupt is enabled.= 0, Transmit buffer empty interrupt is disabled.
bit 10: DIN= 1, Data available in the receive register or FIFO interrupt
is enabled.= 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DIN= 1, Parity bit high received interrupt is enabled.= 0, Parity bit received interrupt is disabled.
bit 8: DINRAM= 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM= 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DINIR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DINST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DINPE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DINL = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DINB3–B0 = XXXX, Baud-Rate Divisor Select Bits (see Table 6)
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
