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Partno	Mfg	Dc	Qty	Available	Descript
MAX3107ETG+	N/A	N/a	2500	avai	SPI/I²C UART with 128-Word FIFOs
MAX3107ETG+ |MAX3107ETG	MAXIM	N/a	100	avai	SPI/I²C UART with 128-Word FIFOs
MAX3107ETG+T	N/A	N/a	2500	avai	SPI/I²C UART with 128-Word FIFOs

MAX3107ETG+ ,SPI/I²C UART with 128-Word FIFOsTABLE OF CONTENTS (CONTINUED)Forced Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . ..
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MAX6363LUT31-T ,3.15 V, SOT23, low-power, mP supervisory circuit with battery backupFeaturesThe MAX6361–MAX6364 supervisory circuits reduce the  Low +1.2V Operating Supply Voltage co ..
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MAX6365HKA46+T ,SOT23, Low-Power µP Supervisory Circuits with Battery Backup and Chip-Enable GatingApplicationsM A X6 36 7 LK A_ _-T -40°C to +85°C 8 SOT23Critical µP/µC Power Portable/Battery-M A ..

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MAX3107ETG+-MAX3107ETG+T
SPI/I²C UART with 128-Word FIFOs
Functional Diagram and Ordering Information appear at
end of data sheet.
General Description
The MAX3107 is an advanced universal asynchronous
receiver-transmitter (UART) with 128 words each of
receive and transmit first-in/first-out (FIFO) that can be
controlled through I2C or high-speed SPI. The 2x and
4x rate modes allow a maximum of 24Mbps data rates. phase-locked loop (PLL), prescaler, and fractional
baud-rate generator allow for high-resolution baud-rate
programming and minimize the dependency of baud rate
on reference clock frequency.
Autosleep and shutdown modes help reduce power con-
sumption during periods of inactivity. A low 640µA (typ)
supply current and tiny 24-pin TQFN (3.5mm x 3.5mm)
package make the MAX3107 ideal for low-power portable
devices.
Integrated logic-level translation on the controller and
transceiver (RX/TX and RTS/CTS) interfaces enable use
with a wide selection of RS-232/RS-485 transceivers.
Automatic hardware and software flow control with select-
able FIFO interrupt triggering offloads low-level activity
from the host controller. Automatic half-duplex transceiver
control with programmable setup and hold times allow
the MAX3107 to be used in high-speed applications, for
example Profibus-DP.
The MAX3107 is ideal for use in portable devices,
industrial, and automotive applications. The MAX3107 is
available in a 24-pin SSOP package and a 24-pin TQFN
package. It is specified over the -40°C to +85°C extended
ambient temperature range.
Applications●Portable Devices●Industrial Control Systems●Fieldbus Networks●Automotive Infotainment Systems●Medical Systems●Point-of-Sale Systems●HVAC or Building Control
Beneits and Features●Bridges an SPI/MICROWIRE or I2C Microprocessor
Bus to an Asynchronous Interface Such as RS-485,
RS-232, or IrDASMSIR- and MIR-Compliant IrDA Encoder/DecoderLine Noise Indication Ensures Data Link Integrity●Saves Up to 23% Board Space24-Pin TQFN (3.5mm x 3.5mm) and SSOP Packages ●Integrated Internal Oscillator Eliminates the Need for
an External Oscillator and Reduces the BOM Cost Integrated PLL and Divider ●Fast Data Rates Allow Maximum System Flexibility
Across Interface Standards24Mbps (max) Data Rate Fractional Baud-Rate Generator SPI Up to 26MHz Clock Rate ●Deep, 128-Word Buffer and Automated Control
Features Help Offload Activity on the MicrocontrollerAuto Transceiver Direction Control Half-Duplex Echo Suppression Auto RTS/CTS and XON/XOFF Flow Control 9-Bit Multidrop-Mode Data Filtering -Special Character Detection -GPIO-Based Character Detection -Four Flexible GPIOs ●Power Management Control Features Minimize
Power Consumption for Portable Applications+2.35V to +3.6V Supply Range -Low 640μA (typ) Supply Current at 1Mbaud and
20MHz Clock Shutdown and Autosleep Modes-Low 20μA (typ) Shutdown Power ●Logic-Level Translation on the Controller and
Transceiver Interfaces (Down to 1.7V) Ensure
System Compatibility●Register Compatible with MAX3108, MAX3109,
MAX14830
MAX3107SPI/I2C UART with 128-Word FIFOs
EVALUATION KIT AVAILABLE
MAX3107SPI/I2C UART with 128-Word FIFOs
TABLE OF CONTENTS
General Description............................................................................1
Applications ..................................................................................1
Benefits and Features ..........................................................................1
Absolute Maximum Ratings......................................................................6
Package Thermal Characteristics (Note 1) ..........................................................6
DC Electrical Characteristics.....................................................................6
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test Circuits/Timing Diagrams...................................................................10
Typical Operating Characteristics .................................................................11
Pin Configurations ............................................................................12
Pin Descriptions..............................................................................12
Register Map ................................................................................14
Detailed Description...........................................................................15
Register Set................................................................................15
Receive and Transmit FIFOs ..................................................................15
Transmitter Operation........................................................................15
Receiver Operation..........................................................................16
Line Noise Indication.........................................................................16
Clocking and Baud-Rate Generation ............................................................16
Crystal Oscillator .........................................................................17
External Clock Source.....................................................................17
PLL and Predivider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fractional Baud-Rate Generator................................................................17
2x and 4x Rate Modes .......................................................................18
Multidrop Mode ..........................................................................19
Auto Data Filtering in Multidrop Mode.........................................................19
Auto Transceiver Direction Control..............................................................19
Echo Suppression...........................................................................20
Auto Hardware Flow Control...................................................................20
AutoRTS Control .........................................................................20
AutoCTS Control .........................................................................21
Auto Software (XON/XOFF) Flow Control ........................................................21
Transmitter Flow Control ...................................................................22
Receiver Flow Control .....................................................................22
FIFO Interrupt Triggering .....................................................................22
Low-Power Standby Modes ...................................................................22
MAX3107SPI/I2C UART with 128-Word FIFOs
Forced Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Autosleep Mode..........................................................................22
Shutdown Mode..........................................................................22
Power-Up and IRQ................................................................22
Interrupt Structure...........................................................................23
Interrupt Enabling.........................................................................23
Interrupt Clearing.........................................................................23
Detailed Register Descriptions.................................................................23
Serial Controller Interface ......................................................................44
SPI Interface...............................................................................44
SPI Single-Cycle Access...................................................................44
SPI Burst Access.........................................................................442C Interface ...............................................................................44
START, STOP, and Repeated START Conditions................................................45
Slave Address ...........................................................................45
Bit Transfer..............................................................................45
Single-Byte Write.........................................................................45
Burst Write..............................................................................45
Single-Byte Read.........................................................................46
Burst Read..............................................................................47
Acknowledge ............................................................................47
Applications Information........................................................................47
Startup and Initialization......................................................................47
Low-Power Operation........................................................................48
Interrupts and Polling ........................................................................48
Logic-Level Translation.......................................................................48
Connector Pin Sharing .......................................................................49
RS-232 5x3 Application ......................................................................49
Typical Application Circuit ......................................................................49
Chip Information..............................................................................49
Ordering Information ..........................................................................49
Functional Diagram ...........................................................................51
Package Information ..........................................................................51
Revision History..............................................................................52
TABLE OF CONTENTS (CONTINUED)
MAX3107SPI/I2C UART with 128-Word FIFOs
LIST OF TABLES
Table 1. StopBits Truth Table....................................................................33
Table 2. Length[1:0] Truth Table..................................................................33
Table 3. SwFlow[3:0] Truth Table.................................................................38
Table 4. PLLFactor[1:0] Selection Guide ............................................................41
Table 5. I2C Address Map ......................................................................45
LIST OF FIGURES
Figure 1. I2C Timing Diagram ...................................................................10
Figure 2. SPI Timing Diagram ...................................................................10
Figure 3. Transmit FIFO Signals .................................................................15
Figure 4. Receive Data Format ..................................................................16
Figure 5. Midbit Sampling ......................................................................16
Figure 6. Receive FIFO ........................................................................17
Figure 7. Clock Selection Diagram................................................................17
Figure 8. 2x and 4x Baud Rates .................................................................18
Figure 9. Auto Transceiver Direction Control........................................................19
Figure 10. Setup and Hold Times in Auto Transceiver Direction Control ..................................20
Figure 11. Half-Duplex with Echo Suppression ......................................................20
Figure 12. Echo Suppression Timing..............................................................21
Figure 13. Simplified Interrupt Structure ...........................................................23
Figure 14. PLL Signal Path ......................................................................41
Figure 15. SPI Single-Cycle Read................................................................44
Figure 16. SPI Single-Cycle Write................................................................44
Figure 17. I2C START, STOP, and Repeated START Conditions ........................................45
Figure 18. Write Byte Sequence .................................................................46
Figure 19. Burst Write Sequence.................................................................46
Figure 20. Read Byte Sequence .................................................................46
Figure 21. Burst Read Sequence.................................................................47
Figure 22. Acknowledge........................................................................47
Figure 23. Startup and Initialization Flowchart ......................................................48
Figure 24. Logic-Level Translation................................................................49
Figure 25. Connector Sharing with a USB Transceiver................................................49
Figure 26. RS-232 Application...................................................................50
Figure 27. RS-485 Half-Duplex Application.........................................................50
MAX3107SPI/I2C UART with 128-Word FIFOs
LIST OF REGISTERS
RHR—Receiver Hold Register...................................................................23
THR—Transmit Hold Register ...................................................................24
IRQEn—IRQ Enable Register ...................................................................24
ISR—Interrupt Status Register ..................................................................25
LSRIntEn—Line Status Register Interrupt Enable....................................................26
LSR—Line Status Register .....................................................................27
SpclChrIntEn—Special Character Interrupt Enable Register ...........................................28
SpclCharInt—Special Character Interrupt Register...................................................29
STSIntEn—STS Interrupt Enable Register .........................................................30
STSInt—Status Interrupt Register................................................................30
MODE1 Register .............................................................................31
MODE2 Register .............................................................................32
LCR—Line Control Register.....................................................................33
RxTimeOut—Receiver Timeout Register...........................................................34
HDplxDelay Register ..........................................................................34
IrDA Register ................................................................................35
FlowLvl—Flow Level Register ...................................................................35
FIFOTrgLvl—FIFO Interrupt Trigger Level Register...................................................36
TxFIFOLvl—Transmit FIFO Level Register..........................................................36
RxFIFOLvl—Receive FIFO Level Register .........................................................36
FlowCtrl—Flow Control Register.................................................................37
XON1 Register...............................................................................38
XON2 Register...............................................................................39
XOFF1 Register ..............................................................................39
XOFF2 Register ..............................................................................40
GPIOConfg—GPIO Configuration Register.........................................................40
GPIOData—GPIO Data Register.................................................................40
PLLConfig—PLL Configuration Register............................................................41
BRGConfig—Baud-Rate Generator Configuration Register............................................42
DIVLSB—Baud-Rate Generator LSB Divisor Register................................................42
DIVMSB—Baud-Rate Generator MSB Divisor Register...............................................42
CLKSource—Clock Source Register..............................................................43
RevID—Revision Identification Register ...........................................................43
TQFNJunction-to-Ambient Thermal Resistance (θJA).......... 65°C/WJunction-to-Case Thermal Resistance (θJC) .............. 15°C/W
SSOPJunction-to-Ambient Thermal Resistance (θJA)...........81°C/WJunction-to-Case Thermal Resistance (θJC) .............. 32°C/W
(Voltages referenced to AGND.)
VL, VA, VEXT, XIN ............................................... -0.3V to +4.0V
V18, XOUT .................................................. -0.3V to (VA + 0.3V)
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, I2C/SPI ................ -0.3V to (VL + 0.3V)
TX, RX, RTS/CLKOUT, CTS, GPIO_ .... -0.3V to (VEXT + 0.3V)
DGND .................................................................. -0.3V to +0.3V
Continuous Power Dissipation (TA = +70°C)TQFN (derate 15.4mW/°C above +70°C)................. 1229mWSSOP (derate 12.3mW/°C above +70°C) .................. 988mW
Operating Temperature Range .......................... -40°C to +85°C
Junction Temperature ..................................................... +150°C
Storage Temperature Range ........................... -65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Note 2)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Digital Interface Supply VoltageVL1.713.6V
Analog Supply VoltageVA2.353.6V
UART Interface Logic Supply
VoltageVEXT1.713.6V
Logic Supply VoltageV181.651.801.95V
CURRENT CONSUMPTION
VA Supply CurrentIA
1.8MHz crystal oscillator active, PLL disabled,
VLDOEN = VL, SPI/I2C interface idle220500µA
Baud rate = 1Mbps, external clock, SPI
frequency is 8MHz, external loopback PLL
disabled, VLDOEN = VL (Note 3)
0.651.3mA
VA Shutdown Supply CurrentIA, SHDNShutdown mode, VLDOEN = 0V, VRST = 0V,
all inputs and outputs are idle2035µA
VA Sleep Supply CurrentIA, SLEEPSleep mode, VLDOEN = VL, VRST = VL, all
inputs and outputs are idle45100µA
VL Supply CurrentILAll logic inputs are at VL or VEXT or 0V 415µA
VEXT Supply CurrentIEXTAll logic inputs are at VL or VEXT or 0V 510µA
V18 Input Power-Supply Current I18SHDN
VLDOEN = 0V (V18 is powered by an
external 1.85V voltage source), static 50µA
MAX3107SPI/I2C UART with 128-Word FIFOs
DC Electrical Characteristics
Package Thermal Characteristics (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCLK/SCL, DOUT/SDA
DOUT/SDA Output Low Voltage
in I2C ModeVOL,I2CILOAD = -3mA, VL > 2V0.4V
ILOAD = -3mA, VL < 2V0.2 x VLV
DOUT/SDA Output Low Voltage
in SPI ModeVOL,SPIILOAD = -2mA0.4V
DOUT/SDA Output High Voltage
in SPI ModeVOH,SPIILOAD = 2mAVL - 0.4V
Input Low VoltageVILSPI and I2C mode0.3 x VLV
Input High VoltageVIHSPI and I2C mode0.7 x VLV
Input HysteresisVHYSTSPI and I2C mode0.05 x VLV
Input Leakage CurrentIILVIN = 0 to VL, SPI and I2C mode-1+1µA
Input CapacitanceCIN_I2C_SPISPI and I2C mode5pF
I2C/SPI, CS/A0, DIN/A1 INPUTS
Input Low VoltageVILSPI and I2C mode0.3 x VLV
Input High VoltageVIHSPI and I2C mode0.7 x VLV
Input HysteresisVHYSTSPI and I2C mode50mV
Input Leakage CurrentIILVIN = 0 to VL, SPI and I2C mode-1+1µA
Input CapacitanceCIN_I2C_SPISPI and I2C mode5pF
IRQ OUTPUT (OPEN DRAIN)
Output Low VoltageVOLILOAD = -2mA0.4V
Output LeakageILKVIRQ = 0 to VL, IRQ is not asserted-1+1µA
LDOEN AND RST INPUTS
Input Low VoltageVIL0.3 x VLV
Input High VoltageVIH0.7 x VLV
Input HysteresisVHYST50mV
Input Leakage CurrentIINVIN = 0 to VL-1+1µA
RTS/CLKOUT AND TX OUTPUTS
Output Low VoltageVOLILOAD = -2mA0.4V
Output High VoltageVOHILOAD = 2mAVEXT - 0.4V
Input Leakage CurrentIINOutput three-stated, VIN = 0 to VEXT-1+1µA
Input CapacitanceCIN_IRSTBHigh-Z mode5pF
RX, CTS INPUTS
Input Low VoltageVIL0.3 x VEXTV
Input High VoltageVIH0.7 x VEXTV
Input HysteresisVHYST50mV
CTS Input Leakage Current IIN_CTSVIN = 0 to VEXT-1+1µA
RX Pullup CurrentIIN_RXVIN = 0V0.31.53µA
MAX3107SPI/I2C UART with 128-Word FIFOs
DC Electrical Characteristics (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Note 2)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
UART CLOCKING
External Crystal FrequencyfXOSC14MHz
External Clock FrequencyfCLK0.535MHz
External Clock Duty Cycle(Note 3)4555%
Baud-Rate Generator Clock
InputfREF(Note 3)96MHz
I2C BUS: TIMING CHARACTERISTICS (see Figure 1)
SCL Clock FrequencyfSCLStandard mode100kHzFast mode400
Bus Free Time Between a STOP
(P) and START (S) ConditiontBUF
Standard mode4.7Fast mode1.3
Hold Time for START (S)
Condition and Repeated START
(Sr) Condition (Note 3)
tHD:STA
Standard mode4.0
Fast mode0.6
Low Period of the SCL ClocktLOW
Standard mode4.7Fast mode1.3
High Period of the SCL ClocktHIGHStandard mode4.0µs
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GPIO_ OUTPUTS AND INPUTS
Output Low VoltageVOLILOAD = -2mA, push-pull or open drain0.4V
Output High VoltageVOHILOAD = 2mA, push-pullVEXT - 0.4V
Input Low VoltageVILConigured as an input0.4V
Input High VoltageVIHConigured as an input2/3 x VEXTV
Pulldown CurrentIPDGPIO_ = VEXT0.2512.5µA
Input CapacitanceCIN_IUARTConigured as an input5pF
XIN
Input Low VoltageVIL0.3V
Input High VoltageVIH1.2VAV
Input CapacitanceCXI16pF
XOUT
Input CapacitanceCXO16pF
MAX3107SPI/I2C UART with 128-Word FIFOs
AC Electrical Characteristics
DC Electrical Characteristics (continued)
Note 2: All devices are production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 3: Not production tested. Guaranteed by design.
Note 4: When V18 is powered by an external voltage regulator, the external power supply must have current capability above or
equal to I18.
Note 5: CB is the total capacitance of either the clock or data line of the synchronous bus in pF.
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, VEXT = +1.71V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VA = +2.8V, VL = +1.8V, VEXT = +2.5V, TA = +25°C.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Hold TimetHD:DATStandard mode00.9µsFast mode00.9
Data Setup TimetSU:DATStandard mode250nsFast mode100
Setup Time for Repeated START
(Sr) ConditiontSU:STAStandard mode4.7µsFast mode0.6
Rise Time of SDA and SCL
Signals Receiving tR
Standard mode (0.3 x VL to 0.7 x VL)
(Note 5)
20 +
0.1CB1000
Fast mode (0.3 x VL to 0.7 x VL) (Note 5)20 +
0.1CB300
Fall Time of SDA and SCL
Signals tF
Standard mode (0.7 x VL to 0.3 x VL)
(Note 5)
20 +
0.1CB300
Fast mode (0.7 x VL to 0.3 x VL) (Note 5)20 +
0.1CB300
Setup Time for STOP (P)
ConditiontSU:STOStandard mode4.7µsFast mode0.6
Capacitive Load for SDA and
SCL (Note 3)CBStandard mode400pFFast mode400
I/O Capacitance (SCL, SDA)CI/O10pF
Pulse Width of Spike
SuppressedtSP50ns
SPI BUS: TIMING CHARACTERISTICS (see Figure 2)
SCLK Clock PeriodtCH+CL38.4ns
SCLK Pulse-Width HightCH16ns
SCLK Pulse-Width LowtCL16ns
CS Fall to SCLK Rise TimetCSS0ns
DIN Hold TimetDH3ns
DIN Setup TimetDS5ns
Output Data Propagation Delay tDO20ns
DOUT Rise and Fall TimestFT10ns
CS Hold TimetCSH32ns
MAX3107SPI/I2C UART with 128-Word FIFOs
AC Electrical Characteristics (continued
Figure 2. SPI Timing Diagram
Figure 1. I2C Timing Diagram
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tCH
tDO
tCSH
SDA
START CONDITION
(S)
START CONDITION
(S)
REPEATED START CONDITION
(Sr)
STOP CONDITION
(P)
SCL
tHD:STA
tSU:DATtSU:STA
tHD:DATtHD:STAtSU:STOtF
tBUF
tHIGHtLOWtRtF
MAX3107SPI/I2C UART with 128-Word FIFOs
Test Circuits/Timing Diagrams
(VA = 2.5V, VL = 2.5V, VEXT = 2.5V, LDOEN = VL, TA = +25°C, unless otherwise noted.)
GPIO_ OUTPUT LOW VOLTAGE
vs. SINK CURRENT (OPEN DRAIN)
MAX3107 toc07
ISINK
(mA)13
VEXT = 3.3V
VEXT = 2.5V
GPIO_ OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT (PUSH-PULL)
MAX3107 toc06
ISOURCE
(mA)
VEXT = 3.3V
VEXT = 2.5V
IA SUPPLY CURRENT
vs. PLL FREQUENCY
MAX3107 toc05
PLL FREQUENCY (MHz)
(mA)
PLL = x48
PLL = x96
PLL = x144
IA SUPPLY CURRENT
vs. TEMPERATURE
MAX3107 toc04
TEMPERATURE (°C)
(µA)3510-15
EXTERNAL 3.6MHz CLOCK
BAUD RATE = 115kbps
VA = 3.3V
VA = 2.5V
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CRYSTAL, PLL ENABLED)
MAX3107 toc03
VA (V)
(mA)
3.686MHz EXT. CRYSTAL
BAUD RATE = 115kbps
6x PLL MULT.FACTOR
LDOEN = VL
LDOEN = AGND
1.8V APPLIED TO V18
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CLOCK, PLL ENABLED)
MAX3107 toc02
VA (V)
(mA)
EXTERNAL 614kHz CLOCK
BAUD RATE = 115kbps
6x PLL MULT.FACTOR
LDOEN = VL
LDOEN = AGND
1.8V APPLIED TO V18
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CLOCK, PLL DISABLED)
MAX3107 toc01
VA (V)
(µA)
EXTERNAL 3.6MHz CLOCK
BAUD RATE = 115kbps
LDOEN = VL
LDOEN = AGND
1.8V APPLIED TO V18
MAX3107SPI/I2C UART with 128-Word FIFOs
Typical Operating Characteristics
PINNAMEFUNCTIONTQFN-EPSSOP4V18Internal 1.8V LDO Output and 1.8V Logic Supply Input. Bypass V18 with a 1µF
ceramic capacitor to DGND. Keep V18 powered in shutdown mode.5I2C/SPISPI or Active-Low I2C Selector Input. Drive I2C/SPI high to enable SPI. Drive I2C/SPI
low to enable I2C.6LDOEN
LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN
low to disable the internal LDO. Power V18 with an external 1.8V supply when
LDOEN is low.7DOUT/SDA
Serial-Data Output. When I2C/SPI is high, DOUT/SDA functions as the DOUT SPI
serial-data output. When I2C/SPI is low, DOUT/SDA functions as the SDA I2C serial-
data input/output.8SCLK/SCL
Serial-Clock Input. When I2C/SPI is high, SCLK/SCL functions as the SCLK SPI serial-
clock input (up to 26MHz). When I2C/SPI is low, SCLK/SCL functions as the SCL I2C
serial-clock input (up to 400kHz).9CS/A0
Active-Low Chip-Select and Address 0 Input. When I2C/SPI is high, CS/A0 functions
as the CS SPI active-low chip select. When I2C/SPI is low, CS/A0 functions as the A0
I2C device address programming input. Connect CS/A0 to DGND or VL.
TQFN
(3.5mm × 3.5mm)
MAX3107234561716151413
XOUT
VEXT
XIN+
I2C
/SPI
LDOEN
DOUT/SDA
SCLK/SCL
/A0
GPIO3
GPIO2GPIO1
AGND
*EP
*CONNECT EP TO AGND.
GPIO0
DGND
RST
DIN/A1
IRQ
CTS
TOP VIEW
XOUT
VEXTV18
AGND
XIN
MAX3107
CTS
GPIO2SCLK/SCL
LDOEN7GPIO3DOUT/SDA10GPIO0DIN/A19GPIO1CS/A012VLRST11DGNDIRQ
I2C/SPI
SSOP
RTS/CLKOUT
/CLKOUT
MAX3107SPI/I2C UART with 128-Word FIFOs
Pin Descriptions
Pin Conigurations
PINNAMEFUNCTIONTQFN-EPSSOP10DIN/A1
Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN
SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I2C device
address programming input and connects to DIN/A1 DGND or VL.11IRQActive-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending.12RST
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
In hardware reset mode, the oscillator and the internal PLL are shut down; there is no
clock activity.13VL
Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, and I2C/SPI. Bypass VL
with a 0.1µF ceramic capacitor to DGND. VL must be powered in all modes.14DGNDDigital Ground15GPIO0General-Purpose Input/Output 0. GPIO0 is user programmable as an input or output
(push-pull or open drain). GPIO0 has a weak pulldown resistor to ground.16GPIO1General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output
(push-pull or open drain). GPIO1 has a weak pulldown resistor to ground.17GPIO2General-Purpose Input/Output 2. GPIO2 is user programmable as an input or output
(push-pull or open drain). GPIO2 has a weak pulldown resistor to ground.18GPIO3General-Purpose Input/Output 3. GPIO3 is user programmable as an input or output
(push-pull or open drain). GPIO3 has a weak pulldown resistor to ground.19CTSActive-Low Clear-to-Send Input. CTS is a low-control input.20RTS/CLKOUTActive-Low Request-to-Send Output. RTS/CLKOUT can be set high or low by
programming bit 7 (RTS) of the LCR register.21RXReceive Input. Serial UART data input. RX has an internal weak pullup resistor to VEXT.22TXTransmit Output. Serial UART data output.23VEXT
Transceiver Interface Level Supply. VEXT powers the internal logic-level translators
for RX, TX, RTS, CTS, and GPIO_. Bypass VEXT with a 0.1µF ceramic capacitor to
DGND.24XOUT
Crystal Output. When using an external crystal, connect one end of the crystal to
XOUT and the other to XIN. When using an external clock source, leave XOUT
unconnected.1XIN
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to
XIN and the other one to XOUT. When using an external clock source, drive XIN with
the external clock.2AGNDAnalog Ground3VAAnalog Supply. VA powers the PLL and internal LDO. Bypass VA with a 0.1µF ceramic
capacitor to AGND.—EPExposed Paddle. Connect EP to AGND. EP is not intended as an electrical connection
point. Only for TQFN-EP package.
MAX3107SPI/I2C UART with 128-Word FIFOs
Pin Descriptions (continued)
*Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x08, RevID = 0xA1.
†Denotes nonread/write value: RHR = R, THR = W, ISR = COR, SpclCharInt = COR, STSInt = R/COR, LSR = R, TxFIFOLvl = R,
RxFIFOLvl = R, RevID = R.
REGISTERADDRBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
FIFO DATA
RHR†*0x00RData7RData6RData5RData4RData3RData2RData1RData0
THR†0x00TData7TData6TData5TData4TData3TData2TData1TData0
INTERRUPTS
IRQEn0x01CTSIEnRxEmtyIEnTxEmtyIEnTxTrgIEnRxTrgIEnSTSIEnSpclChrIEnLSRErrIEn
ISR*†0x02CTSIntRxEmptyIntTxEmptyIntTFifoTriglntRFifoTrigIntSTSIntSpCharIntLSRErrInt
LSRIntEn0x03——NoiseIntEnRBreakIEnFrameErrIEnParityIEnROverrIEnRTimoutIEn
LSR*†0x04CTSbit—RxNoiseRxBreakFrameErrRxParityErrRxOverrunRTimeout
SpclChrIntEn0x05——MltDrpIntEnBREAKIntEnXOFF2IntEnXOFF1IntEnXON2IntEnXON1IntEn
SpclCharInt †0x06——MultiDropIntBREAKIntXOFF2IntXOFF1IntXON2IntXON1Int
STSIntEn0x07—SleepIntEnClkRdyIntEn—GPI3IntEnGPI2IntEnGPI1IntEnGPI0IntEn
STSInt*†0x08—SleepIntClockReady—GPI3IntGPI2IntGPI1IntGPI0Int
UART MODES
MODE10x09IRQSelAutoSleepForcedSleepTrnscvCtrlRTSHiZTXHiZTxDisablRxDisabl
MODE20x0AEchoSuprsMultiDropLoopbackSpecialChrRxEmtyInvRxTrigInvFIFORstRST
LCR*0x0BRTSTxBreakForceParityEvenParityParityEnStopBitsLength1Length0
RxTimeOut0x0CTimOut7TimOut6TimOut5TimOut4TimOut3TimOut2TimOut1TimOut0
HDplxDelay0x0DSetup3Setup2Setup1Setup0Hold3Hold2Hold1Hold0
IrDA0x0E——TxInvRxInvMIR—SIRIrDAEn
FIFO CONTROL
FlowLvl0x0FResume3Resume2Resume1Resume0Halt3Halt2Halt1Halt0
FIFOTrgLvl*0x10RxTrig3RxTrig2RxTrig1RxTrig0TxTrig3TxTrig2TxTrig1TxTrig0
TxFIFOLvl†0x11TxFL7TxFL6TxFL5TxFL4TxFL3TxFL2TxFL1TxFL0
RxFIFOLvl†0x12RxFL7RxFL6RxFL5RxFL4RxFL3RxFL2RxFL1RxFL0
FLOW CONTROL
FlowCtrl0x13SwFlow3SwFlow2SwFlow1SwFlow0SwFlowEnGPIAddrAutoCTSAutoRTS
XON10x14Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
XON20x15Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
XOFF10x16Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
XOFF20x17Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
GPIOs
GPIOConfg0x18GP3ODGP2ODGP1ODGP0ODGP3OutGP2OutGP1OutGP0Out
GPIOData0x19GPI3DatGPI2DatGPI1DatGPI0DatGPO3DatGPO2DatGPO1DatGPO0Dat
CLOCK CONFIGURATION
PLLConig*0x1APLLFactor1PLLFactor0PreDiv5PreDiv4PreDiv3PreDiv2PreDiv1PreDiv0
BRGConig0x1B——4xMode2xModeFRACT3FRACT2FRACT1FRACT0
DIVLSB0x1CDiv7Div6Div5Div4Div3Div2Div1Div0
DIVMSB0x1DDiv15Div14Div13Div12Div11Div10Div9Div8
CLKSource*0x1ECLKtoRTS——-ClockEnPLLBypassPLLEnCrystalEn—
REVISION
RevID*†0x1F10100001
MAX3107SPI/I2C UART with 128-Word FIFOs
Register Map
(All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
MICROWIRE is a registered trademark of National
Detailed Description
The MAX3107 UART is a bridge between an SPI/
MICROWIRE® or I2C microprocessor bus and an
asynchronous serial-data communication link, such as
RS-485, RS-232, or IrDA. The MAX3107 contains an
advanced UART, a fractional baud-rate generator, and
four GPIOs. The MAX3107 is configured and monitored,
and data is written and read from 8-bit registers through
SPI or I2C. These registers are organized by related
function as shown in the Register Map.
The host controller loads data into the Transmit Holding
register (THR) through SPI or I2C. This data is automati-
cally pushed into the transmit FIFO and sent out at TX.
The MAX3107 adds START, STOP, and parity bits to the
data and sends the data out at the selected baud rate.
The clock configuration registers determine the baud rate,
clock source selection, and clock frequency prescaling.
The receiver in the MAX3107 detects a START bit as a
high-to-low RX transition. An internal clock samples this
data. The received data is automatically placed in the
receive FIFO and can then be read out of the RxFIFO
through the RHR.
Register Set
The MAX3107 has a flat register structure without shadow
registers. The registers are 8 bits wide. The MAX3107
registers have some similarities to the 16C550 registers.
Receive and Transmit FIFOs
The UART’s receiver and the transmitter each have a
128-word deep FIFO, reducing the intervals that the host
processor needs to dedicate for high-speed, high-volume
data transfer. As the data rates of the asynchronous RX,
TX interfaces increase and get closer to those of the host
controller’s SPI/I2C data rates, UART management and
flow control can make up a significant portion of the host’s
activity. By increasing FIFO size, the host is interrupted
less often and can utilize SPI/I2C burst data block
transfers to/from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trig-
ger levels are programmed through FIFOTrgLvl with a
resolution of eight FIFO locations. When a receive FIFO
trigger is generated, the host knows that the receive
FIFO has a defined number of words waiting to be read
out or that a known number of vacant FIFO locations are
available and ready to be filled. The transmit FIFO trigger
generates an interrupt when the transmit FIFO level is
above the programmed trigger level. The host then knows
to throttle data writing to the transmit FIFO.
The host can read out the number of words present in each
of the FIFOs through the TxFIFOLvl and RxFIFOLvl regis-
ters. Note: The TxFIFOLvl and RxFIFOLvl values can be
in error. See the TxFIFOLvl register description for details.
Transmitter Operation
Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words that
are written to it through THR.
The transmit FIFO can be programmed to generate
an interrupt when a programmed number of words are
present in the TxFIFO through the FIFOTrgLvl register.
The TxFIFO interrupt trigger level is selectable through
FIFOTrgLvl[3:0]. When the transmit FIFO fill level reaches
the programmed trigger level, the ISR[4] interrupt is set.
The transmit FIFO is empty when ISR[5]: TxEmtyInt is set.
ISR[5] turns high when the transmitter starts transmit-
ting the last word in the TxFIFO. Hence, the transmitter
is completely empty after ISR[5] is set with an additional
delay equal to the length of a complete character (includ-
ing START, parity, and STOP bits).
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst. To halt transmis-
sion, set MODE1[1]: TxDisabl to 1. After MODE1[1] is
set, the transmitter completes transmission of the current
CURRENT FILL LEVEL
TRANSMITTERTX
TRANSMIT FIFO
FIFOTrgLvl[3:0]TRIGGERISR[4]
THR
DATA FROM SPI/I2C INTERFACE
LEVELTxFIFOLvl
EMPTYISR[5]
MAX3107SPI/I2C UART with 128-Word FIFOs
character and then ceases transmission. The TX output
logic can be inverted through IrDA[5]: TxInv. If not stated
otherwise, all transmitter logic described in this data sheet
assumes IrDA[5] is 0. Note: Errors in transmitted data can
occur when the THR is being written to while the transmitter
is sending data. See the THR register description for details.
Receiver Operation
The receiver expects the format of the data at RX to be
as shown in Figure 4. The quiescent logic state is a high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are deposited
into the receive FIFO. Errors and status information are
stored for every received word (Figure 6). The host reads
data out of the receive FIFO through the Receive Holding
register (RHR), oldest data first. The status information
of the word previously read out of the RHR is located in
the Line Status register (LSR). After a word is read out of
the RHR, the LSR contains the status information for that
word. Note: If data is read out of RHR simultaneously
when the receiver is receiving data, errors can occur. See
the RHR register description for details.
The following three error conditions are determined for
each received word: parity error, framing error, and noise
on the line. Line noise is detected by checking the con-
sistency of the logic of the three samples (Figure 5). The
When this bit is set to 1, the MAX3107 turns the receiver
off immediately following the current word and does
not receive any further data. The RX input logic can be
inverted through IrDA[4]: RxInv.
Line Noise Indication
When operating in standard (i.e., not 2x or 4x rate) mode,
the MAX3107 checks that the binary logic level of the
three samples per received bit are identical. If any of the
three samples have differing logic levels, then noise on the
transmission line has affected the received data and is con-
sidered to be noisy. This noise indication is reflected in the
LSR[5]: RxNoise bit for each received byte. Parity errors
are another indication of noise, but are not as sensitive.
Clocking and Baud-Rate Generation
The MAX3107 can be clocked by an external crystal or an
external clock source. Figure 7 shows a simplified diagram
of the clocking circuitry. When the MAX3107 is clocked by
the crystal, the STSInt[5]: ClockReady indicates when the
clocks have settled and the baud-rate generator is ready
for stable operation.
The baud-rate clock can be routed to the RTS/CLKOUT
output. The clock rate is 16x the baud rate in standard
operating mode, and 8x the baud rate in 2x rate mode. In 4x
rate mode, the CLKOUT frequency is 4x the programmed
baud rate. If the fractional portion of the baud-rate genera-
Figure 5. Midbit Sampling
Figure 4. Receive Data Format
BAUD
BLOCK23456789
ONE BIT PERIOD11
MAJORITY
CENTER
SAMPLER13141516
RECEIVED DATA
LSB
STARTD0D1D2D3D4D5D6D7PARITYSTOPSTOP
MSB
MIDBIT
SAMPLING
MAX3107SPI/I2C UART with 128-Word FIFOs
Crystal Oscillator
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 1 to enable and select the crystal oscillator.
The on-chip crystal oscillator has load capacitances of
20pF integrated in both XIN and XOUT. Connect an exter-
nal crystal or ceramic oscillator between XIN and XOUT.
External Clock Source
When an external clock signal is used, this should
be connected to XIN. Leave XOUT unconnected.
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 0 to select external clocking.
PLL and Predivider
The internal predivider and PLL allow for a wide range
of external clock frequencies and baud rates. The PLL
can be configured to multiply the input clock rate by a
factor of 6, 48, 96, or 144 through PLLConfig[7:6]. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
Fractional Baud-Rate Generator
The internal fractional baud-rate generator provides a
high degree of flexibility and high resolution in baud-
rate programming. The baud-rate generator has a 16-bit
integer divisor and a 4-bit word for the fractional divisor.
The fractional baud-rate generator can be used with the
external crystal or clock source.
The integer and fractional divisors are calculated through
the divisor, D:
REFfD16BaudRate=×
where fREF is the reference frequency input to the baud-
rate generator and D is the ideal divisor. fREF must be
less than 96MHz. In 2x and 4x rate modes, replace the
divisor 16 by 8 or 4, respectively.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
Figure 6. Receive FIFO
CRYSTAL
OSCILLATOR
XOUT
CrystalEn
XIN
BAUD-RATE
GENERATOR
ClockEnPLLByps
PLLEn
PLLDIVIDER
RECEIVE FIFO
FIFOTrgLvl[7:4]TRIGGERISR[3]
WORDERROR128
RxFIFOLvl
TIMEOUT
EMPTY
ERRORS
OVERRUNLSR[1]
RECEIVED
DATA
RHR
RECEIVERRX
I2C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
MAX3107SPI/I2C UART with 128-Word FIFOs
DIV can be a maximum of 16 bits wide and is programmed
into the 2-byte-wide registers DIVMSB and DIVLSB. The
minimum allowed for DIVLSB is 1.
The fractional portion of the divisor, FRACT, is a 4-bit
nibble, which is programmed into BRGConfig[3:0]. The
maximum value is 15, allowing the divisor to be pro-
grammed with a resolution of 0.0625. FRACT is calcu-
lated as:
FRACT = ROUND(16 x (D-DIV))
The following is an example of calculating the divisor.
It is based on a required baud rate of 190kbaud and a
reference input frequency of 28.23MHz and 1x (default)
rate mode.
The ideal divisor is calculated as:
D = 28,230,000/(16 x 190,000)
= 9.2861842105263157894736842105263
hence DIV = 9.
FRACT =
ROUND(4.5789473684210526315789473684211) = 5
so that DIVMSB = 0x00, DIVLSB = 0x09, and
BRGConfig[3:0] = 0x05.
The resulting (actual) baud rate can be calculated as:
REFACTUAL
ACTUALBR16D=×
For this example: DACTUAL = 9 + 5/16 = 9.3125
where:
DACTUAL = DIV + FRACT/16
and:
BRACTUAL= 28,230,000/(16 x 9.3125)
= 189463.0872483221476510067114094 baud
Thus, the baud rate is within 0.28% of the ideal rate.
2x and 4x Rate Modes
To support higher baud rates than possible with standard
(16x sampling) operation, the MAX3107 offers 2x and 4x
rate modes. In this case, the reference clock rate only
needs to be either 8x or 4x of the baud rate, respec-
tively. The bits are only sampled once at the midbit instant
instead of the usual three samples to determine the logic
value of the bits. This reduces the tolerance to line noise
on the received data. The 2x and 4x modes are selectable
through BRGConfig[5:4]. Note that IrDA encoding and
decoding does not operate in 2x and 4x modes.
When 2x rate mode is selected, the actual baud rate
is twice the rate programmed into the baud-rate gen-
erator. If 4x rate mode is enabled, the actual baud rate
on the line is quadruple that of programmed baud rate
(Figure 8).
Figure 8. 2x and 4x Baud Rates
FRACTIONAL
RATE
GENERATOR
fREFBAUD RATE
BaudRateConfig[5:4]DIV[LSB]
DIV[MSB]
NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.
FRACT
1x, 2x, 4x RATE
MODES
MAX3107SPI/I2C UART with 128-Word FIFOs
Multidrop Mode
In multidrop mode, also known as 9-bit mode, the word
length is 8 bits and a 9th bit is used for distinguishing
between an address and a data word. Multidrop mode is
enabled through MODE2[6]: MultiDrop. Parity checking is
disabled and an SpclCharInt[5]: MultiDropInt interrupt is
generated when an address (9th bit set) is received.
It is up to the host processor to filter out the data intended
for its address. Alternatively, the auto data-filtering mode
can be used to automatically filter out the data intended
for the station’s specific 9-bit mode address.
Auto Data Filtering in Multidrop Mode
In multidrop mode, the MAX3107 can be configured
to automatically filter out data that is not meant for its
address. The address is user-definable either by pro-
gramming a register value or a combination of a register
values and GPIO hardware inputs. Use either XOFF2
or XOFF2[7:4] in combination with GPIO_ to define the
address.
Enable multidrop mode by setting MODE2[6]: MultiDrop
to 1 and enable auto data filtering by setting MODE2[4]:
SpecialChr to 1.
When using register bits in combination with GPIO_ to
define the address, the MSB of the address is written to
XOFF2[7:4] register bits, while the LSBs of the address
are defined through the GPIOs. To enable this mode,
set FlowCtrl[2]: GPIAddr, MODE2[4]: SpecialChr, and
MODE2[6]: MultiDrop to 1. GPIO_ is automatically read
when FlowCtrl[2]: GPIAddr is set to 1, and the address is
updated on logic changes at GPIO_.
In the auto data-filtering mode, the MAX3107 auto-
matically accepts data that is meant for its address and
places this into the receive FIFO, while it discards data
that is not meant for its address. The received address
word is not put into the FIFO.
Auto Transceiver Direction Control
In some half-duplex communication systems, the trans-
ceiver’s transmitter must be turned off when data is being
received so as not to load the bus. This is the case in half-
duplex RS-485 communication. Similarly in full-duplex
multidrop communication, like RS-485 or RS-422/V.11,
only one transmitter can be enabled at any one time and
the others must be disabled. The MAX3107 can auto-
matically enable/disable a transceiver’s transmitter and/
or receiver. This relieves the host processor of this time-
critical task.
The RTS/CLKOUT output is used to control the transceiv-
ers’ transmit enable input and is automatically set high
when the MAX3107’s transmitter starts transmission. This
occurs as soon as data is present in the transmit FIFO.
Auto transceiver direction control is enabled through
MODE1[4]: TrnscvCtrl. Figure 9 shows a typical MAX3107
connection in a RS-485 application.
The RTS/CLKOUT output can be set high in advance
of TX transmission by a programmable time period
called the setup time (Figure 10). The setup time is pro-
grammed through HDplxDelay[7:4]. Similarly, the RTS/
CLKOUT signal can be held high for a programmable
period after the transmitter has completed transmission.
The hold time is programmed through HDplxDelay[3:0].
MAX3107MAX13431
TRANSMITTERTX
RTS/CLKOUT
TxFIFO
RECEIVER
AUTO
TRANSCEIVER
CONTROL
RxFIFO
MAX3107SPI/I2C UART with 128-Word FIFOs
Echo Suppression
The MAX3107 can suppress echoed data, sometimes
found in half-duplex communication (e.g., RS-485 and
IrDA). If the transceiver’s receiver is not turned off
while the transceiver is transmitting, copies (echoes) are
received by the UART. The MAX3107’s receiver can block
the reception of this echoed data by enabling echo sup-
pression. Set MODE2[7]: EchoSuprs to 1 to enable echo
suppression.
The MAX3107 receiver can block echoes with a long
round trip delay. The transmitter can be configured
to remain enabled after the end of transmission for a
programmable period of time: the hold time delay. The
hold time delay is set by the HDplxDelay[3:0] register.
See the HDplxDelay description in the Detailed Register
Descriptions section for more information.
Auto transceiver direction control and echo suppression
can operate simultaneously.
Auto Hardware Flow Control
The MAX3107 is capable of auto hardware (RTS and
CTS) flow control without the need for host processor
intervention. When AutoRTS control is enabled, the
MAX3107 automatically controls the RTS handshake
without the need for host processor intervention. AutoCTS
flow control separately turns the MAX3107’s transmit-
ter on and off based on the CTS input. AutoRTS and
AutoCTS flow control are independently enabled through
FlowCtrl[1:0].
AutoRTS Control
AutoRTS flow control ensures that the receive FIFO does
not overflow by signaling to the far-end UART to stop
data transmission. The MAX3107 does this automati-
cally by controlling RTS/CLKOUT. AutoRTS flow control
is enabled through FlowCtrl[0]: AutoRTS. The HALT and
RESUME levels determine the threshold levels at which
RTS/CLKOUT is asserted and deasserted. HALT and
Figure 11. Half-Duplex with Echo Suppression
Figure 10. Setup and Hold Times in Auto Transceiver Direction Control
MAX3107MAX13431
TRANSMITTERTX
TxFIFO
RECEIVER
ECHO
SUPPRESSION
RxFIFO
RTS/CLKOUT
FIRST CHARACTERLAST CHARACTER
RTS/CLKOUT
SETUP
HOLD
MAX3107SPI/I2C UART with 128-Word FIFOs
RESUME are programmed in FlowLvl. With differing
HALT and RESUME levels, hysteresis can be defined for
the RTS/CLKOUT transitions.
When the RxFIFO fill level reaches the HALT level
(FlowLvl[3:0]), the MAX3107 deasserts RTS/CLKOUT.
RTS/CLKOUT remains deasserted until the RxFIFO is
emptied and the number of words falls to the RESUME
level.
Interrupts are not generated when the HALT and
RESUME levels are reached. This allows the host con-
troller to be completely disengaged from RTS flow control
management.
AutoCTS Control
When AutoCTS flow control is enabled, the UART auto-
matically starts transmitting data when the CTS input is
logic-level low and stops transmitting when CTS is logic-
high. This frees the host processor from managing this
timing-critical flow-control task. AutoCTS flow control is
enabled through FlowCtrl[1]: AutoCTS. During AutoCTS
flow control the CTS interrupt works normally. Set the
IRQEn[7]: CTSIntEn to 0 to disable CTS interrupts; then
ISR[7]: CTSInt is fixed to logic 0 and the host does not
receive interrupts from CTS. If CTS is set high during
transmission, the MAX3107 completes transmission of
the current word and halts transmission afterwards.
Turn the transmitter off by setting MODE1[1] to 1 before
enabling AutoCTS control.
Auto Software (XON/XOFF) Flow Control
When auto software flow control is enabled, the MAX3107
recognizes and/or sends predefined XON/XOFF charac-
ters to control the flow of data across the asynchronous
serial link. Auto flow works autonomously and does not
involve host intervention, similar to auto hardware flow
control. To reduce the chance of receiving corrupted
data that equals a single-byte XON or XOFF character,
the MAX3107 allows for double-wide (16-bit) XON/XOFF
characters. XON and XOFF are programmed into the
XON1, XON2 and XOFF1, XOFF2 registers.
FlowCtrl[7:3] are used for enabling and configuring
auto software flow control. An ISR[1] interrupt is gener-
ated when XON or XOFF are received and details are
found in SpclCharInt. The IRQ can be masked by setting
IRQEn[1]: SpclChrIEn to 0.
Software flow control consists of transmitter control and
receiver overflow control, which can operate indepen-
dently of each other.
Figure 12. Echo Suppression Timing
DI TO RO PROPAGATION DELAY
HOLD DELAYSTOP
BIT
RTS/CLKOUT
MAX3107SPI/I2C UART with 128-Word FIFOs
Transmitter Flow Control
If auto transmitter control (FlowCtrl[5:4]) is enabled, the
receiver compares all received words with the XOFF and
XON characters. If a XOFF is received, the MAX3107
halts its transmitter from sending further data. The
receiver is not affected and continues reception. Upon
receiving an XON, the transmitter restarts sending data.
The received XON and XOFF characters are filtered out
and are not put into the receive FIFO, as they do not have
significance to the higher layer protocol. An interrupt is not
generated.
Turn the transmitter off (MODE1[1]) before enabling trans-
mitter control.
Receiver Flow Control
If auto receiver overflow control (FlowCtrl[7:6]) is enabled,
the MAX3107 automatically sends XOFF and XON con-
trol characters to the far-end UART to avoid receiver
overflow. XOFF1/XOFF2 are sent when the receive FIFO
fill level reaches the HALT value set in the FlowLvl regis-
ter. When the host controller reads data from the Receive
FIFO to a level equal to the RESUME level programmed
into the FlowLvl register, XON1/XON2 are automati-
cally sent to the far-end station to signal it to resume data
transmission.
If dual-character (XON1 and XON2/XOFF1 and XOFF2)
flow control is selected, XON1/XOFF1 are transmitted
before XON2/XOFF2.
FIFO Interrupt Triggering
Receive and transmit FIFO fill-dependent interrupts are
generated if FIFO trigger levels are defined. When the
number of words in the FIFOs reach or exceed a trigger
level, as programmed in FIFOTrgLvl, an ISR[3] or ISR[4]
interrupt is generated. There is no relationship between
the trigger levels and the HALT or RESUME levels.
The FIFO trigger level can, for example, be used for a
block data transfer, since it gives the host an indication
when a given block size of data is available for readout in
the receive FIFO or available for transfer to the transmit
FIFO.
Low-Power Standby Modes
The sleep and shutdown modes reduce power con-
sumption during periods of inactivity. In both sleep and
shutdown modes, the UART disables specific functional
blocks to reduce power consumption.
Forced Sleep Mode
In forced sleep mode, all UART-related on-chip clocking is
stopped. The following are inactive: the crystal oscillator,
the PLL, the predivider, the receiver, and the transmitter.
Thus, the host controller can access the resisters. To
enter sleep mode, set MODE1[5] to 1. To wake up, set
MODE1[5] to 0.
Autosleep Mode
The MAX3107 can be configured to operate in autosleep
mode by setting MODE1[6] to 1. In autosleep mode, the
MAX3107 automatically enters sleep mode when all the
following conditions are met:●Both FIFOs are empty.●There are no pending IRQ interrupts.●There is no activity on any input pins for a period
equal to 65,536 UART characters lengths.
The MAX3107 exits autosleep mode as soon as activity is
detected on any of the GPIO_, RX, or CTS inputs.
To manually wake up the MAX3107, set MODE1[6] to
0. After wake-up is initiated, the internal clock starts up
and a period of time is needed for clock stabilization. The
STSInt[5]: ClockReady bit indicates when the clocks are
stable. If an external clock source is used, the STSInt[5]
bit does not indicate clock stability.
Shutdown Mode
Shutdown mode is the lowest power consumption mode.
In shutdown mode, all the MAX3107 circuitry is off. This
includes the I2C/SPI interface, the registers, the FIFOs,
and clocking circuitry. The LDO is kept on. To enter shut-
down mode, connect RST to DGND.
When the RST input is toggled high, the MAX3107 exits
shutdown mode. When the MAX3107 sets IRQ to logic-
high, the chip initialization is completed. The MAX3107
needs to be reprogrammed following a shutdown. Keep
V18 powered by the internal LDO or an external 1.8V
supply during shutdown.
Power-Up and IRQ
IRQ has two functions. During normal operation (MODE1[7]
is 1), IRQ operates as a hardware interrupt output, where-
by the IRQ is active when an interrupt is pending. An IRQ
interrupt is only produced during normal operation, if at
least one of the IRQEn interrupt enable bits are enabled.
During power-up or following a reset, IRQ has a differ-
ent function. It is held low until the MAX3107 is ready for
programming following an initialization delay. Once IRQ
goes high, the MAX3107 is ready to be programmed.
The MODE1[7]: IRQSel bit should then be set in order to
enable normal IRQ interrupt operation.
In polled mode, the RevID register can be polled to
check whether the MAX3107 is ready for operation. If
the controller gets a valid response from RevID, then the
MAX3107SPI/I2C UART with 128-Word FIFOs
Bits 7–0: RData[7:0]
The RHR is the bottom of the receive FIFO and is the register used for reading data out of the receive FIFO. It contains the oldest
(first received) character in the receive FIFO. RHR[0] is the first data bit of the serial-data word received by the receiver at the RX
pin. Note that the data read out of RHR can be in error. This occurs when the UART receiver is receiving a character at the same
time as a value is being read out of RHR and the FIFO level counter is being updated. In the event of this error condition, the
result is that a character is read out twice from the RHR. To avoid this, the receiver should not be receiving data while the RHR
is being read out. This can be achieved via flow control, or prior knowledge of the amount of data that is expected to be received.
Bits 7–0: TData[7:0]
Interrupt Structure
The structure of the interrupt is shown in Figure 13. There
are four interrupt source registers: ISR, LSR, STSInt,
and SpclCharInt. The interrupt sources are divided into
top-level and low-level interrupts. The top-level interrupts
typically occur more often and can be read out directly
through the ISR. The low-level interrupts typically occur
less often and their specific source can be read out
through the LSR, STSInt, or SpclChar registers. The three
LSBs of the ISR point to the low-level interrupt registers
that contain the source detail of the interrupt source.
Interrupt Enabling
Every interrupt bit of the four interrupt registers can
be enabled or masked through an associated interrupt
enable register bit. These are the IRQEn, LSRIntEn,
SpclChrIntEn and STSIntEn registers.
Interrupt Clearing
When an ISR interrupt is pending (i.e., any bit in ISR is
set) and the ISR is subsequently read, the ISR bits and
IRQ are cleared. Both the SpclCharInt and the STSInt
registers also are clear on read (COR). The LSR bits are
only cleared when the source of the interrupt is removed,
not when LSR is read.
Detailed Register Descriptions
The MAX3107 has a flat register structure, without shad-
ow registers, that makes programming and code simple
and efficient. All registers are 8 bits wide.
ADDRESS:0x00
MODE:R
BIT76543210
NAMERData7RData6RData5RData4RData3RData2RData1RData0
RESETXXXXXXXX6543210
ISR
[7]IRQ
POWER-UP DONE
MODE1[7]: IRQSel
[0]
LOW-LEVEL INTERRUPTS
TOP-LEVEL INTERRUPTS6543210
SpclChrInt6543210
STSInt6543210
LSR
MAX3107SPI/I2C UART with 128-Word FIFOs
RHR—Receiver Hold Register
The THR is the register that the host controller writes data to for subsequent UART transmission. This data is deposited
in the transmit FIFO. THR[0] is the LSB. It is the first data bit of the serial-data word that the transmitter sends out, right
after the START bit. Note that an error can occur in the TxFIFO when a character is written into THR at the same time
as the transmitter is transmitting out data via TX. In the event of this error condition, the result is that the character will
not be transmitted. To avoid this, stop the transmitter when writing data to the THR. This can be done via the TxDisable
bit in the MODE1 register.
The IRQEn is used to enable the IRQ physical interrupt. Any of the eight ISR interrupt sources can be enabled to gener-
ate an IRQ. The IRQEn bits only influence the IRQ output and do not have any effect on the ISR contents or behavior.
Every one of the IRQEn bits operates on an ISR bit.
Bit 7: CTSIEn
The CTSIEn bit enables IRQ interrupt generation when the CTSInt interrupt bit is set in the ISR. Set CTSIEn bit low to
disable IRQ generation from CTSInt.
Bit 6: RxEmtyIEn
The RxEmtyIEn bit enables IRQ interrupt generation when the RxEmtyInt interrupt bit is set in the ISR. Set RxEmtyIEn
bit low to disable IRQ generation from RxEmtyInt.
Bit 5: TxEmtyIEn
The TxEmtyIEn bit enables IRQ interrupt generation when the TxEmptyInt interrupt bit is set in the ISR. Set TxEmtyIEn
bit low to disable IRQ generation from TxEmptyInt.
Bit 4: TxTrgIEn
The TxTrgIEn bit enables IRQ interrupt generation when the TFifoTrigInt interrupt bit is set in the ISR. Set TxTrgIEn bit
low to disable IRQ generation from TFifoTrigInt.
Bit 3: RxTrgIEn
The RxTrgIEn bit enables IRQ interrupt generation when the RFifoTrigInt interrupt bit is set in the ISR. Set RxTrgIEn bit
low to disable IRQ generation from RFifoTrigInt.
Bit 2: STSIEn
The STSIEn bit enables IRQ interrupt generation when the STSInt interrupt bit is set in the ISR. Set STSIEn bit low to
disable IRQ generation from STSInt.
Bit 1: SpclChrlEn
The SpclChrIEn bit enables IRQ interrupt generation when the SpCharInt interrupt bit is set in the ISR. Set SpclChrIEn
bit low to disable IRQ generation from SpCharInt.
ADDRESS:0x01
MODE:R/W
BIT76543210
NAMECTSIEnRxEmtyIEnTxEmtyIEnTxTrgIEnRxTrgIEnSTSIEnSpclChrIEnLSRErrIEn
RESET00000000
ADDRESS:0x00
MODE:W
BIT76543210
NAMETData7TData6TData5TData4TData3TData2TData1TData0
MAX3107SPI/I2C UART with 128-Word FIFOs
IRQEn—IRQ Enable Register
THR—Transmit Hold Register
The LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set LSRErrIEn
low to disable IRQ generation from LSRErrInt.
The ISR provides an overview of all interrupts generated in the MAX3107. These interrupts are cleared on reading the
ISR. When the MAX3107 is operated in polled mode, the ISR can be polled to establish the UART’s status. In interrupt-
driven mode, IRQ interrupts are enabled through the appropriate IRQEn bits. The ISR contents give direct information
on the cause for the interrupt or point to other registers that contain more detailed information.
Bit 7: CTSInt
The CTSInt is set when a logic state transition occurs at the CTS input. This bit is cleared after ISR is read. The current
logic state of the CTS input can be read out through the LSR[7]: CTSbit.
Bit 6: RxEmptyInt
The RxEmptyInt is set when the receive FIFO is empty. This bit is cleared after ISR is read. Its meaning can be inverted
by setting the MODE2[3]: RxEmtyInv bit.
Bit 5: TxEmptyInt
The TxEmptyInt bit is set when the transmit FIFO is empty. This bit is cleared once ISR is read.
Bit 4: TFifoTriglnt
The TFifoTrigInt bit is set when the number of characters in the transmit FIFO is equal to or greater than the transmit
FIFO trigger level defined in FIFOTrgLvl[3:0]. TFifoTrigInt is cleared when the transmit FIFO level falls below the trigger
level or after the ISR is read. It can be used as a warning that the transmit FIFO is nearing overflow.
Bit 3: RFifoTriglnt
The RFifoTrigInt bit is set when the receive FIFO fill level reaches the receive FIFO trigger level, as defined in the
FIFOTrgLvl[7:4]. This can be used as an indication that the receive FIFO is nearing overrun. It can also be used to report
that a known number of words are available which can be read out in one block. The meaning of RFifoTrigInt can be
inverted through MODE2[2]. RFifoTrigInt is cleared when ISR is read.
Bit 2: STSInt
The STSInt bit is set high when any bit in the STSInt register that is enabled through a STSIntEn bit is high. The STSInt
bit is cleared on reading ISR.
Bit 1: SpCharlnt
The SpCharInt bit is set high when a special character is received, a line BREAK is detected, or an address character is
received in multidrop mode. The cause for the SpCharInt interrupt can be read from the SpclCharInt register, if enabled
through the SpclChrIntEn bits. The SpCharInt interrupt is cleared when the ISR is read.
Bit 0: LSRErrlnt
The LSRErrInt bit is set high when any LSR bits, which are enabled through the LSRIntEn, are set. This bit is cleared
after the ISR is read.
ADDRESS:0x02
MODE:COR
BIT76543210
NAMECTSIntRxEmptyIntTxEmptyIntTFifoTrigIntRFifoTrigIntSTSIntSpCharIntLSRErrInt
RESET01100000
MAX3107SPI/I2C UART with 128-Word FIFOs
ISR—Interrupt Status Register
The LSRIntEn allows routing of LSR interrupt bits to the ISR[0].
Bits 7 and 6: No Function
Bit 5: NoiseIntEn
Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0]. If NoiseIntEn is set low, RxNoise is not
routed to LSR[0].
Bit 4: RBreaklEn
Set the RBreakIEn bit high to enable routing the RxBreak interrupt to LSR[0]. If RBreakIEn is set low, RxBreak is not
routed to LSR[0].
Bit 3: FrameErrlEn
Set the FrameErrIEn bit high to enable routing the FrameErr interrupt to LSR[0]. If FrameErrIEn is set low, FrameErr is
not routed to LSR[0].
Bit 2: ParitylEn
Set the ParityIEn bit high to enable routing the RxParityErr interrupt to LSR[0]. If ParityIEn is set low, RxParityErr is not
routed to the LSR[0].
Bit 1: ROverrlEN
Set the ROverrIEn bit high to enable routing the RxOverrun interrupt to LSR[0]. If ROverrIEn is set low, RxOverrun is not
routed to LSR[0].
Bit 0: RTimoutlEn
Set the RTimoutIEn bit high to enabled routing the RTimeout interrupt to LSR[0]. If RTimoutIEn is set low, the RTimeout
is not routed to LSR[0].
ADDRESS:0x03
MODE:R/W
BIT76543210
NAME——NoiseIntEnRBreakIEnFrameErrIEnParityIEnROverrIEnRTimoutIEn
RESET00000000
MAX3107SPI/I2C UART with 128-Word FIFOs
LSRIntEn—Line Status Register Interrupt Enable

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