MAX3100CEE+T ,SPI/MICROWIRE-Compatible UARTMAX3100SPI/MICROWIRE-Compatible UART in QSOP-16
MAX3100CEE-T ,SPI/MICROWIRE-Compatible UARTELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, T = T to T , unless otherwise noted. Typical values ..
MAX3100CPD ,SPI/Microwire-Compatible UART in QSOP-16MAX310019-1259; Rev 0; 7/97SPI/Microwire-Compatible UART in QSOP-16_______________
MAX3100CPD+ ,SPI/MICROWIRE-Compatible UARTApplicationsMAX3100CEE+ 0°C to +70°C 16 QSOPHandheld Instruments MAX3100EPD+ -40°C to +85°C 14 Plas ..
MAX3100EEE ,SPI/Microwire-Compatible UART in QSOP-16MAX310019-1259; Rev 0; 7/97SPI/Microwire-Compatible UART in QSOP-16_______________
MAX3100EEE+ ,SPI/MICROWIRE-Compatible UARTMAX3100SPI/MICROWIRE-Compatible UART in QSOP-16
MAX635AESA ,Preset -5V output or adjuistable output with 2 resistors, CMOS switching regulator. Output accuracy 5%.19-0918; Re v tk 5/91
[VI llXI/VI
Preset/Adiustable Output CMOS
Inverting Switching Regulato ..
MAX635AESA+ ,Preset/Adjustable Output CMOS Inverting Switching Regulatorsfeatures such as MAX635XCSA 0 C to +70 C 8 Narrow SO
Itogic-level shutdown, adjustable oscillator ..
MAX635AESA-T ,Preset/Adjustable Output CMOS Inverting Switching RegulatorsFeatures
The MAX635/MAX636/MAX637 inverting switching regu- . Preset -5V, -12V, -15V Output Volt ..
MAX635BCPA ,Preset -5V output or adjuistable output with 2 resistors, CMOS switching regulator. Output accuracy 10%.features such as MAX635XCSA 0 C to +70 C 8 Narrow SO
Itogic-level shutdown, adjustable oscillator ..
MAX636 ,Preset/Adjustable Output CMOS Inverting Switching Regulatorsapplications require only a diode, output filter . Only 3 External Components
capacitor, and a Iow ..
MAX6360LSUT-T ,Dual/Triple-Voltage レP Supervisory CircuitsApplicationsOrdering InformationComputers Intelligent InstrumentsPART* TEMP. RANGE PIN-PACKAGEContr ..
MAX3100CEE+-MAX3100CEE+T-MAX3100CEE-T-MAX3100CPD+-MAX3100EEE+-MAX3100EEE+T-MAX3100EPD+
SPI/MICROWIRE-Compatible UART
AVAILABLE
General DescriptionThe MAX3100 universal asynchronous receiver transmit-
ter (UART) is the first UART specifically optimized for
small microcontroller-based systems. Using an
SPI™/MICROWIRE™ interface for communication with
the host microcontroller (µC), the MAX3100 comes in a
compact 16-pin QSOP. The asynchronous I/O is suitable
for use in RS-232, RS-485, IR, and opto-isolated data
links. IR-link communication is easy with the MAX3100’s
infrared data association (IrDA) timing mode.
The MAX3100 includes a crystal oscillator and a baud-
rate generator with software-programmable divider ratios
for all common baud rates from 300 baud to 230k baud.
A software- or hardware-invoked shutdown lowers quies-
cent current to 10µA, while allowing the MAX3100 to
detect receiver activity.
An 8-word-deep first-in/first-out (FIFO) buffer minimizes
processor overhead. This device also includes a flexible
interrupt with four maskable sources, including address
recognition on 9-bit networks. Two hardware-handshak-
ing control lines are included (one input and one output).
The MAX3100 is available in 14-pin plastic DIP and small,
16-pin QSOP packages in the commercial and extended
temperature ranges.
________________________ApplicationsHandheld Instruments
Intelligent Instrumentation
UART in SPI Systems
Small Networks in HVAC or Building Control
Isolated RS-232/RS-485: Directly Drives Opto-Couplers
Low-Cost IR Data Links for Computers/Peripherals
____________________________FeaturesSmall TQFN and QSOP Packages AvailableFull-Featured UART:
—IrDA SIR Timing Compatible
—8-Word FIFO Minimizes Processor
Overhead at High Data Rates
—Up to 230k Baud with a 3.6864MHz Crystal
—9-Bit Address-Recognition Interrupt
—Receive Activity Interrupt in ShutdownSPI/MICROWIRE-Compatible µC InterfaceLowest Power:
—150µA Operating Current at 3.3V
—10µA in Shutdown with Receive Interrupt+2.7V to +5.5V Supply Voltage in Operating ModeSchmitt-Trigger Inputs for Opto-Couplers TX and RTSOutputs Sink 25mA for Opto-Couplers
SPI/MICROWIRE-Compatible
UART in QSOP-16VCC
RTSCS
SCLK
DOUT
DIN
TOP VIEW
MAX3100
CTSGND
SHDN
IRQ
DIPVCC
RTS
N.C.
CTS
DIN
DOUT
SCLK
N.C.
IRQ
SHDN
GND
MAX3100
QSOPTQFN-EPMAX3100234561716151413
N.C.
N.C.
VCC
N.C.
N.C.
DOUTSCLK
IRQ
N.C.
N.C.RXCTSN.C.N.C.
DIN
N.C.
GND
N.C.
*EP = EXPOSED PAD, CONNECT EP TO GROUND
SHDN
RTS
*EP
+
Pin Configurations
Pin Configurations
PARTMAX3100CPD+
MAX3100CEE+0°C to +70°C
0°C to +70°C
TEMP RANGEPIN-PACKAGE14 Plastic DIP
16 QSOP
Ordering Information
Typical Operating Circuit appears at end of data sheet.MAX3100EPD+
MAX3100EEE+-40°C to +85°C
-40°C to +85°C14 Plastic DIP
16 QSOP
MAX3100ETG+-40°C to +85°C24 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
EP = Exposed pad.
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are measured at 9600 baud at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................................+6V
Input Voltage to GND
(CS, SHDN, X1, CTS, RX, DIN, SCLK)....-0.3V to (VCC+ 0.3V)
Output Voltage to GND
(DOUT, RTS, TX, X2) ..............................-0.3V to (VCC+ 0.3V)
IRQ...........................................................................-0.3V to 6V
TX, RTSOutput Current....................................................100mA
X2, DOUT, IRQShort-Circuit Duration
(to VCCor GND).........................................................Indefinite
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.00mW/°C above +70°C)..........800mW
QSOP (derate 8.30mW/°C above +70°C).....................667mW
TQFN (derate 33.3mW/°C above +70°C)................2666.7mW
Operating Temperature Ranges
MAX3100C_ _......................................................0°C to +70°C
MAX3100E_ _...................................................-40°C to +85°C
Storage Temperature Range............................-65°C to +160°C
Lead Temperature (soldering, 10s)................................+300°C
ISOURCE= 25µA, TX only
VIRQ= 5.5V
ISINK= 4mA
DOUT only, CS= VCC
Shutdown mode
Active mode
ISOURCE= 5mAV
VCC= 3.3V
VX1= 0V and 5.5V
CONDITIONSVCC- 0.5VOHOutput High Voltage5COUTOutput Capacitance±1ILKOutput Leakage0.4VOLOutput Low Voltage5COUTOutput Capacitance±1ILKOutput Leakage
DOUT, TX, RTS: ISINK= 4mA
TX, RTS: ISINK= 25mAV5CINInput Capacitance0.3 x VCCVILInput Low Voltage0.7 x VCCVIHInput High Voltage
0.4VOLOutput Low Voltage0.9
VX1= 0V and 5.5VVCC / 20.2 x VCCVILInput Low Voltage0.7 x VCCVCC / 2VIHInput High Voltage0.05 x VCCVHYSTInput Hysteresis±1IILInput Leakage5CINInput Capacitance
UNITSMINTYPMAXSYMBOLPARAMETERIINInput CurrentµA25
VCC- 0.5
ICCVCCSupply Current in
Normal Mode
SHDN bit = 1 or SHDN= 0,
logic inputs are at 0V or VCCµA10ICCVCCSupply Current in
Shutdown
With 1.8432MHz crystal;
all other logic inputs are at
0V or VCC
VCC= 5V
VCC= 3.3V0.150.4
LOGIC INPUTS (DIN, SCLK, CS, SHDN, CTS, RX)
OSCILLATOR INPUT (X1)
OUTPUTS (DOUT, TX, RTS)IRQ
OUTPUT (Open Drain)
POWER REQUIREMENTSMAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)(VCC= +2.7V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CLOAD= 100pF
CLOAD= 100pF, RCS= 10kΩ
CLOAD= 100pF
CONDITIONS100tCLSCLK Low Time100tCHSCLK High Time238tCPSCLK Period0tDHDIN to SCLK Hold Time100tDSDIN to SCLK Setup Time100tDOSCLK Fall to DOUT Valid0tCSHCSto SCLK Hold Time100tCSSCSto SCLK Setup Time100tTRCSHigh to DOUT Tri-State100tDVCSLow to DOUT Valid
UNITSMINTYPMAXSYMBOLPARAMETERTX, RTS, DOUT: CLOAD= 100pF
(Note 1)10trOutput Rise Time200tCSWCSHigh Pulse Width100tCS0SCLK Rising Edge
to CSFalling
(Note 1)ns200tCS1CSRising Edge
to SCLK Rising
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDOtTR
tCSH
Figure 1. Detailed Serial-Interface Timing
TX, RTS, DOUT, IRQ: CLOAD= 100pFns10tfOutput Fall Time
AC TIMING (Figure 1)
Note 1:tCS0and tCS1specify the minimum separation between SCLK rising edges used to write to other devices on the SPI bus
and the CSused to select the MAX3100. A separation greater than tCS0and tCS1ensures that the SCLK edge is ignored.
MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3100-01
TEMPERATURE (°C)
SUPPLY CURRENT (
VCC = 3.3V
VCC = 5V
1.8432MHz CRYSTAL
TRANSMITTING AT
115.2 kbps
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX3100-02
TEMPERATURE (°C)
SHUTDOWN CURRENT (
VCC = 5V
1.8432MHz CRYSTAL700
SUPPLY CURRENT vs.
EXTERNAL CLOCK FREQUENCY
EXTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT (
VCC = 5V
VCC = 3.3V0.20.10.60.70.81.0
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = 3.3V)MAX3100-04
VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
RTS
DOUT
10010k1000100k1M
SUPPLY CURRENT vs. BAUD RATEMAX3100-03a
BAUD RATE (bps)
SUPPLY CURRENT (
TRANSMITTING
1.8432 MHz
CRYSTAL
TRANSMITTING
STANDBY
STANDBY0.20.10.60.70.81.0
TX, RTS, DOUT OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE (VCC = 5V)MAX3100-05
VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
RTS
DOUT
MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
Detailed DescriptionThe MAX3100 universal asynchronous receiver trans-
mitter (UART) interfaces the SPI/MICROWIRE-compati-
ble, synchronous serial data from a microprocessor
(µP) to asynchronous, serial-data communication ports
(RS-232, RS-485, IrDA). Figure 2 shows the MAX3100
functional diagram.
The MAX3100 combines a simple UART and a baud-
rate generator with an SPI interface and an interrupt
generator. Configure the UART by writing a 16-bit word
to a write-configuration register, which contains the
baud rate, data-word length, parity enable, and enable
of the 8-word receive first-in/first-out (FIFO). The write
configuration selects between normal UART timing and
IrDA timing, controls shutdown, and contains 4 interrupt
mask bits.
Transmit data by writing a 16-bit word to a write-data
register, where the last 7 or 8 bits are actual data to be
transmitted. Also included is the state of the transmitted
parity bit (if enabled). This register controls the state of
the RTSoutput pin. Received words generate an inter-
rupt if the receive-bit interrupt is enabled.
Read data from a 16-bit register that holds the oldest
data from the receive FIFO, the received parity data,
and the logic level at the CTSinput pin. This register
also contains a bit that is the framing error in normal
operation and a receive-activity indicator in shutdown.
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B0 to B3 in
the write-configuration register determine the baud-rate
divisor (BRD), which divides down the X1 oscillator fre-
quency. The baud clock is 16 times the data rate (baud
rate).
Pin Description
PIN
QSOPDIPTQFN-EPNAMEFUNCTION123DINSPI/MICROWIRE Serial-Data Input. Schmitt-trigger input.22DOUTSPI/MICROWIRE Serial-Data Output. High impedance when CS is high.33SCLKSPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input.
444CSActive-Low Chip-Select Input. DOUT goes high impedance when CS is high,
IRQ, TX, and RTS are always active. Schmitt-trigger input.
655IRQActive-Low Interrupt Output. Open-drain interrupt output to microprocessor.
768SHDN
Hardware-Shutdown Input. When shut down (SHDN = 0), the oscillator turns
off immediately without waiting for the current transmission to end, reducing
supply current to just leakage currents.79GNDGround810X2Crystal Connection. Leave X2 unconnected for external clock. See Crystal-
Oscillator Operation—X1, X2 Connection section.911X1Crystal Connection. X1 also serves as an external clock input. See Crystal-
Oscillator Operation—X1, X2 Connection section.1015CTSGeneral-Purpose Active-Low Input. Read via the CTS register bit; often used
for RS-232 clear-to-send input (Table 1).1116RTSGeneral-Purpose Active-Low Output. Controlled by the CTS register bit. Often
used for RS-232 request-to-send output or RS-485 driver enable.1217RX
Asynchronous Serial-Data (receiver) Input. The serial information received
from the modem or RS-232/RS-485 receiver. A transition on RX while in
shutdown generates an interrupt (Table 5).1321TXAsynchronous Serial-Data (transmitter) Output1422VCCPositive Supply Pin (2.7V to 5.5V)
5, 12—
1, 6, 7, 12,
13, 14, 18,
19, 20, 24
N.C.No Connection. Not internally connected.——EPExposed Pad. Connect EP to ground or leave unconnected.
MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
DOUTBAUD-RATE
GENERATOR
SPI
INTERFACEBAUD-RATE
GENERATOR
DIN
SCLKB0TX-SHIFT REGISTER
START/STOP-
BIT DETECT
D0t–D7t
RX-SHIFT REGISTER
D0r–D7r
SHDNXTAL
TX-BUFFER REGISTER
RA/FE
(MASKS)RT
RX-BUFFER REGISTER
RX-BUFFER REGISTER
I / O
CTS
RTS
IRQINTERRUPT
LOGIC
TRANSMIT-DONE (TM)
DATA-RECEIVED (RM)
PARITY (PM)
FRAMING ERROR (RAM)/
RECEIVE ACTIVITY
(SOURCES)
ACTIVITY
DETECT
Figure 2. Functional Diagram
The transmitter section accepts SPI/MICROWIREdata,
formats it, and transmits it in asynchronous serial format
from the TX output. Data is loaded into the transmit-
buffer register from the SPI/MICROWIREinterface. The
MAX3100 adds start and stop bits to the data and
clocks the data out at the selected baud rate (Table 7).
MAX3100
MAX3100
The receiver section receives data in serial form. The
MAX3100 detects a start bit on a high-to-low RX transi-
tion (Figure 3). An internal clock samples data at 16
times the data rate. The start bit can occur as much as
one clock cycle before it is detected, as indicated by
the shaded portion. The state of the start bit is defined
as the majority of the 7th, 8th, and 9th sample of the
internal 16x baud clock. Subsequent bits are also
majority sampled. Receive data is stored in an 8-word
FIFO. The FIFO is cleared if it overflows.
The on-board oscillator can use a 1.8432MHz or
3.6864MHz crystal, or it can be driven at X1 with a 45%
to 55% duty-cycle square wave.
SPI InterfaceThe bit streams for DIN and DOUT consist of 16 bits,
with bits assigned as shown in the MAX3100
Operationssection. DOUT transitions on SCLK’s falling
edge, and DIN is latched on SCLK’s rising edge (Figure
4). Most operations, such as the clearing of internal
registers, are executed only on CS’s rising edge. The
DIN stream is monitored for its first two bits to tell the
UART the type of data transfer being executed (Write
Config, Read Config, Write Data, Read Data).
Only 16-bit words are expected. If CSgoes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Every time CSgoes low, a new
16-bit stream is expected. An example of a write con-
figuration is shown in Figure 4.
SPI/MICROWIRE-Compatible
UART in QSOP-16BAUD
BLOCK23456789
ONE BAUD PERIOD11
MAJORITY
CENTER
SAMPLER13141516
Figure 3. Start-Bit Timing
SCLK
DIN
DOUT345678910111213141516
DATA
UPDATED1FENSHDNTMRMPMRAMIRSTPELB3B2B1B000000000000000
Figure 4. SPI Interface (Write Configuration)
MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
MAX3100 Operations
Write OperationsTable 1 shows write-configuration data. A 16-bit
SPI/MICROWIREwrite configuration clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTSand CTSremain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed, the regis-
ters are updated when the transmission is over (T = 0).
The write-configuration bits (FEN, SHDNi, IR, ST, PE, L,
B3–B0) take effect after the current transmission is
over. The mask bits (TM, RM, PM, RAM) take effect
immediately after the 16th clock’s rising edge at SCLK.
Read OperationsTable 2 shows read-configuration data. This register
reads back the last configuration written to the
MAX3100. The device enters test mode if bit 0 = 1. In
this mode, if CS= 0, the RTSpin acts as the 16x clock
generator’s output. This may be useful for direct baud-
rate generation (in this mode, TX and RX are in digital
loopback).
Normally, the write-data register loads the TX-buffer
register. To change the RTSpin’s state without writing
data, set the TEbit. Setting the TEbit high inhibits the
write command (Table 3).
Reading data clears the R bit and interrupt IRQ(Table 4).
Register FunctionsTable 5 shows read/write operation and power-on reset
state (POR), and describes each bit used in program-
ming the MAX3100. Figure 5 shows parity and word-
length control.
D6t
D6r
D7t
D7r2
DIN1D2t
DOUTRD2r
BIT3
D3t
D3r
D0t
D0r
D1t
D1r
D4t
D4r
D5t
D5r
RA/FE
RTS
CTS
D6r
D7r2
DIN00
DOUTRD2r
BIT3
D3r
D0r
D1r
D4r
D5r
RA/FE
CTS
Table 3. Write Data (D15, D14 = 1, 0)
Table 4. Read Data (D15, D14 = 0, 0)2
DIN00
DOUTRB2
BIT3
TEST
RAM
SHDNo
FEN
Table 2. Read Configuration (D15, D14 = 0, 1) RAM
SHDNi
FEN14
DIN1
DOUTR
BIT
Table 1. Write Configuration (D15, D14 = 1, 1)MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16
POR
STATEDESCRIPTION0000Prr
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive
data (see the Nine-Bit Networkssection).rReads the value of the IR bit.
READ/
WRITEB0–B3wBaud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
B0–B3rBaud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
BIT
NAMEBit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1).rReads the value of the L bit.w
Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be
useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is
ignored in transmit mode (see the Nine-Bit Networkssection).
D0r–D7rrEight data bits read from the receive FIFO or the receive register. These will be all 0s when
the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0.
FENwFIFO Enable. Enables the receive FIFO when FEN= 0. When FEN= 1, FIFO is disabled.
FENrFIFO-Enable Readback. FEN’s state is read.wEnables the IrDA timing mode when IR = 1.
change
CTSrClear-to-Send-Input. Records the state of the CTSpin (CTS bit = 0 implies CTSpin = logic
high).
D0t–D7twTransmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.
Table 5. Bit DescriptionsPEw
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt
bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to
be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not
calculate parity.PErReads the value of the Parity-Enable bit.PMwMask for Pr bit. IRQis asserted if PM= 1 and Pr = 1 (Table 6).PMrReads the value of the PMbit (Table 6).RrReceive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the
receive register or FIFO.RMwMask for R bit. IRQis asserted if RM= 1 and R = 1 (Table 6).RMrReads the value of the RMbit (Table 6).RAMwMask for RA/FE bit. IRQis asserted if RAM= 1 and RA/FE = 1 (Table 6).RAMrReads the value of the RAMbit (Table 6).RTSwRequest-to-Send Bit. Controls the state of the RTSoutput. This bit is reset on power-up (RTS
bit = 0 sets the RTSpin = logic high).
MAX3100
MAX3100
Table 5. Bit Descriptions (continued)
SPI/MICROWIRE-Compatible
UART in QSOP-16
POR
STATEDESCRIPTIONREAD/
WRITE
BIT
NAMESHDNiw
Software-Shutdown Bit. Enter software shutdown with a write configuration where SHDNi = 1.
Software shutdown takes effect after CSgoes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a write configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CSgoing high. RTS and CTS are unaffected. Refer
to the Pin Description for hardware shutdown (SHDNinput).SHDNor
Shutdown Read-Back Bit. The read-configuration register outputs SHDNo = 1 when the UART
is in shutdown. Note that this bit is not sent until the current byte in the transmitter is sent (T =
1). This tells the processor when it may shut down the RS-232 driver. This bit is also set imme-
diately when the device is shut down through the SHDNpin.RA/FEr
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error can be cleared with a write configuration. The
FE bit is not cleared on a Read Data operation. When an FE is encountered, the UART resets
itself to the state where it is looking for a start bit. STwTransmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.STrReads the value of the ST bit.TMwMask for T bit. IRQis asserted if TM= 1 and T = 1 (Table 6).TMrReads the value of the TMbit (Table 6).TrTransmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.TEwTransmit-Enable Bit. If TE= 1, then only the RTSpin will be updated on CS’s rising edge. The
contents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE= 0.
IDLE
SECOND STOP BIT IS OMITTED IF ST = 0.
PE = 1, L = 1
TIMESTARTD1D2D3D4D5D6PtSTOPSTOPIDLE
IDLE
PE = 1, L = 0STARTD1D2D3D4D5D6D7PtSTOPSTOPIDLE
IDLE
PE = 0, L = 1STARTD1D2D3D4D5D6STOPSTOPIDLE
IDLE
PE = 0, L = 0STARTD1D2D3D4D5D6D7STOPSTOPIDLE
Figure 5. Parity and Word-Length Control
MAX3100
MAX3100
SPI/MICROWIRE-Compatible
UART in QSOP-16IRQ
RM MASK
TM MASK
PM MASK
TRANSITION ON RX
SHUTDOWN
RAM MASK
FRAMING ERROR
SHUTDOWN
RAM MASKQR
NEW DATA AVAILABLE
DATA READ
TRANSMIT BUFFER EMPTY
DATA READ
PE = 1 AND RECEIVED PARITY BIT = 1
PE = 0 OR RECEIVED PARITY BIT = 0QQ
Table 6. Interrupt Sources and Masks—Bit Descriptions
MEANING
WHEN SETDESCRIPTIONReceived parity bit = 1
Transition on RX when
in shutdown; framing
error when not in
shutdown
RA/FERAM
This is the RA (RX-transition) bit in shutdown, and the FE (framing-error) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3100 exits shutdown. IRQis asserted
when RA is set and RAM= 1.
FE is determined solely by the currently received data, and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character. IRQis asserted
when FE is set and RAM = 1.
MASK
BITPM
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0), or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value that will be read by a Read Data operation.
BIT
NAMEData availableRRM
The R bit is set when new data is available to be read from the receive register/
FIFO. FIFO is cleared when all data has been read. An interrupt is asserted as long
as R = 1 and RM= 1.
Transmit buffer is
emptyTTM
The T bit is set when the transmit buffer is ready to accept data. IRQis asserted
low if TM= 1 and the transmit buffer becomes empty. This source is cleared on
CS’s rising edge during a Read Data operation. Although the interrupt is cleared,
T may be polled to determine transmit-buffer status.
Interrupt Sources and MasksA Read Data operation clears the interrupt IRQ. Table
6 gives the details for each interrupt source. Figure 6
shows the functional diagram for the interrupt sources
and mask blocks.
MAX3100
MAX3100
Clock-Oscillator Baud RatesBits B0–B3 of the write-configuration register determine
the baud rate. Table 7 shows baud-rate divisors for given
input codes, as well as the given baud rate for
1.8432MHz and 3.6864MHz crystals. Note that the baud
rate = crystal frequency / 16x division ratio.
Shutdown ModeIn shutdown, the oscillator turns off to reduce power
dissipation (ICC< 10µA). The MAX3100 enters shut-
down in one of two ways: by a software command
(SHDNi bit = 1) or by a hardware command (SHDN=
logic low). The hardware shutdown is effective immedi-
ately and will immediately terminate any transmission in
progress. The software shutdown, requested by setting
SHDNi bit = 1, is entered upon completing the trans-
mission of the data in both the transmit register and the
transmit-buffer register. The SHDNo bit is set when the
MAX3100 enters shutdown (either hardware or soft-
ware). The microcontroller (µC) can monitor the SHDNo
bit to determine when all data has been transmitted,
and shut down any external circuitry (such as RS-232
transceivers) at that time.
Shutdown clears the receive FIFO, R, A, RA/FE,
D0r–D7r, Pr, and Pt registers and sets the T bit high.
Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L,
B0-3, and RTS) can be modified when SHDNo = 1 and
CTS can also be read. Even though RA is reset upon
entering shutdown, it will go high when any transitions
are detected on the RX pin. This allows the UART to
monitor activity on the receiver when in shutdown.
The command to power up (SHDNi = 0) turns on the
oscillator when CSgoes high if SHDNpin = logic high,
with a start-up time of about 25ms. This is done through
a write configuration, which clears all registers but RTS
and CTS. Since the crystal oscillator typically requires
25ms to start, the first received characters will be gar-
bled, and a framing error may occur.
__________Applications Information
Driving Opto-Couplers Figure 7 shows the MAX3100 in an isolated serial inter-
face. The MAX3100 Schmitt-trigger inputs are driven
directly by opto-coupler outputs. Isolated power is pro-
vided by the MAX253 transformer driver and linear reg-
ulator shown. A significant feature of this application is
that the opto-coupler’s skew does not affect the asyn-
chronous serial output’s timing. Only the set-up and
hold times of the SPI interface need to be met.
Figure 8 shows a bidirectional opto-isolated interface
using only two opto-isolators. Over 81% power savings
is realized using IrDA mode due to its 3/16-wide baud
periods.
Crystal-Oscillator Operation—
X1, X2 ConnectionThe MAX3100 includes a crystal oscillator for baud-rate
generation. For standard baud rates, use a 1.8432MHz
or 3.6864MHz crystal. The 1.8432MHz crystal results in
lower operating current; however, the 3.6864MHz crys-
tal may be more readily available in surface mount.
Ceramic resonators are low-cost alternatives to crystals
and operate similarly, though the “Q” and accuracy are
lower. Some ceramic resonators are available with inte-
gral load capacitors, which can further reduce cost.
The tradeoff between crystals and ceramic resonators
is in initial frequency accuracy and temperature drift.
The total error in the baud-rate generator should be
kept below 1% for reliable operation with other systems.
This is accomplished easily with a crystal, and in most
cases can be achieved with ceramic resonators. Table
8 lists the different types of crystals and resonators and
their suppliers.
Table 7. Baud-Rate Selection Table**Standard baud rates shown in bold
**Default baud rate
SPI/MICROWIRE-Compatible
UART in QSOP-16
115.2k
230.4k**
BAUD
RATE
(fOSC=
3.6864MHz)
BAUDB2B1B000010000**
DIVISION
RATIO
57.6k
115.2k**
BAUD
RATE
(fOSC=
1.8432MHz)28.8k
57.6k00110010
14.4k
28.8k
14.4k
38.4k
76.8k
19.2k10111010
120060011011100
240010011000
19.2k
38.4kMAX3100
MAX3100
