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MAX2395ETI+
WCDMA Quasi-Direct Modulator with VGA and PA Driver
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
General DescriptionThe MAX2395 fully monolithic quasi-direct modulator IC
is designed for use in WCDMA/UMTS transmitters. The
quasi-direct modulation architecture reduces system
cost, component count, and board space compared to
transmitters using an IF SAW filter with IF VCO and IF
synthesizer blocks.
The MAX2395 includes I/Q baseband filters, an IF I/Q
modulator with VGA, a fully monolithic VCO with PLL,
an upconverter mixer, an RF VGA, and a power amplifi-
er (PA) driver. The use of the quasi-direct modulator
scheme ensures 5% (typ) EVM and a 30dB (min) carri-
er suppression. The RF VGA and IF VGA provide a
nominal 90dB of output power control. No external local
oscillators are required, enabling efficient implementa-
tion of variable duplex offset systems.
The PLL is programmed by loading data on the SPI™/
MICROWIRE™-compatible 3-wire serial bus. The IC
operates from a single +2.7V to +3.3V supply. The
devices are available in space-saving 28-pin QFN and
thin QFN exposed-pad packages (5mm x 5mm).
Applications
Features5% EVM for POUT= +6dBm1920MHz to 1980MHz Operation +2.7V to +3.3V Single-Supply Operation+6dBm Output Power at 72mA 81dB Minimum Automatic Gain-Control (AGC)
RangeAutomatic ICCThrottle Back for Optimal Power
ConsumptionNo IF SAW Filter NecessaryOn-Chip RF PLL, with Fully Monolithic VCO Ultra-Low External Component CountSERIAL
BUS
GEN
INTEGER-N
PLL
+27262524232291011121314
POUT
VCC_PA
N.C.
BIAS_SET
VGC
VCC_IF
VCC_BB
SCLK
ATAN.C.N.C.BVPVTUNE
GND_VCO
VCC_VCO
RFCP
VCC_CP
VCC_PLL
REF
N.C.
SHDN
IDLE
90°0°MAX2395
Pin Configuration/
Functional Diagram
Ordering Information19-2970; Rev 3; 1/09
PARTTEMP RANGEPIN-PACKAGE MAX2395EGI -40°C to +85°C 28 QFN-EP*
MAX2395ETI -40°C to +85°C 28 TQFN-EP*
MAX2395ETI+ -40°C to +85°C 28 TQFN-EP*
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
EVALUATION KIT
AVAILABLE*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
WCDMA Phones
UMTS/EDGE Phones
W-TDD Phones
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +3.6V
All Other Pins to GND..................................-0.3V to VCC_+ 0.3V
I_, Q_, REF to GND..............................................................1VP-P
Digital Input Current.........................................................±10mA
Continuous Power Dissipation (TA= +70°C)
28-Pin QFN (derate 20.8mW/°C above +70°C).........1667mW
28-Pin TQFN (derate 21.3mW/°C above +70°C).......1702mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +3.3V, RBIAS= 12kΩ, TA= -40°C to +85°C. Typical values are at VCC= +2.85V and TA= +25°C, unless otherwise
noted.) (Notes 1, 2)
PARAMETERCONDITIONSMINTYPMAXUNITSSupply Voltage Range 2.7 2.85 3.3 V
VVGC = 0.35V 46 60
POUT = 0dBm 67 82 Operating Supply Current
POUT = +6dBm 72 90
IDLE_PRG = 0 16 21 Idle Current IDLE = VILIDLE_PRG = 1 19 27
mA
Shutdown Current SHDN = 0 0.5 10 µA
VGC Input Current -10 +10 µA
VGC Input Current During Shutdown SHDN = VIL 1 µA
Gain-Control Voltage Range 0.35 2.20 V
Lock Indicator High—Leakage Current PLL locked, VLD = VCC 4 µA
Lock Indicator Low—Sink Voltage PLL unlocked, sinking 100µA 0.4 V
SHDN Input Logic-High, VDH 1.5 VCC V
SHDN Input Logic-Low 0 0.5 V
SHDN Input Resistance Resistance to ground 50 k
Digital Input Logic-High, VIHAll digital input pins including IDLE, SDATA,
SCLK, and CS (Note 3)
0.7 x
VDH VCCV
Digital Input Logic-Low, VILAll digital input pins including IDLE, SDATA,
SCLK, and CS (Note 3) 00.3 x
VDHV
Digital Control Pin Input Current IDLE, SDATA, SCLK, and CS -10 +10 µA
I/Q Input Leakage Current -10 +10 µA
I/Q DC Common-Mode Voltage 1.35 1.45 1.65 V
CAUTION! ESD SENSITIVE DEVICE
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
AC ELECTRICAL CHARACTERISTICSMAX2395 EV kit, VCC= +2.7V to +3.3V, RBIAS= 12kΩ,VVGCadjusted to obtain maximum rated output power, and TA= -40°C to
+85°C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel
(12.2kbps), envelope level 1VP-P. Typical values are at VCC= +2.85V and TA= +25°C, unless otherwise noted. See Tables 1 and 3 for
register settings.) (Note 2)
PARAMETERCONDITIONSMINTYPMAXUNITS
CASCADED RF SPECIFICATIONSRF Frequency Range
(Notes 4, 6)192019501980MHz
Maximum Output Power
(Note 6)
VGC set for maximum output power while meeting
ACPR1, ACPR2, out-of-band emissions, and output
noise density specificationsdBm
At f = 1575MHz-31-24Out-of-Band Emissions
(Note 6)At RF + 2 x IF (image)-13-8.5dBc
POUT > 0dBm and TA > 0°C-48-45Adjacent Channel Power Ratio,
ACPR1 (Notes 5, 6)
∆Δf = ±5MHz/3.84MHzPOUT ≤ 0dBm and TA ≤ 0°C-45-43dBc
Alternate Channel Power Ratio,
ACPR2 (Notes 5, 6)∆Δf = ±10MHz/3.84MHz BW-60-57dBcOU T = + 6d Bm at 1920M H z, noi se m easur ed at 1880M H z-140-137Output Noise Power Density
(Note 6)P OU T = + 6d Bm at 1980M H z, noi se m easur ed at 2110M H z-146-143
dBc/Hz
Minimum Output PowerVVGC = 0.35V-85-78dBm
Carrier Suppression30dB
Sideband Suppression32dB
Including BB filter, POUT = +6dBm57.5EVM (Note 6)
Including BB filter, POUT = -44dBm8.614.6
%RMS
I/Q MODULATION BASEBAND INPUTSPassband Amplitude RippleDC to 2MHz (Notes 6, 7)-0.3+0.4dB
At 8.08MHz835Baseband SelectivityRelative to passbandAt 13.44MHz2550dB
INTEGER-N RF PLLMain PLL Integer Division Ratios16-bit register (64/65 dual-modulus prescaler)4032975065,535
Reference Frequency Range819.240MHz
Input Frequency for Reference
Frequency DoublerOPCTRL register bit 7 = 11316MHz
Reference-Divider Ratio9-bit register80511
Locked, RCP1/RCP0 = 0 1, VCC/2120015001800Charge-Pump Nominal Currents
(Sink or Source)Locked, RCP1/RCP0 = 1 1, VCC/2200025003000µA
Charge-Pump Leakage Current20nA
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
PARAMETERCONDITIONSMINTYPMAXUNITS
ON-CHIP VCOPhase NoiseAt 3MHz offset, measured at the center of the RF band
(Note 6)-130-128dBc/Hz
Supply PushingSupply stepped from +2.7V to +3.3V, with on-chip
voltage regulator±0.15MHz/V
RF VCO PullingWhen switching from IDLE mode to active Tx mode±0.1MHzP-P
3-WIRE SERIAL BUS INTERFACEData to Clock Setup, tCSFigure 1 (Note 6)20ns
Data to Clock Hold Time, tCHFigure 1 (Note 6)10ns
Clock Pulse-Width High, tCWHFigure 1 (Note 6)20ns
Clock Pulse-Width Low, tCWLFigure 1 (Note 6)20ns
Clock to Load Enable/Setup
Time, tESFigure 1 (Note 6)20ns
Clock Frequency(Note 6)20MHz
Note 1:The following parameters are characterized using the register settings below.
Note 2:Guaranteed at TA= +25°C and TA= +85°C by production test, and guaranteed by design and characterization at TA= -40°C.
Note 3:VDHis the high voltage applied to the shutdown pin.
Note 4:Output power, linearity, noise power, and LO leakage specifications are met over this frequency range.
Note 5:Specifications valid for all output power levels, unless limited by thermal noise at lower output power levels.
Note 6:Guaranteed by design and characterization.
Note 7:Tested at 1MHz and 2MHz in the passband.
Table 1. Characterization Register Settings
AC ELECTRICAL CHARACTERISTICS (continued)MAX2395 EV kit, VCC= +2.7V to +3.3V, RBIAS= 12kΩ,VVGCadjusted to obtain maximum rated output power, and TA= -40°C to
+85°C. I/Q inputs driven differentially with low- impedance source based on 3GPP UpLink reference measurement channel
(12.2kbps), envelope level 1VP-P. Typical values are at VCC= +2.85V and TA= +25°C, unless otherwise noted. See Tables 1 and 3 for
register settings.) (Note 2)
REGISTERSETTINGSADDRESSFUNCTIONRFR 4050 hex
(80 dec for ÷R) 0000b Reference-divider register
OPCTRL 3B7D hex 0100b Operational control settings
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Typical Operating Characteristics(VCC= +2.85V, fRF= 1950MHz, MPL = 1, and TA= +25°C, unless otherwise noted.)
EVM vs. POUTMAX2395 toc01
POUT (dBm)
EVM (%
RMS-2-6-10-14-18-22-26
TA = +25°C
TA = +85°C
TA = -40°C
POUT
ACPR1 vs. VVGC MAX2395 toc02
VVGC (V)
OUT
(dBm), ACPR (dBc)
TA = +85°C
TA = +25°C
TA = -40°C
OUTPUT SPECTRUM vs. FREQUENCYMAX2395 toc03
FREQUENCY (GHz)
OUTPUT SPECTRUM (dBm)
WANTED SIGNAL, 0dB
RF LO-2IF,
-32dBRF LO-3IF,
-35dB
RF LO, -42dB
RF IMAGE, 15dB
OUTPUT NOISE DENSITY vs. VVGCMAX2395 toc04
VVGC (V)
OUTPUT POWER NOISE DENSITY (dBm/Hz)
fRF = 1922.4MHz
f = 1880MHz
TA = +25°C
TA = +85°C
f = 2112.4MHz
TA = -40°C
ICC vs. VVGCMAX2395 toc05
VVGC (V)
ICC
(mA)
VCC = 2.7V TO 3.3V,
INPUT APPLIED
TA = +85°C
TA = -40°C
TA = +25°C
BASEBAND FILTER REPSONSEMAX2395 toc06
FREQUENCY (MHz)
FILTER RESPONSE (dB)161412108642
CARRIER AND SIDEBAND SUPPRESSION
vs. POUT
MAX2395 toc07
POUT (dBm)
CARRIER AND SIDEBAND SUPPRESSION (dBc)-14-24-34-44-54-64
SIDEBAND
CARRIER
VGC SLOPE LINEARITY vs. POUT MAX2395 toc08
POUT (dBm)
SLOPE (dB/V)-14-34-24-54-44-64-746
TA = -40°C
TA = +25°C
TA = +85°C
FREQUENCY SETTLING TIMEMAX2395 toc09
TIME (μs)
FREQUENCY (kHz)
FROM IDLE
FROM 1920MHz
TO 1980MHz
FROM SHDN
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Pin Description
PINNAMEFUNCTIONN.C.Connect to RF GND on PCBPOUT
Transmitter Output. This is an open-collector output and requires a pullup inductor to the supply
voltage. This pullup inductor can be part of the output matching network and can be connected
directly to the battery.
3VCC_PA
Supply for the PA Driver. This pin must be bypassed with a capacitor to system ground as close to
the pin as possible. Do not share the ground vias for the bypass capacitor with any other branch (see
the Typical Operating Circuit).BIAS_SET
Bias-Setting Pin. The DC voltage at this pin is a bandgap voltage. For nominal bias, connect a 12kΩ
resistor to ground. The value of this resistor can be adjusted to alter current consumption, linearity,
and noise performance of the RF output.VGC
Gain-Control Pin. Analog input pin controls both the IF VGA and RF VGA gain. When not driven, the
voltage on this pin is typically +1.5V. An RC filter on this pin must be used to filter out DAC noise or
the PDM clock.
6VCC_IF
Supply for IF Section. Bypass to system ground with a capacitor as close to the pin as possible. Do
not share the ground vias for the bypass capacitor with any other branch (see the Typical Operating
Circuit).
7VCC_BB
Supply for Baseband Section. Bypass to system ground with a capacitor as close to the pin as
possible. Do not share the ground vias for the bypass capacitor with any other branch (see the
Typical Operating Circuit).IDLE
Idle CMOS Digital Input. Drive LOW to place the device in WCDMA compressed mode (VCO and PLL
are ON; all others are OFF). A small RC lowpass filter can be used to minimize the effect of external
digital noise.SHDN
Shutdown CMOS Digital Input. Drive LOW to place the device in shutdown (everything OFF except
serial interface and registers, which retain their values). A small RC lowpass filter can be used to
minimize the effect of external digital noise. A logic-low on the SHDN pin overrides the serial bus
SHDN bit status.
10, 11I+, I-Differential I-Channel Baseband Inputs to the Baseband Filter
12, 13Q+, Q-Differential Q-Channel Baseband Inputs to the Baseband Filter
14, 24, 25N.C.Leave OpenLDLock CMOS Output. This pin is an open-drain output. Output HIGH indicates the RF PLL is locked.REF
Reference Frequency Input. This pin is internally biased to approximately +1.0V and must be AC-
coupled to the reference source. This is a high-impedance port and can be externally terminated to
the desired impedance.VCC_PLLSupply for PLL. Bypass with a capacitor to GND (see the Typical Operating Circuit).VCC_CPSupply for Synthesizer Charge Pump. Bypass with a capacitor to GND (see the Typical Operating
Circuit).RFCP
RF Charge-Pump Output. Connect the RF PLL’s loop filter between RFCP and system ground. Keep
the line from this pin to the tank tune input as short as possible to prevent spurious pickup. Connect
the loop filter as close to the tune input as possible.
MAX2395
WCDMA Quasi-Direct Modulator
with VGA and PA Driver
Detailed DescriptionThe MAX2395quasi-direct modulator accepts differen-
tial I/Q baseband inputs with external common-mode
bias. A gain-control voltage pin (VGC) controls the gain
of the IF and RF VGAs simultaneously to achieve the
best current consumption and linearity performance.
GmC FiltersThe internal GmC filters are used to eliminate noise and
baseband DAC aliasing signals above 8MHz. The GmC
filter can be bypassed (GMC_EN bit, OPCTRL register bit
3), lowering the total current at the expense of no filtering.
To speed up the settling time when transitioning from
IDLE to transmit mode, the filter can be forced to stay
active in IDLE mode using the IDLE_PRG bit (OPCTRL
register bit 1). Contact factory if bypass mode is used.
I/Q ModulatorDifferential in-phase (I) and quadrature-phase (Q) input
pins are designed to be DC-coupled and biased with
the baseband output from a digital-to-analog converter
(DAC). The I_ and Q_ inputs need a DC bias, which
can range from 1.35V to 1.65V. The current draw is
negligible and the differential input capacitance is 4pF.
The VCO frequency is divided by 6 to produce the RF
I/Q LO signals.
IF/RF VGAThe part offers approximately 90dB of gain-control
range. An external voltage must be applied using a
DAC allowing for dynamic gain control. To minimize the
noise contribution from the DAC to the RF signal, place
an RC filter at this pin (refer to the MAX2395 Evaluation
Kitdatasheet). The PA driver is included in the RF
VGA.
Internal VCO and TankThe integrated monolithic VCO and tank is tuned
through the VTUNE pin. The RF/IF LO signals are gen-
erated from this oscillator.
PLLThe internal PLL uses a charge-pump output to drive a
loop filter. The loop filter is typically a passive 2nd-
order lead lag filter with a bandwidth of 10kHz. The
loop filter must be optimized for a selected charge-
pump current, where KVCO= 90MHz/V. The internal
architecture requires the RF VCO to run at 1.2x the
desired frequency, mandating a 240kHz comparison
frequency for an output step size of 200kHz. The LD
output indicates whether the PLL is locked. An output
high indicates a lock condition.
There is an optional frequency doubler at the input of
the PLL reference divider. When using a 13MHz refer-
ence frequency, either a 40kHz comparison can be
used or the internal frequency doubler is enabled to
allow a comparison frequency of 80kHz. The optional
frequency double can be activated by setting OPCTRL
register bit 7 = 1.
PA Driver/RF UpconverterThe IF signal is upconverted with an image reject RF
mixer, and differentially fed into the PA driver. The PA
driver converts differential input signals to a single-
ended output. The driver requires a pullup inductor,
which is part of the output matching network.
Pin Description (continued)
PINNAMEFUNCTIONVCC_VCOSupply for VCO. Bypass to system ground with a capacitor as close to the pin as possible. Do not
share ground vias for the bypass capacitor with any other branch (see the Typical Operating Circuit).GND_VCORF VCO Varactor Ground. Connect to the ground at the PLL loop-filter capacitors. Do not connect to
the exposed pad.VTUNEOscillator-Frequency Tuning Voltage InputBYPBypass with a Capacitor to GND. The capacitor is used by the on-chip VCO voltage regulator (see
the Typical Operating Circuit).CS3-Wire Serial Bus Enable Input (Figure 1)SDATA3-Wire Serial Bus Data Input (Figure 1)SCLK3-Wire Serial Bus Clock Input (Figure 1)EPExposed Pad. Connect to the ground plane for proper heat dissipation.
