MAX2370ETM+T ,Complete 450MHz Quadrature TransmitterApplications Ordering Information450MHz CDMA/WCDMA PhonesPKGPART TEMP RANGE PIN-PACKAGE®CODEOFDM, c ..
MAX2371EGC+ ,LNAs with Step Attenuator and VGAFeaturesThe MAX2371/MAX2373 wideband low-noise amplifier♦ Low Noise Figure (1.8dB typical)(LNA) ICs ..
MAX2371ETC+ ,LNAs with Step Attenuator and VGAapplications. They contain single-channel, single-ended♦ Wide Frequency Range of Operation LNAs wit ..
MAX2373EGC ,LNAs with Step Attenuator and VGAMAX2371/MAX237319-2301; Rev 1; 10/06LNAs with Step Attenuator and VGA
MAX2373EGC+ ,LNAs with Step Attenuator and VGAELECTRICAL CHARACTERISTICS(MAX2371/MAX2373 EV Kits, V = 2.65V to 3.3V, RX_EN = high, R = 1.1kΩ, T = ..
MAX2373EGC+T ,LNAs with Step Attenuator and VGAELECTRICAL CHARACTERISTICS(V = 2.775V, RX_EN = high, R = 1.1kΩ, V = V /2, T = -40°C to +85°C. Typic ..
MAX5541ESA+ ,Low-Cost, +5V, Serial-Input, Voltage-Output, 16-Bit DACELECTRICAL CHARACTERISTICS(V = +5V ±5%, V = +2.5V, V = V = 0, T = T to T , unless otherwise noted. ..
MAX5541ESA+T ,Low-Cost, +5V, Serial-Input, Voltage-Output, 16-Bit DACFeatures♦ Full 16-Bit Performance Without AdjustmentsThe MAX5541 serial-input, voltage-output, 16-b ..
MAX5541ESA+T ,Low-Cost, +5V, Serial-Input, Voltage-Output, 16-Bit DACApplications Ordering InformationHigh-Resolution Offset and Gain AdjustmentPART TEMP RANGE PIN-PACK ..
MAX5544CSA ,Low-Cost / +5V / Serial-Input / Voltage-Output / 14-Bit DACApplicationsOrdering InformationHigh-Resolution Offset and Gain AdjustmentPART TEMP. RANGE PIN-PACK ..
MAX5544ESA ,Low-Cost / +5V / Serial-Input / Voltage-Output / 14-Bit DACELECTRICAL CHARACTERISTICS(V = +5V ±5%, V = +2.5V, V = V = 0, T = T to T , unless otherwise noted. ..
MAX5550ETE ,Dual, 10-Bit, Programmable, 30mA High-Output-Current DACApplicationsM AX5550E TE 16 Thin Q FN- E P * T1633F-3 ACZPIN Diode Biasing *EP = Exposed paddle. ..
MAX2370ETM+T
Complete 450MHz Quadrature Transmitter
General DescriptionThe MAX2370 integrated quadrature transmitter is
designed for 450MHz applications. The device takes a
differential I/Q baseband input and converts it up to
intermediate frequency (IF) through a quadrature modu-
lator and IF variable-gain amplifier (VGA). The signal is
then routed to an external IF filter and upconverted to RF
through an image-reject mixer and RF VGA. The signal
is further amplified with an on-chip power amplifier (PA)
driver. An IF synthesizer, an RF synthesizer, a local
oscillator buffer, and an SPI™/QSPI™/MICROWIRE™-
compatible, 3-wire programmable bus complete the
basic functional blocks of this IC.
The MAX2370 is available in a 48-pin TQFN package
with exposed paddle and is specified for the extended
temperature range (-40°C to +85°C).
Applications450MHz CDMA/WCDMA Phones
OFDM, cdma2000®, WCDMA, NMT
Wireless Data Links
Features450MHz Operating Frequency+8dBm Output Power
-64dBc Typical ACPR at ±885kHz Offset
-66dBc Typical ACPR at ±1.125MHz Offset100dB Power-Control RangeDual Synthesizer for RF and IF Local OscillatorsSPI/QSPI/MICROWIRE-Compatible 3-Wire
Interface BusSingle-Sideband UpconverterDirectly Drives External Power Amplifier
MAX2370
Complete 450MHz Quadrature Transmitter
Ordering Information19-0222; Rev 0; 5/05
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEPKG
CODEMAX2370ETM-40°C to +85°C48 Thin QFN-EP*
(7mm x 7mm)T4877-3
MAX2370ETM+-40°C to +85°C48 Thin QFN-EP*
(7mm x 7mm)T4877+3
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
*EP = Exposed paddle.
+Denotes lead-free package.
REF
N.C.
N.C.
N.C.
IFLO
VCC
TANK+
TANK-
N.C.LOCK
VCCDRV
VCC
IFIN+
IFIN-
RBIAS
N.C.
N.C.
N.C.
RFOUT1
N.C.
IFOUT-IFOUT+Q-
N.C.
CLK
N.C.GNDGNDLON.C.RFPLLV
CCRFCP
RFCPV
CCIFCP
IFCPGND47464544434241403938371415161718192021222324
SHDN
IDLE
TXGATE
TOP VIEW
MAX2370
+45-45
90°
IF PLLRF PLLSPI
INTERFACE90°
Pin Configuration/
Functional Diagram
MAX2370
Complete 450MHz Quadrature Transmitter
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, RFOUT, VCCIFCP, VCCRFCP,
VCCDRVto GND.................................................-0.3V to +3.6V
DI, SCLK, CS, GC, SHDN, TXGATE, IDLE,
LOCK to GND.........................................-0.3V to (VCC+ 0.3V)
AC Input Pins (IFIN_, Q_, I_, TANK_, REF,
RFPLL, LO) to GND.....................................................1V Peak
Digital Input Current (SHDN, TXGATE, IDLE,
SCLK, DI, CS)...............................................................±10mA
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 38.5mW/°C above +70°C).....3077mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
DC ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +3.3V, SHDN= IDLE= TXGATE= high, VGC= 2.5V, RBIAS= 10kΩ, registers set according to Table 1, fREF=
19.2MHz, no AC signals applied, TA= -40°C to +85°C. Typical values are at VCC= +3.0V, TA= +25°C, unless otherwise noted.)
(Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITSSupply Voltage RangeVCC2.73.3V
VGC = 0.6V5379
VGC = 1.95V5787
PRFOUT = +5.5dBm, IFG[2:0] = 011118
PRFOUT = +8dBm, IFG[2:0] = 011134
Addition for IFLO buffer3.47.7
IDLE = low610
Operating Supply Current
TXGATE = low57
Sleep-Mode Supply CurrentSHDN = 0V0.520µA
Logic-High Voltage0.7 x VCCV
Logic-Low Voltage0.3 x VCCV
Logic Input Current-5+5µA
GC Input CurrentVGC = 0.5V to 2.5V3.35µA
GC Input Current During ShutdownSHDN = low, VGC = 2.5V711µA
Lock Indicator High Voltage (Locked)47kΩ pullup loadVCC -
0.4VV
Lock Indicator Low Voltage (Unlocked)47kΩ pullup load0.5V
CAUTION! ESD SENSITIVE DEVICE
MAX2370
Complete 450MHz Quadrature Transmitter
AC ELECTRICAL CHARACTERISTICS(MAX2370 EV kit, VCC= +2.7V to +3.3V, SHDN= IDLE= TXGATE= high, VGC= 2.5V, RBIAS= 10kΩ, 50Ωsystem, TA= -40°C to
+85°C. Typical values are at VCC_= SHDN= IDLE= TXGATE= CS= 3.0V, fREF= 19.2MHz, LO input power = -15dBm, fLO= 575MHz,
fRFOUT= 455MHz, fIF= 120MHz, registers set according to Table 1, input voltage at I and Q = 130mVRMSdifferential,
cascade specifications assume 400ΩIF filter with 5dB insertion loss, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
MODULATORIF Frequency RangeTypically meets 30dB sideband suppression over this
frequency range95 to 195MHz
I/Q Common-Mode Input Voltage(Notes 2, 3)1.35VCC -
1.25V
I/Q Input CurrentVCM = 1.4V6µA
+25°C < TA < +85°C7087Gain-Control RangeVGC = 0.5V to 2.5VTA = -40°C85dB
Gain Variation Over TemperatureRelative to +25°C, TA = -40°C to +85°C-2.4, +3.4dB
Carrier SuppressionVGC = 2.5V3040dB
Sideband SuppressionVGC = 2.5V3040dB
IF Output Noise at Rx BandVGC set to give -12dBm IF output power, noise
measured at 10MHz offset (Note 4)-138-135dBm/Hz
fOFFSET = ±885kHz in 30kHz BW-66
fOFFSET = ±1.125MHz in 30kHz BW-69
fOFFSET = ±1.98MHz in 30kHz BW-84
IF Adjacent Channel Power Ratio
IS-95 Reverse Modulation
VGC set to give
-12dBm IF output
power, IFG[2:0] =
011fOFFSET = ±4MHz in 30kHz BW-89
dBc
UPCONVERTER AND PREDRIVERRFOUT Frequency RangeSee the Typical Operating Characteristics for typical gain
vs. frequency410 to 500MHz
LO Frequency RangeTypically meets 30dB image suppression over this range530 to 695MHz
LO and RFPLL Input Power-15-70dBm
Conversion Gain23dB
MPL Gain ChangeMPL = 0, gain relative to MPL = 1-3.4dB
+25°C < TA < +85°C3044RF Gain-Control RangeVGC = 0.5V to 2.5VTA = -40°C46dB
RF Image SuppressionAt maximum output power-20dBc
Rx Band Noise PowerPRFOUT = +8dBm, noise measured at +10MHz offset
(Note 4)-130-128.5dBm/Hz
CASCADED MODULATOR, UPCONVERTER, AND PREDRIVERRFOUT Output PowerMeets ACPR specifications (Note 4)5.510dBm
fOFFSET = ±885kHz in 30kHz BW-64-57
fOFFSET = ±1.125MHz in 30kHz BW-66-61
fOFFSET = ±1.98MHz in 30kHz BW-82-78OU T = + 8d Bm ,
IFG[2:0] = 011
fOFFSET = ±4MHz in 30kHz BW-86-78
fOFFSET = ±885kHz in 30kHz BW-64-58
fOFFSET = ±1.125MHz in 30kHz BW-67-62
fOFFSET = ±1.98MHz in 30kHz BW-81-78
Ad j acent C hannel P ow er Rati o
IS - 95 Rever se M od ul ati on ( N ote 4)
POUT = +5.5dBm,
IFG[2:0] = 011
fOFFSET = ±4MHz in 30kHz BW-86-85
dBc
MAX2370
Complete 450MHz Quadrature Transmitter
Note 1:Guaranteed by production test at TA= +25°C to +85°C, design and characterization at TA= -40°C.
Note 2:ACPR is met over the specified VCMrange.
Note 3:VCMmust be supplied by the I/Q baseband source with ±8µA current capability.
Note 4:Guaranteed by design and characterization to 6σ.
Note 5:When enabled with RCP_TURBO1 and RCP_TURBO2 (see Tables 3 and 4), the total charge-pump current is specified.
For all values of RCP, the total turbolock current is 1.63 times the corresponding nonturbo current value.
AC ELECTRICAL CHARACTERISTICS (continued)(MAX2370 EV kit, VCC= +2.7V to +3.3V, SHDN= IDLE= TXGATE= high, VGC= 2.5V, RBIAS= 10kΩ, 50Ωsystem, TA= -40°C to
+85°C. Typical values are at VCC_= SHDN= IDLE= TXGATE= CS= 3.0V, fREF= 19.2MHz, LO input power = -15dBm, fLO= 575MHz,
fRFOUT= 455MHz, fIF= 120MHz, registers set according to Table 1, input voltage at I and Q = 130mVRMSdifferential,
cascade specifications assume 400ΩIF filter with 5dB insertion loss, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITSOutput Power Variation Over
TemperatureRelative to +25°C, TA = -40°C to +85°C0, -2dB
IF PLLReference Frequency530MHz
Refer ence Fr eq uency S i g nal Level 0.10.6VP-P
IF Main-Divide Ratio25616,383
IF Reference-Divide Ratio22047
VCO Operating Range190 to 390MHz
ICP = 0096139174
ICP = 01135192240
ICP = 10190278348
Charge-Pump Source/Sink
Current
ICP = 11267390488
Turbolock Boost CurrentICP = 11, ICP_MAX = 1533774968µA
Charge-Pump Source/Sink
Current MatchingAll values of ICP, over compliance range6%
IF Charge-Pump Compliance0.5V C C I FC P -
0.5V V
RF PLLRF PLL Frequency RangeRF PLL operated at 2x LO frequency1300MHz
Reference Frequency530MHz
RF Main-Divide Ratio4096262,143
RF Reference-Divide Ratio28191
RCP = 00220325406
RCP = 01441650813
RCP = 10499738923
Charge-Pump Source/Sink
Current
RCP = 1171710631329
Turbolock Boost Current(Note 5)115216942118µA
Charge-Pump Source/Sink
Current MatchingAll values of RCP, over compliance range6%
RF Charge-Pump Compliance0.5V C C R FC P -
0.5V V
Phase-Detector Noise FloorRCP = 11, RCP_TURBO1 = RCP_TURBO2 = 0, 50kHz
comparison frequency-162dBc/Hz
MAX2370
Complete 450MHz Quadrature Transmitter
Typical Operating Characteristics(MAX2370 EV kit, VCC_= SHDN= IDLE= TXGATE= CS= 3.0V, fREF= 19.2MHz, LO input power = -15dBm, fLO= 575MHz, fRFOUT=
455MHz, fIF= 120MHz, RBIAS= 10kΩ, VGC= 2.5V, registers set according to Table 1, input voltage at I and Q = 130mVRMSdifferential,= +25°C, unless otherwise noted.)
RF OUTPUT POWER AND SUPPLY CURRENT
vs. GAIN-CONTROL VOLTAGE
MAX2370 toc01
VGC (V)
RF OUTPUT POWER (dBm)
SUPPLY CURRENT (mA)
POWER
CURRENT
IF OUTPUT POWER AND IF ACPR
vs. GAIN-CONTROL VOLTAGE
MAX2370 toc02
VGC (V)
IF OUTPUT POWER AND IF ACPR (dBm, dBc)
POWER
ACPR ±885kHz
ACPR ±1.125MHz
ACPR ±1.98MHz
RF OUTPUT POWER AND RF ACPR
vs. GAIN-CONTROL VOLTAGE
MAX2370 toc03
VGC (V)
RF OUTPUT POWER AND RF ACPR (dBm/dBc)
POWER
ACPR ±885kHz
ACPR ±1.125MHz
ACPR ±1.98MHz
RF GAIN, IMAGE SUPPRESSION, AND LO
SUPPRESSION vs. FREQUENCY
MAX2370 toc04
RF FREQUENCY (MHz)
RF GAIN (dB)
SUPPRESSION (dBc)
LO SUPPRESSION
IMAGE SUPPRESSION
GAIN
NORMALIZED IF OUTPUT POWER vs. IFG[2:0]MAX2370 toc05
NORMALIZED IF OUTPUT POWER (dB)314567
IFG[2:0] (DECIMAL)
RFOUT PORT S22
MAX2370 toc06
FREQUENCY (MHz)
S22 MAGNITUDE
S22 PHASE (
MAGNITUDE
PHASE
RFPLL PORT S11
MAX2370 toc07
FREQUENCY (MHz)
S11 MAGNITUDE
S11 PHASE (°)
MAGNITUDE
PHASE
LO PORT S11
MAX2370 toc08
FREQUENCY (MHz)
S11 MAGNITUDE
S11 PHASE (°)
MAGNITUDE
PHASE
FREQUENCY
IF OUTPUT SPECTRUMMAX2370 toc9
POWER (dBm)
CENTER: 120MHz, SPAN: 5MHz, RBW: 30kHz
POUT = -12dBm
MAX2370
Complete 450MHz Quadrature Transmitter
Pin Description
PINNAMEFUNCTIONRFOUTTransmitter RF Output. This open-collector output requires a pullup inductor to the supply voltage,
which can be part of the output matching network.
2, 10, 11, 16,
17, 32–35,
43, 47
N.C.No Connection. Leave these pins open-circuit. Some of these pins are internally connected.
3LOCKOpen-Drain Output Indicating LOCK Status of the IF and/or the RF PLLs. Requires an external
pullup resistor. Control using configuration register bits LD_MODE[1:0].
4VCCDRVPower Supply for the RF Driver Stage. Bypass to PC board ground with a capacitor placed as
close to the pin as possible. Do not share capacitor ground vias with other ground connections.IDLEDigital Input. Drive to logic-high for normal operation. Logic-low on IDLE shuts down everything
except the RF PLL. A small RC lowpass filter can be used to filter digital noise.
6VCCPower Supply for the Upconverter Stage. Bypass to PC board ground with a capacitor placed as
close to the pin as possible. Do not share capacitor ground vias with other ground connections.TXGATED i g i tal Inp ut. D r i ve to logic-high for nor m al op er ati on. Logic-low on TXG ATE shuts d ow n ever ythi ng
excep t the RF P LL, IF P LL, IF V C O. A sm al l RC l ow p ass can b e used to fi l ter d i g i tal noi se.
8, 9IFIN+, IFIN-
Differential IF Inputs to the RF Upconverter. IFIN+ and IFIN- are internally biased to typically VCC -
1.5V. The input impedance for this port is nominally 400Ω differential. AC-couple the output of the
differential IF filter to this port. Keep the differential lines as short as possible to minimize the
effects of stray pickup.RBIAS
Bias Resistor Connection. Internally biased to typically 1.18V. An external resistor must be
connected from RBIAS to ground to set the bias current for the upconverters and PA driver
stages. The nominal resistor value is 10kΩ. This value can be altered to optimize the linearity of
the driver stage.
Typical Operating Characteristics (continued)(MAX2370 EV kit, VCC_= SHDN= IDLE= TXGATE= CS= 3.0V, fREF= 19.2MHz, LO input power = -15dBm, fLO= 575MHz, fRFOUT=
455MHz, fIF= 120MHz, RBIAS= 10kΩ, VGC= 2.5V, registers set according to Table 1, input voltage at I and Q = 130mVRMSdifferential,= +25°C, unless otherwise noted.)
FREQUENCY
RF OUTPUT SPECTRUMMAX2370 toc10
POWER (dBm)
POUT = +8dBm
CENTER: 455MHz, SPAN: 5MHz, RBW: 30kHz
IF LOCAL OSCILLATOR SPECTRUM
MAX2370 toc11
FREQUENCY (MHz)
IF LO POWER (dBm)
PREF = -10dBm
MAX2370
Complete 450MHz Quadrature Transmitter
Pin Description (continued)
PINNAMEFUNCTION13, 14, 15CLK, DI, CSCMOS Inputs from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE Compatible). A small RC
lowpass filter on each of these pins can be used to reduce noise on these lines.
18, 19IFOUT-, IFOUT+
Differential IF Outputs. This port is active when IF_SEL is LOW and supports both FM and CDMA
modes. IFOUT+ and IFOUT- must be inductively pulled up to VCC and differentially loaded with
typically 560Ω. A 400Ω differential IF bandpass filter is connected between this port and IFIN+/-.
The pullup inductors can be part of the filter structure. The differential output impedance of this
port is nominally 400Ω, including the 560Ω external differential resistor. Keep the transmission
lines from these pins as short as possible to minimize the unintentional pickup of spurious signals
and noise.GC
RF and IF Gain-Control Analog Input. Accepts input voltages from 0.5V (minimum gain) to 2.5V
(maximum gain). When not driven, GC is internally biased to typically 1.5V. RC lowpass filter the
voltage applied to this pin to remove DAC noise or PDM clock spurs.VCCPower Supply for the IF VGA. Bypass to PC board ground with a 0.1µF capacitor placed as close
to the pin as possible. Do not share capacitor ground vias with other ground connections.VCCPower Supply for the I/Q Modulator. Bypass to PC board ground with a 0.1µF capacitor placed as
close to the pin as possible. Do not share capacitor ground vias with other ground connections.
23, 24Q+, Q-
Differential Q-Channel Baseband Inputs to the Modulator. Q+ and Q- connect directly to the
bases of a differential pair and require a typical 1.35V to (VCC - 1.5V) external common-mode bias
voltage.
25, 26I+, I-Differential I-Channel Baseband Inputs to the Modulator. I+ and I- connect directly to the bases of
a differential pair and require a typical 1.35V to (VCC - 1.5V) external common-mode bias voltage.SHDNDigital Input. Drive LOW to shut down the entire IC, drive high for normal operation. A small RC
lowpass filter can be used to filter digital noise.VCCPower Supply for the VCO Section. Bypass to PC board ground with a 0.1µF capacitor placed as
close to the pin as possible. Do not share capacitor ground vias with other ground connections.IFLOIF LO O utp ut. P r ovi d es access to the IF V C O outp ut and can b e used to d r i ve an exter nal P LL. It cane d i sab l ed b y l og i c- l ow on the BU F_E N contr ol b i t. IFLO i s i nter nal l y b i ased to typ i cal l y 1.5V .
30, 31TANK-, TANK+
Differential Tank Connections for the IF VCO. TANK+ and TANK- are internally biased to
approximately 1.6V and must be AC-coupled to the external tank (can be DC-coupled if tank does
not sink or source current).REF
Reference Frequency Input. REF is internally biased to approximately 1.0V and must be AC-
coupled to the reference source. This is a high-impedance port and must be externally terminated
in the desired impedance.VCCIFCP
Power Supply for the IF Charge Pump. This supply can be different from the system VCC. Bypass
to PC board ground with a minimum 0.1µF capacitor placed as close to the pin as possible. Do
not share capacitor ground vias with other ground connections.IFCP
High-Impedance IF Charge-Pump Output. Connect to the tune input of the IF VCO through the IF
PLL loop filter. Keep the connection from IFCP to the tune input as short as possible to prevent
spurious pickup.VCC
Power Supply for Digital Circuitry. Bypass to PC board ground with a minimum 0.1µF capacitor
placed as close to the pin as possible. Do not share capacitor ground vias with other ground
connections.
MAX2370
Detailed DescriptionThe MAX2370 complete quadrature transmitter accepts
differential I/Q baseband inputs with external common-
mode bias. A modulator upconverts the baseband
inputs to a 95MHz to 195MHz IF frequency. A gain-con-
trol voltage pin (GC) controls the gain of both the IF and
RF VGAs simultaneously to achieve the best current
consumption and linearity performance. The IF signal is
brought off-chip for filtering, then fed to a single side-
band upconverter followed by the RF VGA and PA dri-
ver. The RF upconverter requires an external VCO for
operation. The IF PLL, RF PLL, and operating mode can
be programmed by an SPI/QSPI/ MICROWIRE-compati-
ble 3-wire interface.
The following sections describe each block in the
Functional Diagram.
I/Q ModulatorDifferential in-phase (I) and quadrature-phase (Q)
inputs are designed to be DC-coupled and biased with
the baseband output from a digital-to-analog converter
(DAC). The I and Q inputs need a typical DC bias of
VCC/ 2 and a current-drive capability of 8µA. However,
common-mode voltages in the 1.35V to (VCC- 1.25V)
range are also acceptable. The I and Q input capaci-
tances are typically 0.6pF to ground on each pin. The
IF VCO output is fed into a divide-by-two quadrature
generator block to derive quadrature LO components
to drive the I/Q modulator. The output of the modulator
is fed into the IF VGA.
IF VCOThe IF VCO oscillates at twice the desired IF frequency.
The oscillation frequency is determined by external tank
components (see the IF Tank Designsection). Typical
spurious performance for the IF VCO is shown in the
Typical Operating Characteristics.
IFLO Output BufferIFLO provides a buffered LO output when BUF_EN is 1.
The IFLO output frequency is equal to the IF VCO fre-
quency, and the typical output power is -12dBm. This
output is intended for applications where the receive IF
is the same frequency as the transmit IF.
IF/RF PLLThe IF/RF PLL uses a charge-pump output to drive exter-
nal loop filters. The loop filter is typically a passive sec-
ond-order lead-lag filter. Outside the filter’s bandwidth,
phase noise is determined by the tank components. The
two components that contribute most significantly to
phase noise are the inductor and varactor. Use high-Q
inductors and varactors to maximize equivalent parallel
resistance. The IF_TURBO_CHARGE, RCP_TURBO1,
and RCP_TURBO2 bits can be set to enable turbo mode.
Turbo mode provides maximum charge-pump current
during frequency acquisition. Turbo mode is disabled
after frequency acquisition is achieved. When turbo
mode is disabled, charge-pump current returns to the
programmed levels as set by the ICP and RCP bits in the
CONFIG register (Table 3).
IF VGAThe IF VGA allows the IF output level to be controlled by
a voltage applied to the GC pin. The 0.5V to 2.5V voltage
range on GC provides a gain-control range of > 70dB,
with 2.5V providing maximum gain. The differential IF
output ports are optimized for the 95MHz to 195MHz fre-
quency range. Do not allow VGCto exceed VCC- 0.2V
as this may cause oscillations at cold temperatures.
Single-Sideband Mixer and RF VGAThe RF transmit mixer uses a single-sideband architec-
ture to eliminate an off-chip RF filter. The RF VGA fol-
lows the single-sideband mixer and is controlled by the
same GC voltage as the IF VGA to provide optimum
Complete 450MHz Quadrature Transmitter
Pin Description (continued)
PINNAMEFUNCTIONRFCP
High-Impedance RF Charge-Pump Output. Connect to the tune input of the RF VCO through the
RF PLL loop filter. Keep the connection from RFCP to the tune input as short as possible to
prevent spurious pickup.VCCRFCP
Power Supply for the RF Charge Pump. This supply can be different from the system VCC. Bypass
to PC board ground with a minimum 0.1µF capacitor placed as close to the pin as possible. Do
not share capacitor ground vias with other ground connections.RFPLLRF PLL Input. This port drives the RF PLL. RFPLL is internally biased to typically VCC - 0.8V.LORF LO Input. LO is internally biased to typically VCC - 0.8V.
45, 46, 48,GNDGround Connection. Solder the exposed paddle (EP) evenly to the board’s ground plane for
proper operation.
current consumption and linearity performance. The
power-control range of the RF VGA is typically 44dB.
PA DriverThe MAX2370 includes a PA driver that is optimized for
the 410MHz to 500MHz RF frequency range. The PA
driver is an open-collector output and requires a pullup
inductor to VCC. The pullup inductor can act as a shunt
element in a shunt-series matching network.
Programmable RegistersThe MAX2370 includes eight programmable registers
consisting of four divide registers, a configuration regis-
ter, an operational control register, a current control
register, and a test register. Each register consists of
24 bits. The 4 least significant bits (LSBs) are the regis-
ter’s address. The 20 most significant bits (MSBs) are
used for register data. All registers contain some “don’t
care” bits. These can be either a 0 or 1 and do not
affect operation (Figure 1). Data is shifted in MSB first,
followed by the 4-bit address. When CSis low, the
clock is active and data is shifted with the rising edge
of the clock. When CStransitions to high, the shift reg-
ister is latched into the register selected by the con-
tents of the address bits. Typical register settings for
the eight registers are shown in Table 1. The dividers
and control registers are programmed from the
SPI/QSPI/MICROWIRE-compatible serial port.
The RFM register sets the main frequency divide ratio
for the RF PLL. The RFR register sets the reference fre-
quency divide ratio. The RF VCO frequency can be
determined by the following:
RF VCO frequency = fREFx (RFM / RFR)
The IFM and IFR registers are similar:
IF VCO frequency = fREFx (IFM / IFR)
where fREFis the external reference frequency.
The operational control register (OPCTRL) controls the
state of the MAX2370. See Table 2 for a description of
each bit’s function.
The configuration register (CONFIG) sets the configura-
tion for the RF and IF PLL and the baseband I/Q input
levels. See Table 3 for a description of each bit’s function.
The current-control register (ICCCTRL) modifies the bias
current to accommodate different operating modes. In
the high-power mode, MPL = 1 sets the bias current and
conversion gain to deliver an output power of at least
+5.5dBm from the PA drivers. In the low-noise mode,
MPL = 0 reduces output noise by 2.5dB for any given
output power at the expense of 3.4dB less maximum
obtainable output power.
Power ManagementBias control is distributed among several functional
sections and can be controlled to accommodate many
different power-down modes as shown in Table 8.
The serial interface remains active during shutdown.
Setting bit SHDN_BIT = 0 or pin SHDN= GND powers
down the device. In either case, PLL programming and
register information is retained.
Applications Information
3-Wire Serial InterfaceFigure 3 shows the 3-wire interface timing diagram. The
3-wire bus is SPI/QSPI/MICROWIRE compatible.
Electromagnetic Compliance
ConsiderationsTo produce a low-spur and EMC-compliant transmitter,
minimize circular current-loop area to reduce H-field
radiation. To minimize circular current-loop area, bypass
all VCCpins as close to the device as possible and use
the distributed capacitance of a ground plane. To mini-
mize voltage drops, make VCCtraces short and wide.
Program only the necessary bits in any register to mini-
mize cycling of the serial interface’s clock. RC filtering
can also be used to slow the clock edges on the 3-wire
interface, reducing high-frequency spectral content.
RC filtering also provides transient protection by shunt-
ing high frequencies to ground, while the series resis-
tance attenuates the transients for error-free operation.
The same applies to the logic input pins (SHDN,
TXGATE, IDLE).
Place high-frequency bypass capacitors close to the
pins with a dedicated via for each capacitor to ground.
The 48-pin thin QFN-EP package provides minimal
ground inductance by using an exposed paddle under
the part. Provide at least five low-inductance vias under
the exposed paddle to ground. Use a solid ground
plane wherever possible. Any cutout in the ground
plane may act as a slot radiator and reduce its shield
effectiveness.
Keep RF LO traces as short as possible to reduce LO
radiation and susceptibility to interference.
IF Tank DesignThe IF tank is fully differential. The external tank compo-
nents for 120MHz IF operation are shown in the Typical
Application Circuit. See Maxim Application Note IF Tank
Design for the MAX2360at for more
information on designing tanks for alternate IFs.
MAX2370
Complete 450MHz Quadrature Transmitter
MAX2370Internal to the IC, the charge pump has a leakage of less
than 10nA. This is equivalent to a 300MΩshunt resistor.
The charge-pump output must see an extremely high
DC resistance of greater than 300MΩ. This minimizes
charge-pump spurs at the comparison frequency. Make
sure there is no solder flux under the varactor or loop filter
and use low-leakage capacitors.
Layout ConsiderationsThe MAX2370 EV kit can be used as a starting point for
layout. For best performance, take into consideration
power-supply issues as well as RF, LO, and IF layout.
Power-Supply LayoutTo minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central
VCCnode. The VCCtraces branch out from this node,
each going to a separate VCCpin of the MAX2370. At
the end of each trace is a bypass capacitor with imped-
ance to ground less than 1Ωat the frequency of inter-
est. This arrangement provides local decoupling at
each VCCpin. Use at least one via per bypass capaci-
tor for a low-inductance ground connection. Also, con-
nect the exposed paddle to the PC board GND with
multiple vias to provide the lowest inductance ground
connection possible.
Matching Network LayoutThe layout of a matching network can be very sensitive to
parasitic circuit elements. To minimize parasitic induc-
tance, keep all traces short and place components as
close to the IC as possible. To minimize parasitic capaci-
tance, a cutout in the ground plane (and any other planes)
below the matching network components can be used.
Keep traces short on the high-impedance ports (e.g., IF
inputs and outputs) to minimize shunt capacitance.
Tank LayoutKeep the traces coming out of the tank short to reduce
series inductance and shunt capacitance. Keep the
inductor pads and coupling capacitor pads small to
minimize stray shunt capacitance.
Chip InformationPROCESS: BiCMOS
Complete 450MHz Quadrature Transmitter
