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MAX2308EGI
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
General DescriptionThe MAX2306/MAX2308/MAX2309 are IF receivers
designed for dual-band, dual-mode, and single-mode
N-CDMA and W-CDMA cellular phone systems. The
signal path consists of a variable-gain amplifier (VGA)
and I/Q demodulator. The devices feature guaranteed
+2.7V operation, a gain control range of over 110dB,
and high input IP3 (-31dBm at 35dB gain, 3.4dBm at
-35dB gain).
Unlike similar devices, the MAX2306 family of receivers
includes dual oscillators and synthesizers to form a
self-contained IF subsystem. The synthesizer’s refer-
ence and RF dividers are fully programmable through a
3-wire serial bus, enabling dual-band system architec-
tures using any common reference and IF frequency.
The differential baseband outputs have enough band-
width to suit both N-CDMA and W-CDMA systems, and
offer saturated output levels of 2.7Vp-p at a low +2.75V
supply voltage. Including the low-noise voltage-con-
trolled oscillator (VCO) and synthesizer, the MAX2306
draws only 26mA from a +2.75V supply in CDMA (dif-
ferential IF) mode.
The MAX2306/MAX2308/MAX2309 are available in 28-
pin QFN packages.
ApplicationsSingle/Dual/Triple-Mode CDMA Handsets
Globalstar Dual-Mode Handsets
Wireless Data Links
W-CDMA Handsets
Wireless Local Loop (WLL)
FeaturesComplete IF Subsystem Includes VCO and
SynthesizerSupports Dual-Band, Triple-Mode OperationVGA with >110dB Gain ControlQuadrature DemodulatorHigh Output Level (2.7V)Programmable Charge-Pump CurrentSupports Any IF Frequency Between 40MHz and
300MHz3-Wire Programmable InterfaceLow Supply Voltage (+2.7V)
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Ordering Information
Selector Guide*Exposed paddle
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS(VCC= +2.7V to +3.6V, MODE = DIVSEL = SHDN= STBY= BUFEN= high, differential output load = 10kΩ, TA= -40°C to +85°C,
registers set to default power-up settings. Typical values are at VCC= +2.75V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +6.0VSHDNto GND.............................................-0.3V to (VCC + 0.3V)
STBY, BUFEN, MODE, EN, DATA,
CLK, DIVSEL...........................................-0.3V to (VCC+ 0.3V)
VGC to GND...............-0.3V, the lesser of +4.2V or (VCC+ 0.3V)
AC Signals TANKH ±, TANKL ±,
REF, FM ±, CDMA ±.................................................1.0V peak
Digital Input Current SHDN, MODE, DIVSEL,
BUFEN, DATA, CLK, EN, STBY.....................................±10mA
Continuous Power Dissipation (TA= +70°C)
28-Pin QFN (derate 28.5mW/°C above TA= +70°C)...........2W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
fIN = 183.7MHz, fREF= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for
+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS (continued)(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
fIN = 183.7MHz, fREF= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for
+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
Note 1:FM_IQ and FM_I modes are not available on MAX2309.
Note 2:Recommended operating frequency range. Contact factory for operating frequency outside this range.
Note 3:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -15dBm.
Note 4:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -50dBm.
Note 5:Guaranteed by design.
Note 6:Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at
1.25MHz below the LO frequency is applied at the specified level.
Note 7:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -23dBm.
Note 8:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -55dBm.
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and SynthesizerRECEIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX2306/8/9 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
RECEIVE SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
MAX2306/8/9 toc02
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (mA)
GAIN vs. VGC
MAX2306/8/9 toc03
VGC (V)
GAIN (dB)100200300400500
GAIN vs. INPUT FREQUENCYMAX2306/8/9 toc04
FREQUENCY (MHz)
GAIN (dB)
GAIN vs. BASEBAND FREQUENCY
MAX2306/8/9 toc05
FREQUENCY (MHz)
RELATIVE GAIN (dB)
THIRD-ORDER INPUT
INTERCEPT vs. GAIN
MAX2306/8/9 toc06
GAIN (dB)
IIP3 (dBm)
NOISE FIGURE vs. GAIN
MAX2306/8/9 toc07
GAIN (dB)
NF (dB)
NOISE FIGURE vs. TEMPERATURE
MAX2306/8/9 toc08
TEMPERATURE (°C)
NF (dB)
LOCK
VCO
VOLTAGE
VCO VOLTAGE vs. TIMEMAX2306/8/9 toc09
500µs/div
SHDN
1V/div
Typical Operating Characteristics(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, fREF= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and SynthesizerIF PORT PARALLEL RESISTANCE
vs. FREQUENCY
MAX2306/8/9 toc10
FREQUENCY (MHz)
EQUIVALENT PARELLEL RESISTANCE (
MAX2306/8/9 toc12
EQUIVALENT PARELLEL RESISTANCE (240320160400480560
FREQUENCY (MHz)
TANK PORT PARALLEL RESISTANCE
vs. FREQUENCYMAX2306/8/9 toc13
EQUIVALENT PARELLEL CAPACITANCE (160240320400400560
TANK PORT PARALLEL CAPACITANCE
vs. FREQUENCY
Typical Operating Characteristics (continued)(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, fREF= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
_______________Detailed Description
MAX2306The MAX2306 is intended for dual-band (PCS and cel-
lular) and dual-mode code division multiple access
(CDMA) and FM applications (Figure 1). The device
includes an IF variable-gain amplifier, quadrature
demodulator, dual VCOs, and dual-frequency synthe-
sizers(Functional Diagram). Dual VCOs are provided
for applications using different IF frequencies for each
mode or band of operation. The analog FM output sig-
nal can be configured for conversion to the I channel,
or it may be converted in quadrature to both the I and
Q channels. The MAX2306’s operation modes are
described in Table 1. These modes are set by pro-
gramming the control register and setting logic levels
on control pins. If MODE is left floating, the internal reg-
ister controls the operation. If driven high or low, mode
will override certain register bits, as shown in Table 1.
MAX2308The MAX2308 supports dual-band, triple mode with
common IF VCO. As with the MAX2306, the FM mode
can be configured for conversion to the I port or quad-
rature conversion to both the I and Q ports (Figure 2).
The MAX2308’s operational modes are described in
Table 2. These modes are set by programming the con-
trol register.
MAX2309The MAX2309 quadrature demodulators are simplified
versions of the MAX2306 that can be used in single-
mode CDMA or triple mode using an external FM dis-
criminator (Figure 3). The MAX2309 VCO is optimized
for the 67MHz to 300MHz IF frequency range.
The MAX2309 includes a buffered output for the VCO.
The buffered VCO output can be used to support sys-
tems implementing traditional limiting IF stages for FM
demodulation in dual-mode phones as well as for the
transmit LO in TDD systems. This buffered output can
be configured for the VCO frequency (twice the IF fre-
quency) or one-half the VCO frequency (IF frequency).
The BUFENpin enables this feature. A standby mode,
in which only the VCO and synthesizer are operational,
can be selected through the serial interface or the
STBYpin. The MAX2309’s operational modes are
described in Table 3. These modes are set by pro-
gramming the control register and/or setting logic levels
on control pins. If the control pins (STBY, BUFEN,
DIVSEL) are left floating, the internal register controls
the operational mode. If driven high or low, the control
pins will override certain register bits, as shown in
Table 3.
Applications Information
Variable-Gain Amplifier and DemodulatorThe MAX2306 family provides a VGA with exceptional
gain range. The MAX2306/MAX2308 support multimode
applications with dual differential inputs, selectable with
the IN_SEL (IS) control bit. On the MAX2306, this func-
tion can be controlled with the MODE pin, which over-
rides the IS control bit. The VGA’s gain is controlled
over a 110dB range with the VGC pin. The output of the
VGA drives the RF ports of a quadrature demodulator.
The MAX2306/MAX2308 provide two types of FM
demodulation, controlled by the FM_TYPE (FT) control
bit. When FM_TYPE is “1,” the signal is passed through
both the I and Q signal paths for subsequent lowpass
filtering and A/D conversion at baseband. If FM_TYPE
is “0,” the FM signal is passed through the I mixer only.
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Voltage-Controlled Oscillator,
Buffers, and Quadrature GenerationThe LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an on-
chip differential oscillator, and an off-chip high-Q reso-
nant network.Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2306 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
control bit. They oscillate at twice the desired LO fre-
quency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
The MAX2309 buffers the output of the VCO and pro-
vides this signal at the LOOUT pin. This signal is
enabled by the BUFEN(BE) control bit or by theBUFENcontrol pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.
Quadrature downconversion is realized by providing in-
phase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.
MAX2306/MAX2308/MAX2309
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 1. MAX2306 Control Register States
Note:H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.
The appropriate latch outputs provide I and Q signals
at the desired LO frequency.
SynthesizerThe VCO’s output frequency is controlled by an internal
phase-locked-loop (PLL) dual-modulus synthesizer. The
loop filter is off-chip to simplify loop design for emerg-
ing applications. The tunable resonant network is also
off-chip for maximum Q and for system design flexibili-
ty. The VCO output frequency is divided down to the
desired comparison frequency with the M counter. The
M counter consists of a 4-bit A swallow counter and a
10-bit P counter. A reference signal is provided from an
external source and is divided down to the comparison
frequency with the R counter. The two divided signals
are compared with a three-state digital phase-frequen-
cy detector. The phase-detector output drives a
charge-pump as well as lock-detect logic and tur-
bocharge control logic. The charge-pump output
(CP_OUT) pin is processed by the loop filter and drives
the tunable resonant network, altering the VCO frequen-
cy and closing the loop.
Multimode applications are supported by two indepen-
dent programmable registers each for the M counter
(M1, M2), the R counter (R1, R2), and the charge-pump
output current magnitude (CP1, CP2). The DIVSEL (DS)
bit selects which set of registers is used. It can be over-
ridden by the MAX2306’s MODE pin or the MAX2309’s
DIVSEL pin. Programming these registers is discussed
in the 3-Wire Interface and Registerssection.
