MAX2306ETI+T-MAX2308ETI+T-MAX2309ETI+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX2308ETI+T ,CDMA IF VGAs and I/Q Demodulators with VCO and SynthesizerELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differen ..
MAX2309EGI ,CDMA IF VGAs and I/Q Demodulators with VCO and SynthesizerBlock Diagram appears at end of data sheet.Wireless Local Loop (WLL)Selector GuidePART MODE DESCRIP ..
MAX2309ETI+T ,CDMA IF VGAs and I/Q Demodulators with VCO and SynthesizerFeaturesThe MAX2306/MAX2308/MAX2309 are IF receivers♦ Complete IF Subsystem Includes VCO anddesigne ..
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MAX534AEEE ,+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
MAX534AEEE ,+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
MAX534AEEE+T ,+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
MAX534BCEE ,+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers
MAX5352ACUA ,Low-Power, 12-Bit Voltage-Output DACs with Serial InterfaceFeaturesThe MAX5352/MAX5353 combine a low-power, voltage- ' 12-Bit DAC with Configurable Output Amp ..
MAX5352AEPA ,Low-Power, 12-Bit Voltage-Output DACs with Serial InterfaceGeneral Description __________

MAX2306ETI+T-MAX2308ETI+T-MAX2309ETI+T
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
neral DescriptionThe MAX2306/MAX2308/MAX2309 are IF receivers
designed for dual-band, dual-mode, and single-mode
N-CDMA and W-CDMA cellular phone systems. The
signal path consists of a variable-gain amplifier (VGA)
and I/Q demodulator. The devices feature guaranteed
+2.7V operation, a gain control range of over 110dB,
and high input IP3 (-31dBm at 35dB gain, 3.4dBm at
-35dB gain).
Unlike similar devices, the MAX2306 family of receivers
includes dual oscillators and synthesizers to form a
self-contained IF subsystem. The synthesizer’s refer-
ence and RF dividers are fully programmable through a
3-wire serial bus, enabling dual-band system architec-
tures using any common reference and IF frequency.
The differential baseband outputs have enough band-
width to suit both N-CDMA and W-CDMA systems, and
offer saturated output levels of 2.7Vp-p at a low +2.75V
supply voltage. Including the low-noise voltage-con-
trolled oscillator (VCO) and synthesizer, the MAX2306
draws only 26mA from a +2.75V supply in CDMA (dif-
ferential IF) mode.
The MAX2306/MAX2308/MAX2309 are available in 28-
pin Thin QFN and QFN packages.
Applications
Single/Dual/Triple-Mode CDMA Handsets
Globalstar Dual-Mode Handsets
Wireless Data Links
W-CDMA Handsets
Wireless Local Loop (WLL)
FeaturesComplete IF Subsystem Includes VCO and
SynthesizerSupports Dual-Band, Triple-Mode OperationVGA with >110dB Gain ControlQuadrature DemodulatorHigh Output Level (2.7V)Programmable Charge-Pump CurrentSupports Any IF Frequency Between 40MHz and
300MHz3-Wire Programmable InterfaceLow Supply Voltage (+2.7V)DMA IF VGAs and I/Q Demodulators ith VCO and Synthesize
19-2014; Rev 3; 8/04
EVALUATION KIT AVAILABLE
Pin Configurations appear at end of data sheet.
Block Diagram appears at end of data sheet.
Ordering Information
Selector Guide
*Exposed paddle
PARTTEMP RANGEPIN-PACKAGE
MAX2306EGI-40°C to +85°C28 QFN-EP*
MAX2306ETI-40°C to +85°C28 TQFN-EP*
MAX2308EGI-40°C to +85°C28 QFN-EP*
MAX2308ETI-40°C to +85°C28 TQFN-EP*
MAX2309EGI-40°C to +85°C28 QFN-EP*
MAX2309ETI-40°C to +85°C28 TQFN-EP*
PARTMODEDESCRIPTIONINPUT RANGE
MAX2306
AMPS,
Cellular CDMA,
PCS CDMA
Dual Band, Triple Mode with Two
IF VCOs40MHz to 300MHz
MAX2308
AMPS,
Cellular CDMA,
PCS CDMA
Dual Band, Triple Mode with Common
IF VCO70MHz to 300MHz
MAX2309
External AMPS,
Cellular CDMA,
PCS CDMA
Dual Band, Triple Mode (Drives External
AMPS Discriminator)70MHz to 300MHz
CDMA IF VGAs and I/Q Demodulators ith VCO and Synthesizer
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +2.7V to +3.6V, MODE = DIVSEL = SHDN= STBY= BUFEN= high, differential output load = 10kΩ, TA= -40°C to +85°C,
registers set to default power-up settings. Typical values are at VCC= +2.75V and TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +6.0V
SHDNto GND.............................................-0.3V to (VCC + 0.3V)
STBY, BUFEN, MODE, EN, DATA,
CLK, DIVSEL...........................................-0.3V to (VCC+ 0.3V)
VGC to GND...............-0.3V, the lesser of +4.2V or (VCC+ 0.3V)
AC Signals TANKH ±, TANKL ±,
REF, FM ±, CDMA ±.................................................1.0V peak
Digital Input Current SHDN, MODE, DIVSEL,
BUFEN, DATA, CLK, EN, STBY.....................................±10mA
Continuous Power Dissipation (TA= +70°C)
28-Pin QFN (derate 28.5mW/°C above TA= +70°C)...........2W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TA = +25°C25.937.5CDMA modeTA = -40°C to +85°C41.5
TA = +25°C25.436.7FM_IQ modeTA = -40°C to +85°C40.6
TA = +25°C24.735.7FM_I modeTA = -40°C to +85°C39.5
TA = +25°C12.318.8STANDBY (VCO_H)TA = -40°C to +85°C20.7
TA = +25°C11.418.4STANDBY (VCO_L)TA = -40°C to +85°C20.3
Supply Current
(Note 1)ICC
Addition for LO out (BUFEN = low)3.5
Shutdown CurrentICCSHDN = low1.510μA
Register Shutdown CurrentICC45.8mA
Logic High2.0V
Logic Low0.5V
Logic High Input CurrentIIH2μA
Logic Low Input CurrentIIL2μA
VGC Control Input Current0.5V < VVGC < 2.3V-55μA
VGC Control Input Current
During ShutdownSHDN = low1μA
Lock Indicator High (locked)47kΩ load2.0V
Lock Indicator Low (unlocked)47kΩ load0.5V
DC Offset VoltageI+ to I- and Q+ to Q-, PLL locked-20±1.5+20mV
Common-Mode Output VoltageVCC = +2.75VVCC - 1.4V
DMA IF VGAs and I/Q Demodulators ith VCO and SynthesizeAC ELECTRICAL CHARACTERISTICS
(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
fIN = 183.7MHz, fREF= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for
+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input FrequencyfIN(Note 2)40300MHz
Reference FrequencyfREF39MHz
Frequency Reference Signal
LevelVREF0.2Vp-p
SIGNAL PATH, CDMA MODE
Gain = -35dB, (Note 3)3.4
Input 3rd-Order InterceptIIP3Gain = +35dB, TA = -40°C to +85°C
(Notes 4, 5)-38-31.0dBm
Gain = -35dB-9Input 1dB CompressionP1dBGain = +35dB-44dBm
Gain = -35dB-14.8Input 0.25dB Desensitization(Note 6)Gain = +35dB-49dBm
Minimum Voltage GainAVVVGC = 0.5V (Note 5)-56-51dB
Maximum Voltage GainAVVVGC = 2.3V (Note 5)5761dB
Gain = -35dB62.9DSB Noise FigureNFGain = +35dB6.36dBm
SIGNAL PATH, FM_IQ MODE
Gain = -35dB, (Note 7)-6.5
Input 3rd-Order InterceptIIP3Gain = +35dB, TA = -40°C to +85°C
(Notes 5, 8)-40.2-32dBm
Gain = -35dB-20Input 1dB CompressionP1dBGain = +35dB-44dBm
Minimum Voltage GainAVVVGC = 0.5V (Note 5)-56.7-52dB
Maximum Voltage GainAVVVGC = 2.3V (Note 5)5659.5dB
SIGNAL PATH, CDMA AND FM_IQ MODE
Gain Variation Over TemperatureNormalized to +25°C±2.5dB
Baseband 0.5dB Bandwidth4.2MHz
Quadrature SuppressionTA = -40°C to +85°C (Note 5)2840dB
LO to Baseband Leakage1mVp-p
Saturated Output LevelVSATDifferential2.7Vp-p
PHASE-LOCKED LOOP
FVCO_L(Note 2)80300VCO Tune RangeFVCO_H(Note 2)135600MHz
LO_OUT Output PowerPLORL = 50Ω, BUFEN = low-13.7dBm
VCO Minimum Divide RatioM1, M2256
VCO Maximum Divide RatioM1, M216383
REF Minimum Divide RatioR1, R22
CDMA IF VGAs and I/Q Demodulators ith VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2306/MAX2308/MAX2309 EV kit, VCC= +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16,
fIN = 183.7MHz, fREF= 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for
+35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
Note 1:FM_IQ and FM_I modes are not available on MAX2309.
Note 2:Recommended operating frequency range. Contact factory for operating frequency outside this range.
Note 3:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -15dBm.
Note 4:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -50dBm.
Note 5:Guaranteed by design.
Note 6:Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at
1.25MHz below the LO frequency is applied at the specified level.
Note 7:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -23dBm.
Note 8:f1= 183.7MHz, f2= 183.71MHz, Pf1= Pf2 = -55dBm.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
REF Maximum Divide RatioR1, R22047
Minimum Phase Detector
Comparison Frequency(Note 5)20kHz
Maximum Phase Detector
Comparison Frequency(Note 5)1500kHz
1kHz offset, TA = -40°C to +85°C-79.6
12.5kHz offset, TA = -40°C to +85°C-94.6
30kHz offset, TA = -40°C to +85°C-105
120kHz offset, TA = -40°C to +85°C-115.3
Phase Noise
900kHz offset, TA = -40°C to +85°C-125
dBc/Hz
TURBO LOCK
Acquisition, CPX = XX, TC =1148021002650
Locked, CPX = 00105150190
Locked, CPX = 01150210265
Locked, CPX = 10210300380
Charge-Pump Source/Sink
Current
Locked, CPX = 11300425530
Charge-Pump Source/Sink
Matching
Locked, all values of CPX,
0.5V < VCP < VCC - 0.5V0.210%
DMA IF VGAs and I/Q Demodulators ith VCO and SynthesizeRECEIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2306/8/9 toc01
SUPPLY VOLTAGE (V)
(mTA = +85°C
TA = +25°C
TA = -40°C
RECEIVE SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
AX2306/8/9 toc02
SUPPLY VOLTAGE (V)
(m
TA = -40°C
TA = +25°C
TA = +85°C
GAIN vs. VGC
AX2306/8/9 toc03
VGC (V)
(d
TA = +25°C
TA = -40°C
TA = +85°C100200300400500
GAIN vs. INPUT FREQUENCY
AX2306/8/9 toc04
FREQUENCY (MHz)
(d
VGC = 2.5V
GAIN vs. BASEBAND FREQUENCY
AX2306/8/9 toc05
FREQUENCY (MHz)
(d
THIRD-ORDER INPUT
INTERCEPT vs. GAIN
AX2306/8/9 toc06
GAIN (dB)
IIP
(d
TA = -40°C
TA = +85°C
TA = +25°C
NOISE FIGURE vs. GAIN
X2306/8/9 toc07
GAIN (dB)
(d
NOISE FIGURE vs. TEMPERATURE
2306/8/9 toc08
TEMPERATURE (°C)
(d
GAIN = 50dB
LOCK
VCO
VOLTAGE
VCO VOLTAGE vs. TIME
MAX2306/8/9 toc09
500μs/div
SHDN
LOCK TIME
1.83ms
1V/div
Typical Operating Characteristic
(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, fREF= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
CDMA IF VGAs and I/Q Demodulators ith VCO and Synthesizer
IF PORT PARALLEL RESISTANCE
vs. FREQUENCY
AX2306/8/9 toc10
FREQUENCY (MHz)
(Ω
MEASURED DIFFERENTIALLY
CDMA PORT
FM PORT
X2306/8/9 toc12
(Ω240320160400480560
FREQUENCY (MHz)
TANK PORT PARALLEL RESISTANCE
vs. FREQUENCY
TANKH
TANKL
MEASURED DIFFERENTIALLY
2306/8/9 toc13
FREQUENCY (MHz)
(p160240320400400560
TANK PORT PARALLEL CAPACITANCE
vs. FREQUENCY
TANK
TANKL
MEASURED DIFFERENTIALLY
Typical Operating Characteristics (continued)
(MAX2306/MAX2308/MAX2309 EV kits, VCC= +2.75V, registers set to default power-up states, fIN= 183.7MHz, fREF= 19.2MHz,
synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN= high, VGC set for +35dB voltage gain, differential output load
= 10kΩ, all power levels referred to 50Ω, TA= +25°C, unless otherwise noted.)
LOOUT PORT
S11 vs. FREQUENCY
2310 toc14
START:10MHz
STOP:600MHz
AX2306/8/9 toc11
FREQUENCY (MHz)
(p
IF PORT PARALLEL CAPACITANCE
vs. FREQUENCY
CDMA PORT
FM PORT
MEASURED DIFFERENTIALLY
DMA IF VGAs and I/Q Demodulators ith VCO and SynthesizePin Description
PIN
MAX2306MAX2308MAX2309
NAMEFUNCTION
1, 28—— TANKL+,
TANKL-Differential Tank Input for Low-Frequency Oscillator1, 4—N.C.No Connection. Must be left open-circuit.
2, 32, 31, 2 TANKH+,
TANKH-Differential Tank Input for High-Frequency Oscillator—3BUFENLO Buffer Amplifier—active low——MODEMode Select. High selects CDMA mode; low selects FM mode.—4LOOUT
Internal VCO Output. Depending on setting of BD bit, LOOUT is
either the VCO frequency (twice the IF frequency) or one-half the
VCO frequency (equal to the IF frequency).55VCC+2.7V to +5.5V Supply66GNDGround77REFReference Frequency Input88SHDNShutdown Input—active low. Low powers down entire device,
including registers and serial interface.
9, 109, 109, 10 IOUT+,
IOUT-
Differential In-Phase Baseband Output, or FM signal output if FM_I
mode is selected.1111LOCKLock Output—open-collector pin. Logic high indicates phase-locked
condition.
12, 1312, 1312, 13QOUT-,
QOUT+
Differential Quadrature-Phase Baseband Output. Disabled if FM_I
mode is selected.1414CLKClock input of the 3-wire serial bus1515ENEnable Input. When low, input shift register is enabled.1616DATAData input of the 3-wire serial bus.1717VCC+2.7V to +5.5V Supply1818VGCVGA Gain Control Input. Control voltage range is 0.5V to 2.3V.
19, 2019, 2019, 20CDMA-,
CDMA+Differential CDMA Input. Active in CDMA mode.21—FM+Differential Positive Input. Active in FM mode.22—FM-Differential Negative Input for FM signal. Bypass to GND for
single-ended operation.—22STBYStandby Input—active low. Low powers down VGA and demodulator
while keeping VCO, PLL, and serial bus on.
23, 2423, 2423, 24BYPBypass Node. Must be capacitively decoupled (bypassed) to pin 17.
CDMA IF VGAs and I/Q Demodulators ith VCO and Synthesizer
_______________Detailed Description
MAX2306
The MAX2306 is intended for dual-band (PCS and cel-
lular) and dual-mode code division multiple access
(CDMA) and FM applications (Figure 1). The device
includes an IF variable-gain amplifier, quadrature
demodulator, dual VCOs, and dual-frequency synthe-
sizers(Functional Diagram). Dual VCOs are provided
for applications using different IF frequencies for each
mode or band of operation. The analog FM output sig-
nal can be configured for conversion to the I channel,
or it may be converted in quadrature to both the I and
Q channels. The MAX2306’s operation modes are
described in Table 1. These modes are set by pro-
gramming the control register and setting logic levels
on control pins. If MODE is left floating, the internal reg-
ister controls the operation. If driven high or low, mode
will override certain register bits, as shown in Table 1.
MAX2308
The MAX2308 supports dual-band, triple mode with
common IF VCO. As with the MAX2306, the FM mode
can be configured for conversion to the I port or quad-
rature conversion to both the I and Q ports (Figure 2).
The MAX2308’s operational modes are described in
Table 2. These modes are set by programming the con-
trol register.
MAX2309
The MAX2309 quadrature demodulators are simplified
versions of the MAX2306 that can be used in single-
mode CDMA or triple mode using an external FM dis-
criminator (Figure 3). The MAX2309 VCO is optimized
for the 67MHz to 300MHz IF frequency range.
The MAX2309 includes a buffered output for the VCO.
The buffered VCO output can be used to support sys-
tems implementing traditional limiting IF stages for FM
demodulation in dual-mode phones as well as for the
transmit LO in TDD systems. This buffered output can
be configured for the VCO frequency (twice the IF fre-
quency) or one-half the VCO frequency (IF frequency).
The BUFENpin enables this feature. A standby mode,
in which only the VCO and synthesizer are operational,
can be selected through the serial interface or the
STBYpin. The MAX2309’s operational modes are
described in Table 3. These modes are set by pro-
gramming the control register and/or setting logic levels
on control pins. If the control pins (STBY, BUFEN,
DIVSEL) are left floating, the internal register controls
the operational mode. If driven high or low, the control
pins will override certain register bits, as shown in
Table 3.
Applications Informationariable-Gain Amplifier and Demodulator
The MAX2306 family provides a VGA with exceptional
gain range. The MAX2306/MAX2308 support multimode
applications with dual differential inputs, selectable with
the IN_SEL (IS) control bit. On the MAX2306, this func-
tion can be controlled with the MODE pin, which over-
rides the IS control bit. The VGA’s gain is controlled
over a 110dB range with the VGC pin. The output of the
VGA drives the RF ports of a quadrature demodulator.
The MAX2306/MAX2308 provide two types of FM
demodulation, controlled by the FM_TYPE (FT) control
bit. When FM_TYPE is “1,” the signal is passed through
both the I and Q signal paths for subsequent lowpass
filtering and A/D conversion at baseband. If FM_TYPE
is “0,” the FM signal is passed through the I mixer only.
Pin Description (continued)
PIN
MAX2306MAX2308MAX2309NAMEFUNCTION2525BYPBypass Node. Must be capacitively decoupled (bypassed)
to ground.2626CP_OUTCharge-Pump Output2727GNDGround2821N.C.No Connection—28DIVSELHigh selects M1/R1; low selects M2/R2.
Exposed PaddleEPGround
DMA IF VGAs and I/Q Demodulators ith VCO and SynthesizeVoltage-Controlled Oscillator,
Buffers, and Quadrature Generation
The LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an on-
chip differential oscillator, and an off-chip high-Q reso-
nant network.Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2306 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
control bit. They oscillate at twice the desired LO fre-
quency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
bit.
The MAX2309 buffers the output of the VCO and pro-
vides this signal at the LOOUT pin. This signal is
enabled by the BUFEN(BE) control bit or by the
BUFENcontrol pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.
Quadrature downconversion is realized by providing in-
phase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.
Figure 1. MAX2306 Typical Operating Circuit
MAX2306
BYP
BYP
FM-
FM+
CDMA+
CDMA
3-WIRE
DAC
0.1μF0.01μF
0.068μF
47pF
2pF
33pF
0.01μF
10kΩ
2.4kΩ
10kΩ33pF
47pF
33nH
0.01μF
680Ω
CDMA-
LOCK
VGC
VCC
VCC
VCC
VCC
DATA
CLK
QOUT+
QOUT-
TANKH-
IOUT-
IOUT+
REF
GND
VCC
MODE
TANKH+
TANKL-
GND
CP_OUT
BYP
SHDN
TANKL+
0.01μF
VCC
47pF
10kΩ
47kΩ10kΩ
2pF
33pF10kΩ
10kΩ33pF
33nH
CDMA IF VGAs and I/Q Demodulators ith VCO and Synthesizer
Table 1. MAX2306 Control Register States
MODE
SHDN
PINSLShutdown pin completely
powers down the chipSHUTDOWN
ACTION
RESULT
OPERATIONAL
MODE
TEST_MODE
CP POL
TEST_ENX
TURBOCHARGE
DIVSEL
VCO_BYPVCO_SELXX
BUF_DIV
BUFENX
FM_TYPE
IN_SEL
STBY
SHDNCONTROL REGISTERSXXXXHX0 in shutdown register bit leaves
serial port activeSHUTDOWNXXXXXXX0XX0XHX0 in standby register bit turns off
VGA and modulator onlySTANDBYXX10HHMode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to highCDMAXXXXX1X1FHFloating mode pin returns control
to registerCDMA11XX11X1LHMode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to lowFM_IQXXXXX101FHFloating mode pin returns control
to registerFM_IQXX0101LHMode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to lowFM_IXXXXX111FH
Floating pins return control to
registerFM_IXX0111
Note:H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.
The appropriate latch outputs provide I and Q signals
at the desired LO frequency.
Synthesizer
The VCO’s output frequency is controlled by an internal
phase-locked-loop (PLL) dual-modulus synthesizer. The
loop filter is off-chip to simplify loop design for emerg-
ing applications. The tunable resonant network is also
off-chip for maximum Q and for system design flexibili-
ty. The VCO output frequency is divided down to the
desired comparison frequency with the M counter. Thecounter consists of a 4-bit A swallow counter and a
10-bit P counter. A reference signal is provided from an
external source and is divided down to the comparison
frequency with the R counter. The two divided signals
are compared with a three-state digital phase-frequen-y detector. The phase-detector output drives a
charge-pump as well as lock-detect logic and tur-
bocharge control logic. The charge-pump output
(CP_OUT) pin is processed by the loop filter and drives
the tunable resonant network, altering the VCO frequen-
cy and closing the loop.
Multimode applications are supported by two indepen-
dent programmable registers each for the M counter
(M1, M2), the R counter (R1, R2), and the charge-pump
output current magnitude (CP1, CP2). The DIVSEL (DS)
bit selects which set of registers is used. It can be over-
ridden by the MAX2306’s MODE pin or the MAX2309’s
DIVSEL pin. Programming these registers is discussed
in the 3-Wire Interface and Registerssection.

Partno	Mfg	Dc	Qty	Available	Descript
MAX2306ETI+T	MAXIM	N/a	43	avai	CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
MAX2308ETI+T	MAXIM	N/a	55	avai	CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
MAX2309ETI+T	MAXIM	N/a	40	avai	CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer