MAX197BCNI+ ,Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interfacefeatures include a 5MHz bandwidth track/hold, a100ksps throughput rate, software-selectable interna ..
MAX197BCWI ,Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus InterfaceMAX19719-0381; Rev 1; 6/96Multi-Range (±10V, ±5V, +10V, +5V),Single +5V, 12-Bit DAS with 8+4 Bus In ..
MAX197BCWI+ ,Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus InterfaceMAX19719-0381; Rev 2; 9/01Multi-Range (±10V, ±5V, +10V, +5V),Single +5V, 12-Bit DAS with 8+4 Bus In ..
MAX197BEAI ,Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus InterfaceFeatures' 12-Bit Resolution, 1/2LSB LinearityThe MAX197 multi-range, 12-bit data-acquisition sys-te ..
MAX197BENI ,Multi-Range (【10V, 【5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interfacefeatures include a 5MHz bandwidth track/hold, a100ksps throughput rate, software-selectable interna ..
MAX197BENI+ ,Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interfacefeatures include a 5MHz bandwidth track/hold, a100ksps throughput rate, software-selectable interna ..
MAX5003EEE+T ,High-Voltage PWM Power-Supply ControllerApplicationsPin ConfigurationTelecommunication Power SuppliesISDN Power SuppliesTOP VIEW+42V Automo ..
MAX5003EEE+T ,High-Voltage PWM Power-Supply ControllerFeaturesThe MAX5003 high-voltage switching power-supply♦ Wide Input Range: 11V to 110Vcontroller ha ..
MAX5003ESE ,High-Voltage PWM Power-Supply ControllerApplicationsPin ConfigurationTelecommunication Power SuppliesISDN Power SuppliesTOP VIEW+42V Automo ..
MAX5003ESE+ ,High-Voltage PWM Power-Supply ControllerELECTRICAL CHARACTERISTICS(V+ = V = V = +12V, V = 2V, V = 0, R = R = 200kΩ, T = T to T , unless oth ..
MAX5005BCUB ,150mA USB LDO Regulators with ±15kV TVS and µP ResetApplicationsMAX5007_CUB* 0°C to +70°C 10 µMAXHighUSB Peripherals*Insert “A” for a 7.5% reset thresh ..
MAX5008CUB+ ,Regulated 5V USB Charge Pump with Programmable Current LimitApplicationsOrdering InformationFlash Memory SuppliesPART TEMP RANGE PIN-PACKAGEUSB Host DevicesMAX ..
MAX197ACAI+-MAX197ACAI+T-MAX197ACNI+-MAX197ACWI+-MAX197AEAI+-MAX197AENI+-MAX197AEWI+-MAX197BCAI+-MAX197BCNI+-MAX197BCWI+-MAX197BENI+-MAX197BEWI+
Multi-Range (±10V, ±5V, +10V, +5V), Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________General DescriptionThe MAX197 multi-range, 12-bit data-acquisition sys-
tem (DAS) requires only a single +5V supply for opera-
tion, yet accepts signals at its analog inputs that may
span both above the power-supply rail and below
ground. This system provides 8 analog input channels
that are independently software programmable for a
variety of ranges: ±10V, ±5V, 0V to +10V, or 0V to +5V.
This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V sys-
tem. In addition, the converter is overvoltage tolerant to
±16.5V; a fault condition on any channel does not
affect the conversion result of the selected channel.
Other features include a 5MHz bandwidth track/hold, a
100ksps throughput rate, software-selectable internal or
external clock and acquisition, 8+4 parallel interface,
and an internal 4.096V or an external reference.
A hardware SHDNpin and two programmable power-
down modes (STBYPD, FULLPD) are provided for low-
current shutdown between conversions. In STBYPD
mode, the reference buffer remains active, eliminating
start-up delays.
The MAX197 employs a standard microprocessor (µP)
interface. A three-state data I/O port is configured to
operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popular µPs. All logic inputs and outputs are
TTL/CMOS compatible.
The MAX197 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
For a different combination of ranges (±4V, ±2V, 0V to
4V, 0V to 2V), refer to the MAX199 data sheet. For 12-bit
bus interface, refer to the MAX196 and MAX198 data
sheets.
________________________ApplicationsIndustrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features12-Bit Resolution, 1/2LSB LinearitySingle +5V OperationSoftware-Selectable Input Ranges: ±10V, ±5V, 0V to 10V, 0V to 5VFault-Protected Input Multiplexer (±16.5V)8 Analog Input Channels6µs Conversion Time, 100ksps Sampling RateInternal or External Acquisition ControlInternal 4.096V or External ReferenceTwo Power-Down ModesInternal or External Clock
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus InterfaceDGND
VDD
REF
REFADJ
INT
CH7
AGND
CH6
CH5
CH4
CH3
CH2
CH1
CH0
D0/D8
D1/D9
D2/D10
D3/D11
SHDN
HBEN
CLK
DIP/SO/SSOP/Ceramic SBTOP VIEW
MAX197
__________________Pin Configuration19-0381; Rev 2; 9/01
PARTMAX197ACNI
MAX197BCNI
MAX197ACWI0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGEPIN-PACKAGE28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
______________Ordering InformationMAX197BCWI0°C to +70°C28 Wide SO
MAX197ACAI0°C to +70°C28 SSOP
MAX197BCAI0°C to +70°C28 SSOP
MAX197BC/D0°C to +70°CDice*
Ordering Information continued at end of data sheet.*Dice are specified at TA= +25°C, DC parameters only.
EVALUATION KIT
MANUAL AVAILABLE
Functional Diagram appears at end of data sheet.
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7µF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (VDD+ 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
CH0–CH7 to AGND..........................................................±16.5V
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C)......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX197_C_ _.......................................................0°C to +70°C
MAX197_E_ _.....................................................-40°C to +85°C
MAX197_M_ _..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX197A
Internal CLK mode/internal acquisition
control (Note 4)
External CLK mode/external acquisition
control
External CLK mode/external acquisition control
50kHz, VIN= ±5V (Note 3)
Bipolar
Unipolar
Up to the 5th harmonic
Bipolar
MAX197B
Unipolar
CONDITIONS<50
Aperture Jitter15Aperture Delay-86Channel-to-Channel Crosstalk80SFDRSpurious-Free Dynamic Range-85-78THDTotal Harmonic Distortion70
LSB±1/2INLIntegral Nonlinearity
Bits12Resolution
±0.5LSB±0.1Channel-to-Channel Offset
Error Matching
±10
LSB±1DNLDifferential Nonlinearity
LSB
Offset Error±5
UNITSMINTYPMAXSYMBOLPARAMETERMAX197A
MAX197B
MAX197A
MAX197B
Bipolar
Unipolar
Bipolar
Unipolarppm/°C3Gain Temperature Coefficient
(Note 2)
±10
MAX197A
MAX197B
MAX197A
MAX197B
LSB
Gain Error
(Note 2)
±10SINADSignal-to-Noise + Distortion Ratio
ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, ±10Vp-p, fSAMPLE= 100ksps)
MAX197A
MAX197B
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7µF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX, unless otherwise noted.)
fCLK= 2.0MHz= +25°C
(Note 5)
Unipolar
CONDITIONS30Output Short-Circuit Current
ppm/°C40REF Output Tempco4.0764.0964.116VREFREF Output Voltage40Input Capacitance 3Track/Hold Acquisition TimeV
Input Voltage Range
(See Table 1)
-3dB rolloff2.5
UNITSMINTYPMAXSYMBOLPARAMETERMHz
Small-Signal Bandwidth2.5
Bipolar
Unipolar
0V to 10V range
0V to 5V range
-10V to 10V range
-5V to 5V range
Bipolar
Input Current
Unipolar
360kΩ21Input Dynamic Resistance
Bipolar-55
0mA to 0.5mA output current (Note 6)mV7.5Load Regulation2.4652.5002.535REFADJ Output Voltage4.7Capacitive Bypass at REF
With recommended circuit (Figure 1)%±1.5REFADJ Adjustment Range
V/V1.6384Buffer Voltage Gain2.44.18Input Voltage Range
Input CurrentVREF= 4.18VVDD- 50mVREFADJ Threshold for
Buffer Disable
Normal or STANDBY power-down modekΩ10Input ResistanceFULL power-down mode5MΩ
ANALOG INPUT
INTERNAL REFERENCE
REFERENCE INPUT (Buffer disabled, reference input applied to REF pin)±10V range
±5V range
0V to 10V range
0V to 5V range
Normal or STANDBY
power-down mode
FULL power-down
mode
TC VREF
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7µF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX, unless otherwise noted.)
Internal acquisition3.05.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONSFull power-down mode (FULLPD) (Note 7)
3.0tACQI
Acquisition Time
LSB±1/2PSRRPower-Supply Rejection Ratio
(Note 8)
3.0tACQE
External CLKµs4.755.25VDDSupply Voltage
6.0tCONVConversion TimeInternal CLK, CCLK= 100pF6.07.710.0
To 0.1mV REF bypass
capacitor fully dischargedms8Reference Buffer Settling
Normal mode, bipolar ranges
Normal mode, unipolar ranges
UNITSMINTYPMAXSYMBOLPARAMETERStandby power-down (STBYPD)18
IDDSupply Current610
Internal reference±1/2
CCLK= 100pFMHz1.251.562.00fCLKInternal Clock Frequency
0.12.0fCLKExternal Clock Frequency RangeMHz
External CLK
Internal CLK
Power-up (Note 10)µs200Bandgap Reference
Start-Up Time
External CLKksps100Throughput RateInternal CLK, CCLK= 100pF62
CREF= 4.7µF
CREF= 33µF2.4VINHInput High Voltage0.8VINLInput Low Voltage
VIN= 0V or VDDµA±10IINInput Leakage Current
(Note 5)pF15CINInput Capacitance
VDD= 4.75V, ISINK= 1.6mAV0.4VOLOutput Low Voltage
VDD= 4.75V, ISOURCE= 1mAVVDD- 1VOHOutput High Voltage
(Note 5)pF15COUTThree-State Output Capacitance
POWER REQUIREMENTS
TIMING
DIGITAL INPUTS(D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
DIGITAL OUTPUTS(D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
Note 1:Accuracy specifications tested at VDD= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V input range.
Note 2:External reference: VREF= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3:Ground "on" channel; sine wave applied to all "off" channels.
Note 4:Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5:Guaranteed by design. Not tested.
Note 6:Use static loads only.
Note 7:Tested using internal reference.
Note 8:PSRR measured at full-scale.
Note 9:External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WRwith ACQMOD
= high control byte.
Note 10:Not subject to production testing. Provided for design guidance only.
Note 11:All input control signals specified with tR= tF= 5ns from a voltage level of 0.8V to 2.4V.
Note 12:tDOand tDO1are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13:tTRis defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7µF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX, unless otherwise noted.)
(Note 13)ns70
CONDITIONStTRRDHigh to Output Disable120tINT1RDLow to INTHigh Delay80tCSCSPulse Width
UNITSMINTYPMAXSYMBOLPARAMETER80tWRWR Pulse Width0tCSWS0tCSWHCSto WR Hold Timeto WRSetup Time0tCSRS0tCSRHCSto RDHold Timeto RDSetup Time100tCWS50tCWHCLK to WRHold Time
CLK to WRSetup Time60tDS0tDHData Valid to WRHold
Data Valid to WRSetup
Figure 2, CL= 100pF (Note 12)
Figure 2, CL= 100pF (Note 12)120tDO120tDO1HBENHighor HBENLowto
Output ValidLow to Output Data Valid
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
__________________________________________Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX197-1
DIGITAL CODE
INTEGRAL NONLINEARITY (LSB)
FFT PLOT
FREQUENCY (kHz)
AMPLITUDE (dB)-80
fTONE = 10kHz
fSAMPLE = 100kHz
MAX197-2
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX197-3
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
FSAMPLE = 100kHz
TEMPERATURE (°C)
REF
(V)
REFERENCE OUTPUT VOLTAGE (VREF)
vs. TEMPERATURE
MAX197-4
REFADJ
AV = 1.6384
REF+2.5V
INTERNAL
REFERENCE
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE
MAX197-7
MAX197-5
TEMPERATURE (°C)
PSRR (LSB)
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
100Hz
120Hz
VDD = 5V ±0.25V
MAX197-6
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING (LSB)
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________Pin DescriptionDigital GroundDGND28
+5V Supply. Bypass with 0.1µF capacitor to AGND.VDD27
INTgoes low when conversion is complete and output data is ready.INT24
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND. Connect
to VDDwhen using an external reference at the REFpin.REFADJ25
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF26
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).D2/D1012
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).D1/D913
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.D0/D814
Analog GroundAGND15
Analog Input ChannelsCH0–CH716–23
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.HBEN5
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.SHDN6
Three-State Digital I/OD7–D47–10
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).D3/D1111
If CSis low, a falling edge on RDwill enable a read operation on the data bus.RD4
When CSis low, in the internal acquisition mode, a rising edge on WRlatches in configuration data and starts an
acquisition plus a conversion cycle. When CSis low, in the external acquisition mode, the first rising edge onstarts an acquisition and a second rising edge on WRends acquisition and starts a conversion cycle.3
PINChip Select, active low.CS2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor from this pin to ground to set the internal clock frequency; fCLK= 1.56MHz typical with
CCLK= 100pF.
CLK1
FUNCTIONNAME100kΩ
510kΩ
24kΩ
REFADJ
+5V
0.01μF
MAX197
Figure 1. Reference-Adjust Circuit
3kΩ
3kΩ
DOUT
DOUT
+5V
a. HIGH-Z TO VOH AND VOL TO VOHb. HIGH-Z TO VOL AND VOH TO VOL
CLOADCLOAD
Figure 2. Load Circuits for Enable Time
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________Detailed Description
Converter OperationThe MAX197, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easy
interface to microprocessors (µPs). Figure 3 shows the
MAX197 in its simplest operational configuration.
Analog-Input Track/HoldIn the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. A low
impedance input source, which settles in less than
1.5µs, is required to maintain conversion accuracy at
the maximum conversion rate.
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WRrising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the External Acquisition
section.
Input BandwidthThe ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and ProtectionFigure 4 shows the equivalent input circuit. With VREF=
4.096V, the MAX197 can be programmed for input
ranges of ±10V, ±5V, 0V to 10V, or 0V to 5V by setting the
appropriate control bits (D3, D4) in the control byte (see
Tables 2 and 3). The full-scale input voltage depends on
the voltage at REF (Table 1). When an external reference
is applied at REFADJ, the voltage at REF is given by VREF
= 1.6384 x VREFADJ(2.4V < VREF< 4.18V).
DGND
VDD
REF
REFADJ
INT
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
AGND
4.7μF0.1μF
+5V
+4.096V
OUTPUT STATUS
CONTROL
INPUTS
CLK
HBEN
SHDN
D3/D11
D2/D10
D1/D9
D0/D8
100pF
μP DATA BUS
ANALOG
INPUTS
MAX197
Figure 3. Operational Diagram
5.12kΩ
8.67kΩ
12.5kΩ
CH_
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
CHOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
Figure 4. Equivalent Input Circuit
RANGE (V)ZERO SCALE (V)-FULL SCALE+FULL SCALE0 to 50—VREFx 1.2207
0 to 100—VREFx 2.4414—-VREFx 1.2207VREFx 1.2207
±10—-VREFx 2.4414VREFx 2.4414
Table 1. Full Scale and Zero Scale
