MAX19713ETN+ ,10-Bit, 45Msps, Full-Duplex, Analog Front-EndApplicationsV 51 20 AD7DDQDN 52 19 AD6● WiMAX CPEs ● Portable Communication QDP 53 18 AD5● 801.11a/ ..
MAX1971EEE ,Dual / 180 Out-of-Phase / 1.4MHz / 750mA Step- Down Regulator with POR and RSI/PFOELECTRICAL CHARACTERISTICS(V = V = V = 5V, R = 100kΩ to IN, R = 100kΩ to IN, V = 0, C = 0.1µF, FBSE ..
MAX1971EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOMAX1970/MAX1971/MAX197219-2297; Rev 1; 2/09Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulat ..
MAX1972EEE ,Dual / 180 Out-of-Phase / 1.4MHz / 750mA Step- Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current- Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX1972EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current-♦ Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX1973EUB ,PLASTIC ENCAPSULATED DEVICESTable of Contents I. ........Device Description V. ........Quality Assurance Information II ..
MAX494CSD+ ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsGeneral Description ________
MAX494CSD+T ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsApplications *Dice are specified at TA = +25°C, DC parameters only.__________Typical Operating Circ ..
MAX494CSD-T ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsApplications *Dice are specified at TA = +25°C, DC parameters only.__________Typical Operating Circ ..
MAX494EPD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsMAX492/MAX494/MAX49519-0265; Rev 2; 9/96Single/Dual/Quad, Micropower,Single-Supply Rail-to-Rail Op ..
MAX494ESD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsFeatures' Low-Voltage Single-Supply Operation (+2.7V to +6V)The dual MAX492, quad MAX494, and singl ..
MAX494ESD+ ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op Amps Not Recommended for New Designs The MAX495 was manufactured for Maxim by an outside wafer foundr ..
MAX19713ETN+
10-Bit, 45Msps, Full-Duplex, Analog Front-End
General DescriptionThe MAX19713 is an ultra-low-power, highly integrated
mixed-signal analog front-end (AFE) ideal for wideband
communication applications operating in full-duplex (FD)
mode. Optimized for high dynamic performance and ultra-
low power, the device integrates a dual 10-bit, 45Msps
receive (Rx) ADC; dual 10-bit, 45Msps transmit (Tx) DAC;
three fast-settling 12-bit aux-DAC channels for ancillary
RF front-end control; and a 10-bit, 333ksps housekeep-
ing aux-ADC. The typical operating power in FD mode is
91.8mW at a 45MHz clock frequency.
The Rx ADCs feature 54dB SINAD and 72.2dBc SFDR at
5.5MHz input frequency with a 45MHz clock frequency.
The analog I/Q input amplifiers are fully differential and
accept 1.024VP-P full-scale signals. Typical I/Q channel
matching is ±0.03 phase and ±0.02dB gain.
The Tx DACs feature 70.3dBc SFDR at fOUT = 2.2MHz
and fCLK = 45MHz. The analog I/Q full-scale output volt-
age range is ±400mV differential. The output DC com-
mon-mode voltage is selectable from 0.71V to 1.06V. The
I/Q channel offset is adjustable to optimize radio lineup
sideband/carrier suppression. Typical I/Q channel match-
ing is ±0.01dB gain and ±0.05° phase.
Two independent 10-bit parallel, high-speed digital buses
used by the Rx ADC and Tx DAC allow full-duplex opera-
tion for frequency-division duplex applications. The Rx
ADC and Tx DAC can be disabled independently to opti-
mize power management. A 3-wire serial interface con-
trols power-management modes, the aux-DAC channels,
and the aux-ADC channels.
The MAX19713 operates on a single 2.7V to 3.3V analog
supply and 1.8V to 3.3V digital I/O supply. The MAX19713
is specified for the extended (-40°C to +85°C) tempera-
ture range and is available in a 56-pin, TQFN package.
The Selector Guide at the end of the data sheet lists other
pin-compatible versions in this AFE family. For time-divi-
sion duplex (TDD) applications, refer to the MAX19705–
MAX19708 AFE family of products.
Applications●WiMAX CPEs●801.11a/b/g WLAN●VoIP Terminals●Portable Communication
Equipment
Features●Dual 10-Bit, 45Msps Rx ADC and Dual 10-Bit,
45Msps Tx DAC●Ultra-Low Power 91.8mW at fCLK = 45MHz, FD Mode 79.2mW at fCLK = 45MHz, Slow Rx Mode 49.5mW at fCLK = 45MHz, Slow Tx Mode Low-Current Standby and Shutdown Modes●Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim●Excellent Dynamic Performance SNR = 54.1dB at fIN = 5.5MHz (Rx ADC) SFDR = 70.3dBc at fOUT = 2.2MHz (Tx DAC)●Three 12-Bit, 1μs Aux-DACs●10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data Averaging●Excellent Gain/Phase Match ±0.03° Phase, ±0.02dB Gain (Rx ADC) at
fIN = 5.5MHz●Multiplexed Parallel Digital I/O●Serial-Interface Control●Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable●Miniature 56-Pin TQFN Package
(7mm x 7mm x 0.8mm)
Functional Diagram and Functional Diagram appear at end
of data sheet.*All devices are specified over the -40°C to +85°C operating range.
**EP = Exposed paddle. +Denotes lead-free package.
PART*PIN-PACKAGEPKG CODEMAX19713ETN56 TQFN-EP** T5677-1
MAX19713ETN+56 TQFN-EP** T5677-1
TOP VIEW
MAX19713
TQFNAD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
OGND
OVDD
DA0
DA1
DA2
DA3
REFN
COM
REFIN
QDP
QDN
VDD
GND
IDP
IDN
VDD
DAC1
DAC2
DAC3
ADC123456789101112131441403938373635343332313029
GND
AD0AD1V
QAPQAN
GND
CLK
GND
IANIAP
REFP
DA6DA5DA4DA7DA8DA9DOUTDINSCLKV
GNDV
ADC2
EXPOSED PADDLE (GND)
CS/WAKE
NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.
MAX1971310-Bit, 45Msps, Full-Duplex
Analog Front-End
Pin Coniguration
Ordering Information
EVALUATION KIT AVAILABLE
VDD to GND, OVDD to OGND .............................-0.3V to +3.6V
GND to OGND ......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND ...................-0.3V to VDD
ADC1, ADC2 to GND ...............................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND ........-0.3V to (VDD + 0.3V)
AD0–AD9, DA0–DA9, SCLK, DIN, CS/WAKE,
CLK, DOUT to OGND .......................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
56-Pin TQFN-EP (derate 27.8mW/°C above +70°C) ........2.22WThermal Resistance θJA ..................................................36°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33μF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
VDD Supply Current
FD mode: fCLK = 45MHz, fOUT = 2.2MHz
on both DAC channels;
fIN = 5.5MHz on both ADC channels; aux-
DACs ON and at midscale, aux-ADC ON
SPI2-Tx mode: fCLK = 45MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
OFF; aux-DACs ON and at midscale,
aux-ADC ON
SPI1-Rx mode: fCLK = 45MHz, fIN =
5.5MHz on both ADC channels; Tx DAC
OFF (Tx DAC outputs at 0V); aux-DACs
ON and at midscale, aux-ADC ON
SPI4-Tx mode: fCLK = 45MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
ON (output three-stated); aux-DACs ON
and at midscale, aux-ADC ON
SPI3-Rx mode: fCLK = 45MHz, fIN =
5.5MHz on both channels; Tx DAC ON
(Tx DAC outputs at midscale); aux-DACs
ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
MAX1971310-Bit, 45Msps, Full-Duplex
Analog Front-End
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33μF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVDD Supply Current
Idle mode: fCLK = 45MHz; aux-DACs ON
and at midscale, aux-ADC ON 12.415mA
Shutdown mode: CLK = 0 or OVDD, aux-
ADC OFF0.55µA
OVDD Supply Current
FD mode: fCLK = 45MHz, fOUT = 2.2MHz
on both DAC channels; fIN = 5.5MHz on
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
4.6SPI1-Rx and SPI3-Rx modes: fCLK
= 45MHz, fIN = 5.5MHz on both ADC
channels; DAC input bus three-stated;
aux-DACs ON and at midscale, aux-ADC
SPI2-Tx and SPI4-Tx modes: fCLK =
45MHz, fOUT = 2.2MHz on both DAC
channels; ADC output bus three-stated;
aux-DACs ON and at midscale, aux-ADC
310Standby mode: CLK = 0 or OVDD; aux-
DACs ON and at midscale, aux-ADC ON0.1
Idle mode: fCLK = 45MHz; aux-DACs ON
and at midscale, aux-ADC ON73
Shutdown mode: CLK = 0 or OVDD,
aux-ADC OFF0.1
Rx ADC DC ACCURACYResolution10Bits
Integral Nonlinearity INL±1.25 LSB
Differential NonlinearityDNL±0.65LSB
Offset Error Residual DC offset error-5±0.2+5%FS
Gain Error Includes reference error-5±0.7+5%FS
DC Gain Matching -0.15±0.04+0.15dB
Offset Matching±10LSB
Gain Temperature Coeficient±30ppm/°C
Power-Supply RejectionOffset (VDD ±5%)±0.2LSBGain (VDD ±5%)±0.07
Rx ADC ANALOG INPUTInput Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD/2V
Input ImpedanceRINSwitched capacitor load 120kΩ
CIN5pF
MAX1971310-Bit, 45Msps, Full-Duplex
Analog Front-End
Electrical Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33μF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC CONVERSION RATEMaximum Clock FrequencyfCLK(Note 2)45MHz
Data LatencyChannel IA5Clock
CyclesChannel QA5.5
Rx ADC DYNAMIC CHARACTERISTICS (Note 3)Signal-to-Noise RatioSNRfIN = 5.5MHz52.754.5dBfIN = 19.4MHz54
Signal-to-Noise and DistortionSINADfIN = 5.5MHz52.454.3dBfIN = 19.4MHz53.9
Spurious-Free Dynamic RangeSFDRfIN = 5.5MHz6372.1dBcfIN = 19.4MHz76.3
Total Harmonic Distortion THDfIN = 5.5MHz-69.4-61dBcfIN = 19.4MHz-71.3
Third-Harmonic DistortionHD3fIN = 5.5MHz-73.7dBcfIN = 19.4MHz-76.3
Intermodulation DistortionIMDfIN1 = 1.8MHz, AIN1 = -7dBFS,
fIN2 = 1.0MHz, AIN2 = -7dBFS-69dBc
Third-Order Intermodulation
DistortionIM3fIN1 = 1.8MHz, AIN1 = -7dBFS,
fIN2 = 1.0MHz, AIN2 = -7dBFS-72dBc
Aperture Delay 3.5ns
Aperture Jitter2psRMS
Overdrive Recovery Time1.5x full-scale input2ns
Rx ADC INTERCHANNEL CHARACTERISTICSCrosstalk Rejection
fINX,Y = 5.5MHz, AINX,Y = -0.5dBFS,
fINY,X = 1.8MHz, AINY,X = -0.5Dbfs
(Note 4)
-88dB
Amplitude MatchingfIN = 5.5MHz, AIN = -0.5dBFS (Note 5)±0.02dB
Phase MatchingfIN = 5.5MHz, AIN = -0.5dBFS (Note 5)±0.03Degrees
Tx DAC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.35LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 6)-0.7±0.2+0.7LSB
Residual DC OffsetVOS-4±0.1+4mV
Full-Scale Gain Error-40+40mV
MAX1971310-Bit, 45Msps, Full-Duplex
Analog Front-End
Electrical Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33μF, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx DAC DYNAMIC PERFORMANCEDAC Conversion RatefCLK(Note 2) 45MHz
In-Band Noise DensityNDfOUT = 2.2MHz-129dBFS/Hz
Third-Order Intermodulation
DistortionIM3fOUT1 = 2MHz, fOUT2 = 2.2MHz-82dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfOUT = 2.2MHz61.570.3dBc
Total Harmonic Distortion to
NyquistTHDfOUT = 2.2MHz-68.1-60.5dBc
Signal-to-Noise Ratio to NyquistSNRfOUT = 2.2MHz56.1dB
Tx DAC INTERCHANNEL CHARACTERISTICSI-to-Q Output IsolationfOUTX,Y = 500kHz, fOUTY,X = 620kHz85dB
Gain Mismatch Between I and Q
ChannelsMeasured at DC-0.4±0.01+0.4dB
Phase Mismatch Between I and Q
ChannelsfOUT = 2.2MHz±0.05Degrees
Differential Output Impedance 800Ω
Tx DAC ANALOG OUTPUTFull-Scale Output Voltage VFS±400mV
Output Common-Mode Voltage VCOMD
Bits CM1 = 0, CM0 = 0 (default)1.011.061.11Bits CM1 = 0, CM0 = 10.880.941.00
Bits CM1 = 1, CM0 = 00.750.820.90
Bits CM1 = 1, CM0 = 10.620.710.81
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICSReceive Transmit IsolationADC: fINI = fINQ = 5.5MHz,
DAC: fOUTI = fOUTQ = 2.2MHz85dB
AUXILIARY ADCs (ADC1, ADC2)ResolutionN10Bits
Full-Scale ReferenceVREFAD1 = 0 (default)2.048VAD1 = 1VDD
Analog Input Range0 to
VREFV
Analog Input ImpedanceMeasured at DC500kΩ
Input-Leakage CurrentMeasured at unselected input from 0 to
VREF±0.1µA
Gain ErrorGEIncludes reference error, AD1 = 0-5+5%FS
Zero-Code ErrorZE±2mV
Differential NonlinearityDNL±0.6LSB
MAX1971310-Bit, 45Msps, Full-Duplex
Analog Front-End
Electrical Characteristics (continued)
