MAX19708ETM+T ,10-bit, 11Msps, Ultra-Low-Power Analog Front-EndFeatures♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,The MAX19708 is an ultra-low-power, mixed-sign ..
MAX1970EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOApplicationsPART TEMP RANGE PIN-PACKAGExDSL Modems USB-Powered DevicesMAX1970EEE -40°C to +85°C 16 ..
MAX1970EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOELECTRICAL CHARACTERISTICS(V = V = V = 5V, R = 100kΩ to IN, R = 100kΩ to IN, V = 0, C = 0.1µF, FBSE ..
MAX1970EEE+T ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOFeaturesThe MAX1970/MAX1971/MAX1972 dual-output current-♦ Current-Mode, 1.4MHz Fixed-Frequency PWMm ..
MAX19710ETN+T ,10-Bit, 7.5Msps, Full-Duplex, Analog Front-Endapplications operating in full-duplex (FD)♦ Ultra-Low Powermode. Optimized for high dynamic perform ..
MAX19712 ,10-Bit, 22Msps, Full-Duplex, Analog Front-Endapplications operating in full-duplex ♦ Ultra-Low Power50.4mW at f = 22MHz, FD Mode(FD) mode. Optim ..
MAX4945AELA+ ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4945LELA+T ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4946ELA+ ,Overvoltage-Protection Controllers with Internal FETELECTRICAL CHARACTERISTICS(V = +5V (MAX4943/MAX4944_/MAX4945_/MAX4949), V = +3V (MAX4946), T = -40° ..
MAX4947ETG+ ,Hex SPDT Data SwitchApplications♦ Wide Supply Capability1.8V to 5.5V Supply Voltage RangeUSB Signal Switching Cell Phon ..
MAX494CSD ,Single/Dual/Quad, Micropower, Single-Supply Rail-to-Rail Op AmpsGeneral Description ________
MAX494CSD+ ,Single/Dual/Quad, Micropower, Single-Supply, Rail-to-Rail Op AmpsGeneral Description ________
MAX19708ETM+T
10-bit, 11Msps, Ultra-Low-Power Analog Front-End
General DescriptionThe MAX19708 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for TD-SCDMA handsets
and data cards. Optimized for high dynamic perfor-
mance at ultra-low power, the device integrates a dual
10-bit, 11Msps receive (Rx) ADC; dual 10-bit, 11Msps
transmit (Tx) DAC with TD-SCDMAbaseband filters;
three fast-settling 12-bit aux-DAC channels for ancillary
RF front-end control; and a 10-bit, 333ksps housekeep-
ing aux-ADC. The typical operating power in Tx-Rx
FAST mode is 36.9mW at a 5.12MHz clock frequency.
The Rx ADCs feature 55dB SNR and 77.4dBc SFDR at a
1.87MHz input frequency with an 11MHz clock frequen-
cy. The analog I/Q input amplifiers are fully differential
and accept 1.024VP-Pfull-scale signals. Typical I/Q
channel matching is ±0.08°phase and ±0.02dB gain.
The Tx DACs with TD-SCDMA lowpass filters feature -3dB
cutoff frequency of 1.32MHz and > 55dB stopband rejec-
tion at fIMAGE= 4.32MHz. The analog I-Q full-scale output
voltage range is selectable at ±410mV or ±500mV differ-
ential. The output DC common-mode voltage is selec-
table from 0.9V to 1.4V. The I/Q channel offset is
adjustable to optimize radio lineup sideband/carrier sup-
pression. Typical I-Q channel matching is ±0.02dB gain
and ±0.04°phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADCchannels.
The MAX19708 operates on a single +2.7V to +3.3V
analog supply and +1.8V to +3.3V digital I/O supply.
The MAX19708 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The Selector Guideat the end of the
data sheet lists other pin-compatible versions in this
AFE family.
ApplicationsTD-SCDMA Handsets
TD-SCDMA Data Cards
Portable Communication Equipment
FeaturesDual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,
11Msps Tx DACUltra-Low Power
36.9mW at fCLK= 5.12MHz, Fast Mode
19.8mW at fCLK= 5.12MHz, Slow Mode
Low-Current Standby and Shutdown ModesIntegrated TD-SCDMAFilters with > 55dB
Stopband RejectionProgrammable Tx DAC Common-Mode DC Level
and I/Q Offset TrimExcellent Dynamic Performance
SNR = 55dB at fIN= 1.87MHz (Rx ADC)
SFDR = 73dBc at fOUT= 620kHz (Tx DAC)Three 12-Bit, 1µs Aux-DACs10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data AveragingExcellent Gain/Phase Match
±0.08°Phase, ±0.02dB Gain (Rx ADC) at
fIN= 1.87MHzMultiplexed Parallel Digital I/OSerial-Interface ControlVersatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx DisableMiniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End19-3764; Rev 0; 8/05
EVALUATION KIT
AVAILABLE
Ordering Information
PART*PIN-PACKAGEPKG CODEMAX19708ETM48 Thin QFN-EP**T4877-4
MAX19708ETM+48 Thin QFN-EP**T4877-4
*All devices are specified over the -40°C to +85°C operating range.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram and Selector Guide appear at end of
data sheet.OVDD
OGNDVDD
IDN
IDP
GND
VDD
QDN
QDP
REFN
EXPOSED PADDLE (GND)REFIN
DAC1
COM
DAC237345678910
ADC1ADC2V
GNDVSCLKDINT/RSHDNDOUTDAC3
THIN QFNMAX19708
TOP VIEW
REFP
IAPIAN
GND
CLK
GND
QANQAP
GND123534333231302928272625
Pin Configuration
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND, OVDDto OGND..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND...........-0.3V to (VDD + 0.3V)
D0–D9, DOUT, T/R, SHDN, SCLK, DIN, CS,
CLK to OGND.....................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 27.8mW/°C above +70°C).....2.22W
Thermal Resistance θJA..................................................36°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
fCLK = 5.12MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
fCLK = 5.12MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
fCLK = 5.12MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
fCLK = 5.12MHz, fIN = 1.87MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
VDD Supply Current
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
fCLK = 11MHz, fOUT = 620kHz on both
channels, aux-DACs ON and at midscale,
aux-ADC ON
14.116
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSExt1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
fCLK = 11MHz, fOUT = 620kHz on both
channels, aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
fCLK = 11MHz, fIN = 1.87MHz on both
channels, aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
fCLK = 11MHz, fIN = 1.87MHz on both
channels, aux-DACs ON and at midscale,
aux-ADC ON
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 11MHz; aux-DACs ON
and at midscale, aux-ADC ON5.57VDD Supply Current
Shutdown mode: CLK = 0 or OVDD0.52µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): fCLK = 11MHz,
fIN = 1.87MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
1.5mA
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx): fCLK = 11MHz, fOUT
= 620kHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OVDD; aux-
DACs ON and at midscale, aux-ADC ON1
Idle mode: fCLK = 11MHz; aux-DACs ON
and at midscale, aux-ADC ON19
OVDD Supply Current
Shutdown mode: CLK = 0 or OVDD0.1
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.9LSB
Differential NonlinearityDNLGuar anteed no m i ssi ng cod e ( N ote 2) -1.0±0.4+1.2LSB
Offset ErrorResidual DC offset error-5±0.1+5%FS
Gain ErrorInclude reference error-7.0±1.5+10.5%FS
DC Gain Matching-0.25±0.01+0.25dB
Offset Matching±10LSB
Gain Temperature Coefficient±18.4ppm/°C
Offset error (VDD ±5%)±2LSBPower-Supply RejectionPSRRGain error (VDD ±5%)±0.07%FS
Rx ADC ANALOG INPUTInput Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD / 2V
RINSwitched capacitor load491kΩInput ImpedanceCIN5pF
Rx ADC CONVERSION RATEMaximum Clock FrequencyfCLK(Note 3)11MHz
Channel I5Data Latency (Figure 3)Channel Q5.5
Clock
Cycles
Rx ADC DYNAMIC CHARACTERISTICS (Note 4)fIN = 1.875MHz, fCLK = 11MHz53.355Signal-to-Noise RatioSNRfIN = 3.5MHz, fCLK = 11MHz55dB
fIN = 1.875MHz, fCLK = 11MHz53.254.9Signal-to-Noise and DistortionSINADfIN = 3.5MHz, fCLK = 11MHz54.9dB
fIN = 1.875MHz, fCLK = 11MHz63.577.4Spurious-Free Dynamic RangeSFDRfIN = 3.5MHz, fCLK = 11MHz78.3dBc
fIN = 1.875MHz, fCLK = 11MHz-84.3Third-Harmonic DistortionHD3fIN = 3.5MHz, fCLK = 11MHz-85dBc
Intermodulation DistortionIMDf1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-72.7dBc
Third-Order Intermodulation
DistortionIM3f1 = 1.8MHz, -7dBFS;
f2 = 1MHz, -7dBFS-74.4dBc
fIN = 1.875MHz, fCLK = 11MHz-75.6-63Total Harmonic DistortionTHDfIN = 3.5MHz, fCLK = 11MHz-76.3dB
Aperture Delay3.5ns
Overdrive Recovery Time1.5x full-scale input2ns
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC INTERCHANNEL CHARACTERISTICSCrosstalk RejectionfIN X ,Y = 1.875M H z at - 0.5d BFS , fIN X ,Y =
1M H z at - 0.5d BFS ( N ote 5) -90dB
Amplitude MatchingfIN = 1.875MHz at -0.5dBFS (Note 6)±0.02dB
Phase MatchingfIN = 1.875MHz at -0.5dBFS (Note 6)±0.08D eg r ees
Tx DAC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.45LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 2)-1±0.4+1LSB
TA > +25°C-4±1+4
Residual DC OffsetVOS
TA < +25°C-5.5±1+5.5
Full-Scale Gain ErrorIncl ud e r efer ence er r or ( p eak- to- p eak er r or ) -50+50mV
Tx PATH DYNAMIC PERFORMANCECorner Frequency3dB corner1.051.321.65MHz
Passband RippleDC to 640kHz (Note 2)0.150.5dBP-P
Group Delay Variation in PassbandDC to 640kHz50ns
Error-Vector MagnitudeEVMDC to 700kHz2%
Stopband RejectionfIMAGE = 4.32MHz, fOUT = 800kHz, fCLK =
5.12MHz5562.5dBc
2MHz21.5
4MHz49
5MHz58
10MHz90
Baseband AttenuationSpot relative to
100kHz
20MHz90
DAC Conversion RatefCLK(Note 3)11MHz
In-Band Noise DensityNDfOUT = 620kHz, fCLK = 5.12MHz,
offset = 500kHz-120.6dBc/Hz
Third-Order Intermodulation
DistortionIM3f1 = 620kHz, f2 = 640kHz82dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 11MHz, fOUT = 620kHz6073dBc
Total Harmonic Distortion to
NyquistTHDfCLK = 11MHz, fOUT = 620kHz-71-60dB
Signal-to-Noise Ratio to NyquistSNRfCLK = 11MHz, fOUT = 620kHz56.5dB
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx PATH INTERCHANNEL CHARACTERISTICSI-to-Q Output IsolationfOUTX,Y = 500kHz, fOUTX,Y = 620kHz90dB
Gain Mismatch Between DAC
OutputsMeasured at DC-0.30±0.02+0.31dB
Phase Mismatch Between DAC
OutputsfOUT = 620kHz, fCLK = 11MHz±0.04D eg r ees
Differential Output Impedance800Ω
Tx PATH ANALOG OUTPUTBit E7 = 0 (default)±410Full-Scale Output Voltage (Table 8)VFSBit E7 = 1±500mV
Bits CM1 = 0, CM0 = 0 (default)1.271.41.48
Bits CM1 = 0, CM0 = 11.25
Bits CM1 = 1, CM0 = 01.1
Output Common-Mode Voltage
(Table 11)VCOM
Bits CM1 = 1, CM0 = 10.9
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICSReceive Transmit IsolationADC fINI = fINQ = 1.875MHz, DAC fOUTI =
fOUTQ = 620kHz, fCLK = 11MHz90dB
AUXILIARY ADC (ADC1, ADC2)ResolutionN10Bits
AD1 = 0 (default)2.048Full-Scale ReferenceVREFAD1 = 1VDDV
Analog Input Range0 to
VREFV
Analog Input ImpedanceAt DC500kΩ
Input-Leakage CurrentMeasured at unselected input from 0 to
VREF±0.1µA
Gain ErrorGEIncludes reference error-5+5%FS
Zero-Code ErrorZE2mV
Differential NonlinearityDNL±0.53LSB
Integral NonlinearityINL±0.45LSB
Supply Current210µA
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
AUXILIARY DACs (DAC1, DAC2, DAC3)ResolutionN12Bits
Integral NonlinearityINL±1.25LSB
Differential NonlinearityDNLGuaranteed monotonic over codes 100 to
4000 (Note 2)-1.0±0.65+1.2LSB
Gain ErrorGERL > 200kΩ±0.7%FS
Zero-Code ErrorZE±0.6%FS
Output-Voltage LowVOLRL > 200kΩ0.1V
Output-Voltage HighVOHRL > 200kΩ2.56V
DC Output ImpedanceDC output at midscale4Ω
Settling TimeFrom 1/4 FS to 3/4 FS, within ±10 LSB 1µs
Glitch ImpulseFrom 0 to FS transition24nV•s
Rx ADC-Tx DAC TIMING CHARACTERISTICSCLK Rise to Channel-I Output Data
ValidtDOIFigure 3 (Note 2)5.37.08.5ns
CLK Fall to Channel-Q Output
Data ValidtDOQFigure 3 (Note 2)6.89.111.3ns
I-DAC DATA to CLK Fall Setup
TimetDSIFigure 6 (Note 2)10ns
Q-DAC DATA to CLK Rise Setup
TimetDSQFigure 6 (Note 2)10ns
CLK Fall to I-DAC Data Hold TimetDHIFigure 6 (Note 2)0ns
CLK Rise to Q-DAC Data Hold
TimetDHQFigure 6 (Note 2)0ns
CLK Duty Cycle50%
CLK Duty-Cycle Variation±15%
Digital Output Rise/Fall Time20% to 80%2.5ns
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 7, Note 2)Falling Edge of CS to Rising Edge
of First SCLK TimetCSS10ns
DIN to SCLK Setup TimetDS10ns
DIN to SCLK Hold TimetDH0ns
SCLK Pulse-Width HightCH25ns
SCLK Pulse-Width LowtCL25ns
SCLK PeriodtCP50ns
SCLK to CS Setup TimetCS10ns
CS High Pulse WidthtCSW80ns
CS High to DOUT Active HightCSDBit AD0 set200ns
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCS High to DOUT Low (Aux-ADC
Conversion Time)tCONV
Bit AD0 set, no averaging (see Table 15),
fCLK = 11MHz,
CLK divider = 4 (see Table 16)
4.36µs
DOUT Low to CS Setup TimetDCSBit AD0, AD10 set200ns
SCLK Low to DOUT Data OuttCDBit AD0, AD10 set14.5ns
CS High to DOUT High ImpedancetCHZBit AD0, AD10 set200ns
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8)From shutdown to Rx mode, ADC settles
to within 1dB SINAD82.2
Shutdown Wake-Up TimetWAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error29
Fr om i d l e to Rx m od e w i th C LK p r esentur i ng i d l e, AD C settl es to w i thi n 1d B S IN AD 9.6
Idle Wake-Up Time (With CLK)tWAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error7.6
From standby to Rx mode, ADC settles to
within 1dB SINAD17.5
Standby Wake-Up TimetWAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error24
Enable Time from Tx to Rx (Ext2-Tx
to Ext2-Rx, Ext4-Tx to Ext4-Rx, and
SPI4-Tx to SPI3-Rx States)
tENABLE, RXADC settles to within 1dB SINAD500nsnab l e Ti m e fr om Rx to Tx ( E xt1- Rx
to E xt1- Tx, E xt4- Rx to E xt4- Tx, and P I3- Rx to S P I4- Tx S tates)
tENABLE, TXDAC settles to within 10 LSB error500ns
Enable Time from Tx to Rx (Ext1-Tx
to Ext1-Rx, Ext3-Tx to Ext3-Rx, and
SPI1-Tx to SPI1-Rx States)
tENABLE, RXADC settles to within 1dB SINAD8.1µsnab l e Ti m e fr om Rx to Tx ( E xt2- Rx
to E xt2- Tx, E xt3- Rx to E xt3- Tx, and P I1- Rx to S P I2- Tx S tates)
tENABLE,TXDAC settles to within 10 LSB error7.0µs
INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally)Positive ReferenceVREFP - VCOM0.256V
Negative ReferenceVREFN - VCOM-0.256V
Common-Mode Output VoltageVCOMVDD / 2
- 0.15VDD / 2VDD / 2
+ 0.15V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMaximum REFP/REFN/COM
Sink CurrentISINK2mA
Differential Reference OutputVREFVREFP - VREFN+0.460+0.512+0.548V
Differential Reference Temperature
CoefficientREFTC±18ppm/°C
BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally)Reference Input VoltageVREFIN1.024V
Differential Reference OutputVDIFFVREFP - VREFN0.512V
Common-Mode Output VoltageVCOMVDD / 2V
Maximum REFP/REFN/COM
Source CurrentISOURCE2mA
Maximum REFP/REFN/COM
Sink CurrentISINK2mA
REFIN Input Current-0.7µA
REFIN Input Resistance500kΩ
DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN)Input High ThresholdVINH0.7 x OVDDV
Input Low ThresholdVINL0.3 x OVDDV
Input LeakageDIIND0–D9, CLK, SCLK, DIN, CS, T/R,
SHDN = OGND or OVDD-1+1µA
Input CapacitanceDCIN5pF
DIGITAL OUTPUTS (D0–D9, DOUT)Output-Voltage LowVOLISINK = 200µA0.2 x OVDDV
Output-Voltage HighVOHISOURCE = 200µA0.8 x OVDDV
Tri-State Leakage CurrentILEAK-1+1µA
Tri-State Output CapacitanceCOUT5pF
Note 1:Specifications from TA= +25°C to +85°C are guaranteed by production tests. Specifications from TA= +25°C to -40°C are
guaranteed by design and characterization.
Note 2:Guaranteed by design and characterization.
Note 3:The minimum clock frequency (fCLK) for the MAX19708 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequen-
cy (ACLK) is determined by fCLKand the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz /
128 = 11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI. The maximum
conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 1.5MHz = 1024µs.
Note 4:SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 5:Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second
channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel
FFT test tone.
Note 6:Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Rx ADC CHANNEL-IA FFT PLOTMAX19708 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fIA = 1.882886MHz
HD2HD3
Rx ADC CHANNEL-QA FFT PLOTMAX19708 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fQA = 1.882886MHz
HD2HD3
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOTMAX19708 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
f1 = 1.885MHz
f2 = 1.985MHz
AIA = -7dBFS
PER TONE
4096-POINT
DATA RECORDf1
Rx ADC CHANNEL-QA
TWO-TONE FFT PLOTMAX19708 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
f1 = 1.885MHz
f2 = 1.985MHz
AIA = -7dBFS
PER TONE
4096-POINT
DATA RECORDf1
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCYMAX19708 toc05
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)102030405060708090100
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCYMAX19708 toc06
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)102030405060708090100
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCYMAX19708 toc07
ANALOG INPUT FREQUENCY (MHz)
THD (dB)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX19708 toc08
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)102030405060708090100
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
MAX19708 toc09
ANALOG INPUT AMPLITUDE (dBFS)
SNR (dB)
fIN = 1.875MHz
ypical Operating Characteristics(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-EndRx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDE
MAX19708 toc10
ANALOG INPUT AMPLITUDE (dBFS)
SINAD (dB)
fIN = 1.875MHz
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT AMPLITUDE
MAX19708 toc11
ANALOG INPUT AMPLITUDE (dBFS)
SFDR (dBc)
fIN = 1.875MHz
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
MAX19708 toc12
SAMPLING RATE (MHz)
SNR (dB)
fIN = 1.875MHz
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE
MAX19708 toc13
SAMPLING RATE (MHz)
SINAD (dB)
fIN = 1.875MHz3567891011
Rx ADC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATEMAX19708 toc14
SAMPLING RATE (MHz)
SFDR (dBc)
fIN = 1.875MHz
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
MAX19708 toc15
CLOCK DUTY CYCLE (%)
SNR (dB)
fIN = 1.875MHz
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
MAX19708 toc16
CLOCK DUTY CYCLE (%)
SINAD (dB)
fIN = 1.875MHz454050556065
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLEMAX19708 toc17
CLOCK DUTY CYCLE (%)
SFDR (dBc)
fIN = 1.875MHz
Rx ADC OFFSET ERROR
vs. TEMPERATURE
MAX19707 toc18
TEMPERATURE (°C)
OFFSET ERROR (%FS)
ypical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-EndTx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT AMPLITUDE
MAX19708 toc22
OUTPUT AMPLITUDE (dBFS)
SFDR (dBc)
fOUT = 620kHz
Rx ADC GAIN ERROR
vs. TEMPERATURE
MAX19708 toc19
TEMPERATURE (°C)
GAIN ERROR (%FS)3567891011
Tx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATEMAX19708 toc20
SAMPLING RATE (MHz)
SFDR (dBc)
fOUT = 617kHz
Tx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY
MAX19708 toc21
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
Tx PATH CHANNEL-ID SPECTRAL PLOTMAX19708 toc23
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fID = 617kHz
Tx PATH CHANNEL-QD SPECTRAL PLOTMAX19708 toc24
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fQD = 617kHz
Tx PATH CHANNEL-ID SPECTRAL PLOT
WITH IMAGE REJECTIONMAX19708 toc25
AMPLITUDE (dBFS)
fID = 800kHz,
fCLK = 5.12MHz
IMAGE REJECTION
Tx PATH CHANNEL-ID TWO-TONE
SPECTRAL PLOTMAX19708 toc26
FREQUENCY (MHz)
AMPLITUDE (dBFS)
f1 = 560kHz,
f2 = 660kHz
Tx PATH CHANNEL-QD TWO-TONE
SPECTRAL PLOTMAX19708 toc27
FREQUENCY (MHz)
AMPLITUDE (dBFS)
f1 = 560kHz,
f2 = 660kHz
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-EndSUPPLY CURRENT vs. SAMPLING RATE
MAX19708 toc28
SAMPLING RATE (MHz)
SUPPLY CURRENT (mA)
Ext4 MODE
IVDD Tx MODE
IVDD Rx MODE
Rx ADC INTEGRAL NONLINEARITYMAX19708 toc29
DIGITAL OUTPUT CODE
INL (LSB)
TRANSMIT FILTER
FREQUENCY RESPONSE
MAX19708 toc30
FREQUENCY (MHz)
AMPLITUDE (dB)
Tx PATH INTEGRAL NONLINEARITY
MAX19708 toc31
DIGITAL INPUT CODE
INL (LSB)
Tx PATH DIFFERENTIAL NONLINEARITY
MAX19707 toc32
DIGITAL INPUT CODE
DNL (LSB)
TRANSMIT FILTER PASSBAND RIPPLE
MAX19708 toc34
FREQUENCY (MHz)
AMPLITUDE (dB)
AUX-DAC INTEGRAL NONLINEARITY
MAX19708 toc35
DIGITAL INPUT CODE
INL (LSB)
AUX-DAC DIFFERENTIAL NONLINEARITY
MAX19708 toc36
DIGITAL INPUT CODE
DNL (LSB)
Typical Operating Characteristics (continued)
(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATUREMAX19708 toc33
TEMPERATURE (°C)
REFP
- V
REFN
(V)60-151035
VREFP - VREFN
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
PINNAMEFUNCTIONREFPUpper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
2, 8, 11, 31,
33, 39, 43VDDAnalog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with
a 0.1µF capacitor.IAPChannel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.IANChannel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
5, 7, 12, 32, 42GNDAnalog Ground. Connect all GND pins to ground plane.CLKConversion Clock Input. Clock signal for both receive ADCs and transmit DACs.QANChannel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
Pin Description
AUX-ADC INTEGRAL NONLINEARITYMAX19708 toc37
DIGITAL OUTPUT CODE
INL (LSB)
AUX-ADC DIFFERENTIAL NONLINEARITY
MAX19708 toc38
DIGITAL OUTPUT CODE
DNL (LSB)
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX19708 toc39
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)10.10.01
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX19708 toc40
OUTPUT SINK CURRENT (mA)
OUTPUT VOLTAGE (V)10.10.01
AUX-DAC SETTLING TIME
MAX19708 toc41
500ns/div
500mV/div
STEP FROM 1/4FS TO 3/4FS
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, TA= +25°C, unless otherwise noted.)
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
PINNAMEFUNCTIONQAPChannel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
13–18, 21–24D0–D9Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most
significant bit (MSB) and D0 is the least significant bit (LSB).OGNDOutput-Driver GroundOVDDOutput-Driver Power Supply. Supply range from +1.8V to VDD. Bypass OVDD to OGND with a
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.SHDNActive-Low Shutdown Input. Apply logic-low to place the MAX19708 in shutdown.DOUTAux-ADC Digital OutputT/RTransmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A
logic-high input sets the device in transmit mode.DIN3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.SCLK3-Wire Serial-Interface Clock InputCS3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface.ADC2Analog Input for Auxiliary ADCADC1Analog Input for Auxiliary ADCDAC3Analog Output for Auxiliary DAC3DAC2Analog Output for Auxiliary DAC2DAC1Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up)
40, 41IDN, IDPTx Path Channel-ID Differential Voltage Output
44, 45QDN, QDPTx Path Channel-QD Differential Voltage OutputREFINReference Input. Connect to VDD for internal reference.COMCommon-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.REFNNegative Reference I/O. Rx ADC conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a
0.1µF capacitor.EPExposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
Pin Description (continued)SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Detailed DescriptionThe MAX19708 integrates a dual, 10-bit Rx ADC and a
dual, 10-bit Tx DAC with TD-SCDMA baseband filters
while providing ultra-low power and high dynamic per-
formance at 11Msps conversion rate. The Rx ADC ana-
log input amplifiers are fully differential and accept
1.024VP-P full-scale signals. The Tx DAC analog out-
puts are fully differential with ±410mV or ±500mV full-
scale output, selectable common-mode DC level, and
adjustable I/Q offset trim.
The MAX19708 integrates three 12-bit auxiliary DAC
(aux-DAC) channels and a 10-bit, 333ksps auxiliary
ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC
channels feature 1µs settling time for fast AGC, VGA,
and AFC level setting. The aux-ADC features data aver-
aging to reduce processor overhead and a selectable
clock-divider to program the conversion rate.
The MAX19708 includes a 3-wire serial interface to
control operating modes and power management. The
serial interface is SPI™ and MICROWIRE™ compatible.
The MAX19708 serial interface selects shutdown, idle,
standby, transmit (Tx), and receive (Rx) modes, as well
as controlling aux-DAC and aux-ADC channels.
The Rx ADC and Tx DAC share a common digital I/O to
reduce the digital interface to a single 10-bit parallel
multiplexed bus. The 10-bit digital bus operates on a
single +1.8V to +3.3V supply.
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-EndFigure 1. Rx ADC Internal T/H Circuits
S3b
S3a
COM
S5b
S5a
QAP
QAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
HOLDHOLDCLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACKTRACK
S2a
S2b
S3b
S3a
COM
S5b
S5a
IAP
IAN
OUT
OUT
C2a
C2b
S4c
S4a
S4bC1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
S2a
S2b
MAX19708
Dual 10-Bit Rx ADCThe ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
QA. The ADC full-scale analog input range is ±VREF
with a VDD/ 2 (±0.2V) common-mode input range. VREF
is the difference between VREFPand VREFN. See the
Reference Configurationssection for details.
Input Track-and-Hold (T/H) CircuitsFigure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differen-
tially or single-ended. Match the impedance of IAP and
IAN, as well as QAP and QAN, and set the input signal
common-mode voltage within the VDD/2 (±200mV) Rx
ADC range for optimum performance.
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Rx ADC System Timing RequirementsFigure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel I
(CHI) and channel Q (CHQ) are sampled on the rising
edge of the clock signal (CLK) and the resulting data is
multiplexed at the D0–D9 outputs. CHI data is updated
on the rising edge and CHQ data is updated on the
falling edge of the CLK. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for CHI and 5.5 clock cycles for CHQ.
Digital Input/Output Data (D0–D9)D0–D9 are the Rx ADC digital logic outputs when the
MAX19708 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic inputs
when the MAX19708 is in transmit mode. The logic level
is set by OVDDfrom 1.8V to VDD. The digital output cod-
ing is offset binary (Table 1). Keep the capacitive load
on the digital outputs D0–D9 as low as possible
(< 15pF) to avoid large digital currents feeding back into
the analog portion of the MAX19708 and degrading its
dynamic performance. Buffers on the digital outputs iso-
late the outputs from heavy capacitive loads. Adding
100Ωresistors in series with the digital outputs close to
the MAX19708 will help improve ADC performance.
Refer to the MAX19708EVKIT schematic for an example
of the digital outputs driving a digital buffer through
100Ωseries resistors.
During SHDN, IDLE, and STBY states, D0–D9 are inter-
nally pulled up to prevent floating digital inputs. To
ensure no current flows through D0–D9 I/O, the external
bus needs to be either tri-stated or pulled up to OVDD
and should not be pulled to ground.
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGEDIFFERENTIAL INPUT (LSB)OFFSET BINARY (D0–D9)OUTPUT DECIMAL CODEVREF x 512/512511 (+Full Scale - 1 LSB)11 1111 11111023
VREF x 511/512510 (+Full Scale - 2 LSB)11 1111 11101022
VREF x 1/512+110 0000 0001513
VREF x 0/5120 (Bipolar Zero)10 0000 0000512
-VREF x 1/512-101 1111 1111511
-VREF x 511/512-511 (-Full Scale +1 LSB)00 0000 00011
-VREF x 512/512-512 (-Full Scale)00 0000 00000
Figure 2. Rx ADC Transfer Function
INPUT VOLTAGE (LSB)-510-509
2 x VREF1 LSB = VREF = VREFP - VREFN
VREFVREF
REF
REF1-511+510+512+511-512+509
(COM)
(COM)
OFFSET BINAR
Y OUTPUT CODE (LSB)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0011
11 1111 1111
11 1111 1110
11 1111 1101
01 1111 1111
10 0000 0000
10 0000 0001
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-EndFigure 3. Rx ADC System Timing Diagram
tDOQ
tCLtCH
tCLK
tDOI
5 CLOCK-CYCLE LATENCY (CHI)
5.5 CLOCK-CYCLE LATENCY (CHQ)
D0–D9D0QD1ID1QD2ID2QD3ID3QD4ID4QD5ID5QD6ID6Q
CHI
CHQ
CLK
Table 2. Tx Path Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC= 1.024V, External Reference Mode VREFDAC= VREFIN; VFS= 410 for 820mVP-P
Full Scale and VFS= 500 for 1VP-PFull Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V)OFFSET BINARY (D0–D9)INPUT DECIMAL CODE11 1111 11111023
11 1111 11101022
10 0000 0001513
10 0000 0000512
01 1111 1111511
00 0000 00011
00 0000 00000VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×VREFDAC
1023()×−VREFDAC
1023()×−VREFDAC
1023()×−
Dual 10-Bit Tx DAC and Transmit PathThe dual 10-bit digital-to-analog converters (Tx DAC)
operate with clock speeds up to 11MHz. The Tx DAC
digital inputs, D0–D9, are multiplexed on a single 10-bit
bus. The voltage reference determines the Tx path full-
scale voltage at IDP, IDN and QDP, QDN analog out-
puts. See the Reference Configurationssection for
setting reference voltage. Each Tx path output channel
integrates a lowpass filter tuned to meet the TD-SCDMA
spectral mask requirements.
The TD-SCDMA filters are tuned for 1.32MHz cutoff fre-
quency and > 55dB image rejection at fIMAGE=
4.32MHz, fOUT= 800kHz, and fCLK= 5.12MHz. See
Figure 4 for an illustration of the filter frequency response.
Buffer amplifiers follow the TD-SCDMA filters. The amplifi-
er outputs (IDN, IDP, QDN, QDP) are biased at an
adjustable common-mode DC level and designed to
drive a differential input stage with ≥70kΩinput imped-
ance. This simplifies the analog interface between RF
MAX19708
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-Endquadrature upconverters and the MAX19708. Many RF
upconverters require a 0.9V to 1.4V common-mode bias.
The MAX19708 common-mode DC bias eliminates dis-
crete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC. The Tx DAC differential analog outputs cannot
be used in single-ended mode because of the internally
generated common-mode DC level. Table 2 shows the
Tx path output voltage vs. input codes. Table 11 shows
the selection of DC common-mode levels. See Figure 5
for an illustration of the Tx DAC analog output levels.
The buffer amplifiers also feature a programmable full-
scale output level of ±410mV or ±500mV and indepen-
dent DC offset trim on each I/Q channel. Both features
are configured through the SPI interface. The DC offset
correction is used to optimize sideband and carrier sup-
pression in the Tx signal path (see Tables 8 and 10).
Tx DAC TimingFigure 6 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel (ID) is
latched on the falling edge of the clock signal, and Q-
channel (QD) data is latched on the rising edge of the
clock signal. Both I and Q outputs are simultaneously
updated on the next rising edge of the clock signal.
3-Wire Serial Interface and
Operation ModesThe 3-wire serial interface controls the MAX19708 oper-
ation modes as well as the three 12-bit aux-DACs and
the 10-bit aux-ADC. Upon power-up, program the
MAX19708 to operate in the desired mode. Use the 3-
wire serial interface to program the device for shutdown,
idle, standby, Rx, Tx, aux-DAC controls, or aux-ADC
conversion. A 16-bit data register sets the mode control
as shown in Table 3. The 16-bit word is composed of
A3–A0 control bits and D11–D0 data bits. Data is shifted
in MSB first (D11) and LSB last (A0). Tables 4, 5, and 6
show the MAX19708 operating modes and SPI com-
mands. The serial interface remains active in all modes.
SPI Register DescriptionProgram the control bits, A3–A0, in the register as shown
in Table 3 to select the operating mode. Modify A3–A0
bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2,
Aux-DAC3, IOFFSET, QOFFSET, Aux-ADC, ENABLE-8,
and COMSEL modes. ENABLE-16 is the default operat-
ing mode. This mode allows for shutdown, idle, and
standby states as well as switching between FAST,
SLOW, Rx and Tx modes. Table 4 shows the MAX19708
power-management modes. Table 5 shows the T/Rpin-
controlled external Tx-Rx switching modes. Table 6
shows the SPI-controlled Tx-Rx switching modes.
Figure 4. TD-SCDMA Filter Frequency Response
CHANNEL EDGE
IMAGE1.27
fCLK
FREQ (MHz)
NOT TO SCALE
-49.3dB
-15dB
-3dB
0dB
-55dB (min)
-57.1dB
OCCUPIED
CHANNELAMPLITUDE
TD-SCDMA
FILTER RESPONSE
DAC sin(x)/x
RESPONSE
Tx PATH:
SFDR = 73dBc
THD = -71dB
SNR = 56.5dB
