MAX19705ETM+ ,10-bit, 7.5Msps, Ultra-Low-Power Analog Front-EndFeaturesThe MAX19705 is an ultra-low-power, mixed-signal ana- ♦ Dual 10-Bit, 7.5Msps Rx ADC and Dua ..
MAX19707ETM ,10-Bit, 45Msps, Ultra-Low-Power Analog Front-EndApplications21IDN 40 D6WiMAX CPEs VoIP Terminals 20IDP 41 OVDDGND 42 19 OGND802.11a/b/g WLAN Portab ..
MAX19707ETM+ ,10-Bit, 45Msps, Ultra-Low-Power Analog Front-EndELECTRICAL CHARACTERISTICS(V = 3V, OV = 1.8V, internal reference (1.024V), C ≈ 10pF on all digital ..
MAX19707ETM+ ,10-Bit, 45Msps, Ultra-Low-Power Analog Front-EndFeaturesThe MAX19707 is an ultra-low-power, mixed-signal ana- ♦ Dual, 10-Bit, 45Msps Rx ADC and Dua ..
MAX19708ETM+T ,10-bit, 11Msps, Ultra-Low-Power Analog Front-EndFeatures♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,The MAX19708 is an ultra-low-power, mixed-sign ..
MAX1970EEE+ ,Dual, 180° Out-of-Phase, 1.4MHz, 750mA Step-Down Regulator with POR and RSI/PFOApplicationsPART TEMP RANGE PIN-PACKAGExDSL Modems USB-Powered DevicesMAX1970EEE -40°C to +85°C 16 ..
MAX4944ELA+ ,Overvoltage-Protection Controllers with Internal FETMAX4943–MAX4946/MAX4944L/MAX4945A/MAX4945L/MAX494919-0552; Rev 3; 6/08Overvoltage-Protection Contro ..
MAX4944ELA+T ,Overvoltage-Protection Controllers with Internal FETApplicationsACOK 4 5 GNDMAX4949Cell Phones PDAs and Palmtop DevicesµDFN2mm × 2mmDigital Still Camer ..
MAX4944LELA+ ,Overvoltage-Protection Controllers with Internal FETApplicationsACOK 4 5 GNDMAX4949Cell Phones PDAs and Palmtop DevicesµDFN2mm × 2mmDigital Still Camer ..
MAX4945AELA+ ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4945LELA+T ,Overvoltage-Protection Controllers with Internal FETFeaturesThe MAX4943–MAX4946/MAX4949 family of overvolt- ♦ Input Voltage Protection Up to +28Vage-pr ..
MAX4946ELA+ ,Overvoltage-Protection Controllers with Internal FETELECTRICAL CHARACTERISTICS(V = +5V (MAX4943/MAX4944_/MAX4945_/MAX4949), V = +3V (MAX4946), T = -40° ..
MAX19705ETM+
10-bit, 7.5Msps, Ultra-Low-Power Analog Front-End
General DescriptionThe MAX19705 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for power-sensitive com-
munication equipment. Optimized for high dynamic
performance at ultra-low power, the device integrates a
dual 10-bit, 7.5Msps receive (Rx) ADC; dual 10-bit,
7.5Msps transmit (Tx) DAC; three fast-settling 12-bit
aux-DAC channels for ancillary RF front-end control;
and a 10-bit, 333ksps housekeeping aux-ADC. The typ-
ical operating power in Tx-Rx FAST mode is 28.2mW at
a 7.5MHz clock frequency.
The Rx ADCs feature 55.1dB SNR and 73.4dBc SFDR at
a 1.875MHz input frequency with a 7.5MHz clock fre-
quency. The analog I/Q input amplifiers are fully differen-
tial and accept 1.024VP-Pfull-scale signals. Typical I/Q
channel matching is ±0.01°phase and ±0.02dB gain.
The Tx DACs feature 77.2dBc SFDR at fOUT= 620kHz
and fCLK= 7.5MHz. The analog I/Q full-scale output
voltage is ±400mV differential. The Tx DAC common-
mode DC level is programmable from 0.9V to 1.35V.
The I/Q channel offset is adjustable. The typical I/Q
channel matching is ±0.03dB gain and ±0.08°phase.
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
The MAX19705 operates on a single +2.7V to +3.3V
analog supply and +1.8V to +3.3V digital I/O supply.
The MAX19705 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The Selector Guideat the end of the
data sheet lists other pin-compatible versions in this
AFE family.
ApplicationsBroadband Access Radio
Private Mobile Radio (PMR)
Portable Communication Equipment
FeaturesDual 10-Bit, 7.5Msps Rx ADC and Dual 10-Bit,
7.5Msps Tx DACUltra-Low Power
28.2mW at fCLK= 7.5MHz, Fast Mode
21mW at fCLK= 7.5MHz, Slow Mode
Low-Current Standby and Shutdown ModesProgrammable Tx DAC Common-Mode DC Level
and I/Q Offset TrimExcellent Dynamic Performance
SNR = 55.1dB at fIN= 1.875MHz (Rx ADC)
SFDR = 77.2dBc at fOUT= 620kHz (Tx DAC)Three 12-Bit, 1µs Aux-DACs10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
Data AveragingExcellent Gain/Phase Match
±0.01°Phase, ±0.02dB Gain (Rx ADC) at
fIN= 1.875MHzMultiplexed Parallel Digital I/OSerial-Interface ControlVersatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx DisableMiniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End19-3763; Rev 0; 8/05
EVALUATION KIT
AVAILABLE
Ordering Information
PART*PIN-PACKAGEPKG CODEMAX19705ETM48 Thin QFN-EP**T4877-4
MAX19705ETM+48 Thin QFN-EP**T4877-4
*All devices are specified over the -40°C to +85°C operating
range.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram and Selector Guide appear at end of
data sheet.OVDD
OGNDVDD
IDN
IDP
GND
VDD
QDN
QDP
REFN
EXPOSED PADDLE (GND)REFIN
DAC1
COM
DAC237345678910
ADC1ADC2V
GNDVSCLKDINT/RSHDNDOUTDAC3
THIN QFNMAX19705
TOP VIEW
REFP
IAPIAN
GND
CLK
GND
QAN
QAP
GND123534333231302928272625
Pin Configuration
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND, OVDDto OGND..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND...........-0.3V to (VDD + 0.3V)
D0–D9, DOUT, T/R, SHDN, SCLK, DIN, CS,
CLK to OGND.....................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin Thin QFN (derate 27.8mW/°C above +70°C).....2.22W
Thermal Resistance θJA..................................................36°C/W
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.03.3V
Output Supply VoltageOVDD1.8VDDV
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
fCLK = 7.5MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
fCLK = 7.5MHz, fOUT = 620kHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
fCLK = 7.5MHz, fIN = 1.875MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
VDD Supply Current
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
fCLK = 7.5MHz, fIN = 1.875MHz on both
channels; aux-DACs ON and at midscale,
aux-ADC ON
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSStandby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: fCLK = 7.5MHz; aux-DACs ON
and at midscale, aux-ADC ON4.76VDD Supply Current
Shutdown mode: CLK = 0 or OVDD0.6µA
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): fCLK = 7.5MHz,
fIN = 1.875MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
1.4mA
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
operating mode (Tx): fCLK = 7.5MHz, fOUT
= 620kHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OVDD; aux-
DACs ON and at midscale, aux-ADC ON1
Idle mode: fCLK = 7.5MHz; aux-DACs ON
and at midscale, aux-ADC ON13.8
OVDD Supply Current
Shutdown mode: CLK = 0 or OVDD0.01
Rx ADC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.6LSB
Differential NonlinearityDNLGuar anteed no m i ssi ng cod e ( N ote 2) -1±0.4+1LSB
Offset ErrorResidual DC offset error-5.5±0.4+5.5%FS
Gain ErrorInclude reference error-8±1.65+11%FS
DC Gain Matching-0.25±0.01+0.25dB
Offset Matching±12LSB
Gain Temperature Coefficient±13ppm/°C
Offset error (VDD ±5%)±1.7LSBPower-Supply RejectionPSRRGain error (VDD ±5%)±0.05%FS
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx ADC ANALOG INPUTInput Differential RangeVIDDifferential or single-ended inputs±0.512V
Input Common-Mode Voltage
RangeVCMVDD / 2V
RINSwitched capacitor load720kΩInput ImpedanceCIN5pF
Rx ADC CONVERSION RATEMaximum Clock FrequencyfCLK(Note 3)7.5MHz
Channel I5Data Latency (Figure 3)Channel Q5.5
Clock
Cycles
Rx ADC DYNAMIC CHARACTERISTICS (Note 4)fIN = 1.875MHz, fCLK = 7.5MHz53.755.1Signal-to-Noise RatioSNRfIN = 3.5MHz, fCLK = 7.5MHz55.1dB
fIN = 1.875MHz, fCLK = 7.5MHz53.655Signal-to-Noise and DistortionSINADfIN = 3.5MHz, fCLK = 7.5MHz55dB
fIN = 1.875MHz, fCLK = 7.5MHz6473.4Spurious-Free Dynamic RangeSFDRfIN = 3.5MHz, fCLK = 7.5MHz74dBc
fIN = 1.875MHz, fCLK = 7.5MHz-84.5Third-Harmonic DistortionHD3fIN = 3.5MHz, fCLK = 7.5MHz-82.5dBc
Intermodulation DistortionIMDf1 = 1.8MHz, -7dBFS;
f2 = 1.0MHz, -7dBFS-69.5dBc
Third-Order Intermodulation
DistortionIM3f1 = 1.8MHz, -7dBFS;
f2 = 1.0MHz, -7dBFS-78.1dBc
fIN = 1.875MHz, fCLK = 7.5MHz-71.9-62.5Total Harmonic DistortionTHDfIN = 3.5MHz, fCLK = 7.5MHz-72dB
Aperture Delay3.5ns
Overdrive Recovery Time1.5x full-scale input2ns
Rx ADC INTERCHANNEL CHARACTERISTICSCrosstalk RejectionfIN X ,Y = 1.875M H z at - 0.5d BFS , fIN X ,Y = 1M H z
at - 0.5d BFS ( N ote 5) -91.5dB
Amplitude MatchingfIN = 1.875MHz at -0.5dBFS (Note 6)±0.02dB
Phase MatchingfIN = 1.875MHz at -0.5dBFS (Note 6)±0.01D eg r ees
MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3V, OVDD= 1.8V, internal reference (1.024V), CL≈10pF on all digital outputs, fCLK= 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP= CREFN=
CCOM= 0.33µF, unless otherwise noted. CL< 5pF on all aux-DAC outputs. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Tx DAC DC ACCURACYResolutionN10Bits
Integral NonlinearityINL±0.35LSB
Differential NonlinearityDNLGuaranteed monotonic (Note 2)-1±0.25+1LSB
Residual DC OffsetVOS-4±0.06+4mV
Full-Scale Gain ErrorIncl ud e r efer ence er r or ( p eak- to- p eak er r or ) -55+55mV
Tx DAC DYNAMIC PERFORMANCEDAC Conversion RatefCLK(Note 3)7.5MHz
In-Band Noise DensityNDfOUT = 620kHz, fCLK = 7.5MHz-127dBc/Hz
Third-Order Intermodulation
DistortionIM3f1 = 620kHz, f2 = 640kHz78dBc
Glitch Impulse10pV•s
Spurious-Free Dynamic Range to
NyquistSFDRfCLK = 7.5MHz, fOUT = 620kHz5977.2dBc
Total Harmonic Distortion to
NyquistTHDfCLK = 7.5MHz, fOUT = 620kHz-76.1-59.5dB
Signal-to-Noise Ratio to NyquistSNRfCLK = 7.5MHz, fOUT = 620kHz61dB
Tx DAC INTERCHANNEL CHARACTERISTICSI-to-Q Output IsolationfOUTX,Y = 500kHz, fOUTX,Y = 620kHz90dB
Gain Mismatch Between DAC
OutputsMeasured at DC-0.4±0.03+0.4dB
Phase Mismatch Between DAC
OutputsfOUT = 620kHz, fCLK = 7.5MHz±0.08D eg r ees
Differential Output Impedance800Ω
Tx DAC ANALOG OUTPUTFull-Scale Output VoltageVFS±400mV
Bits CM1 = 0, CM0 = 0 (default)1.301.351.48
Bits CM1 = 0, CM0 = 11.2
Bits CM1 = 1, CM0 = 01.05Output Common-Mode VoltageVCOM
Bits CM1 = 1, CM0 = 10.9
