MAX198BCWI+ ,6-Channel, Multirange, 5V, 12-Bit DAS with 12-Bit Bus Interface and Fault Protectionfeatures include a 5MHzbandwidth track/hold, 100ksps throughput rate, soft-ware-selectable internal ..
MAX198BENI ,Multirange, Single %V, 12-Bit DAS with 12-Bit Bus InterfaceELECTRICAL CHARACTERISTICS (continued)(V = 5V ±5%; unipolar/bipolar range; external reference mode, ..
MAX198BENI+ ,6-Channel, Multirange, 5V, 12-Bit DAS with 12-Bit Bus Interface and Fault ProtectionGeneral Description ________
MAX1992ETG ,Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output VoltagesFeaturesThe MAX1992/MAX1993 pulse-width modulation (PWM)♦ Inductor Saturation Protectioncontrollers ..
MAX1992ETG+ ,Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output VoltagesELECTRICAL CHARACTERISTICS(V+ = 15V, V = V = SHDN = 5V, SKIP = GND, T = 0°C to +85°C, unless otherw ..
MAX1992ETG+T ,Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output VoltagesApplications18 17 16 15 14 13Notebook Computers VDD 19 CSN1220 11 CSPPGNDCore/IO Supplies as Low as ..
MAX5024MASA+ ,65V, Low-Quiescent-Current, High-Voltage Linear Regulators with µP Reset and Watchdog TimerApplicationsRESET RESET● AutomotiveONOFFEN● IndustrialWDI I/O● Home SecurityI/OHOLD● Fire/Smoke Ala ..
MAX5024SASA+ ,65V, Low-Quiescent-Current, High-Voltage Linear Regulators with µP Reset and Watchdog TimerMAX5023/MAX5024 65V, Low-Quiescent-Current, High-Voltage Linear Regulators with μP Reset and Watchd ..
MAX5024TASA ,65V, low-quiescent-current, high-voltage linear regulator with mP reset and watchdog timerFeaturesThe MAX5023/MAX5024 high-voltage linear regulators Wide Operating Input Voltage Rangeopera ..
MAX5024TASA+ ,65V, Low-Quiescent-Current, High-Voltage Linear Regulators with µP Reset and Watchdog TimerMAX5023/MAX5024 65V, Low-Quiescent-Current, High-Voltage Linear Regulators with μP Reset and Watchd ..
MAX5025EUT+T ,500kHz, 36V Output, SOT23, PWM Step-Up DC-DC ConvertersELECTRICAL CHARACTERISTICS(V = 5V, SHDN = V , T = -40°C to +85°C, unless otherwise noted. Typical v ..
MAX5026EUT ,RELIABILITY REPORT FOR MAX5026EUT PLASTIC ENCAPSULATED DEVICES MAX5026EUT Rev. A RELIABILITY REPORT FOR MAX5026EUT PLASTIC ENCA ..
MAX196ACAI+-MAX196ACNI+-MAX196ACWI+-MAX196AEAI+-MAX196AENI+-MAX196AEWI+-MAX196BCNI+-MAX196BENI+-MAX196BEWI+-MAX198ACNI+-MAX198ACWI+-MAX198BCAI+-MAX198BCNI+-MAX198BCWI+-MAX198BENI+
6-Channel, Multirange, 5V, 12-Bit DAS with 12-Bit Bus Interface and Fault Protection
_______________General DescriptionThe MAX196/MAX198 multirange, 12-bit data-acquisi-
tion systems (DAS) require only a single +5V supply for
operation, yet convert analog signals at their inputs up
to ±10V (MAX196) and ±4V (MAX198). These systems
provide six analog input channels that are indepen-
dently software programmable for a variety of ranges:
±10V, ±5V, 0V to +10V, and 0V to +5V for the MAX196;
±VREF, ±VREF/2, 0V to +VREF, and 0V to +VREF/2 for
the MAX198. This range switching increases the effec-
tive dynamic range to 14 bits and provides the flexibility
to interface ±12V, ±15V, and 4mA to 20mA powered
sensors to a single +5V system. In addition, these con-
verters are fault protected to ±16.5V; a fault condition
on any channel will notaffect the conversion result of
the selected channel. Other features include a 5MHz
bandwidth track/hold, 100ksps throughput rate, soft-
ware-selectable internal/external clock, internal/external
acquisition control, 12-bit parallel interface, and internal
4.096V or external reference.
Two programmable power-down modes (STBYPD,
FULLPD) provide low-current shutdown between con-
versions. In STBYPD mode, the reference buffer
remains active, eliminating start-up delays.
The MAX196/MAX198 employ a standard microproces-
sor (μP) interface. A three-state data I/O port is config-
ured to operate with 16-bit data buses, and data-
access and bus-release timing specifications are com-
patible with most popular μPs. All logic inputs and out-
puts are TTL/CMOS compatible.
These devices are available in 28-pin DIP, wide SO,
SSOP (55% smaller in area than wide SO), and ceramic
SB packages. For 8+4 bus interface, see the MAX197
and the MAX199 data sheets. An evaluation kit will be
available after December 1995 (MAX196EVKIT-DIP).
________________________ApplicationsIndustrial-Control Systems
Robotics
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
Telecommunications
____________________________Features12-Bit Resolution, 1/2LSB LinearitySingle +5V Supply OperationSoftware-Selectable Input Ranges:
±10V, ±5V, 0V to +10V, 0V to +5V (MAX196)
±VREF, ±VREF/2, 0V to +VREF, 0V to +VREF/2
(MAX198)Internal 4.096V or External ReferenceFault-Protected Input Multiplexer6 Analog Input Channels6μs Conversion Time, 100ksps Sampling RateInternal or External Acquisition ControlTwo Power-Down ModesInternal or External Clockultirange, Single +5V, 12-Bit DAS ith 12-Bit Bus Interface
________________________________________________________________Maxim Integrated Products1DGND
VDD
INT
REF
AGND
REFADJ
CH5
CH4
CH3
CH2
CH1
CH0
D10
D11
CLK
DIP/SO/SSOP/Ceramic SBTOP VIEW
MAX196
MAX198
__________________Pin Configuration
Call toll free 1-800-722-8266 for free samples or literature.19-0435; Rev 0; 9/95
PART
MAX196ACNIMAX196BCNI
MAX196ACWI0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGEPIN-PACKAGE28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
EVALUATION KIT
AVAILABLE
______________Ordering InformationMAX196BCWI0°C to +70°C28 Wide SO
Functional Diagram appears at end of data sheet.
Ordering Information continued at end of data sheet.MAX196ACAI0°C to +70°C28 SSOP
MAX196BCAI0°C to +70°C28 SSOP
Aperture Jitter
Multirange, Single +5V, 12-Bit DASith 12-Bit Bus Interface_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7μF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +7V
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (VDD+ 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
CH0–CH5 to AGND..........................................................±16.5V
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C)......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
MAX196_C_ I/MAX198_C_ I.................................0°C to +70°C
MAX196_E_ I/MAX198_E_ I...............................-40°C to +85°C
MAX196_MYI/MAX198_MYI.............................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX196A/MAX198A
Internal CLK mode/internal acquisition
control (Note 4)
External CLK mode/external acquisition control
External CLK mode/external acquisition control
50kHz, VIN= ±5V (MAX196) or ±4V (MAX198)
(Note 3)
Up to the 5th harmonic
Bipolar
MAX196B/MAX198B
Unipolar
MAX196A/MAX198A
CONDITIONS<5015Aperture Delay-86Channel-to-Channel Crosstalk80SFDRSpurious-Free Dynamic Range-85-78THDTotal Harmonic Distortion70
LSB±1/2INLIntegral Nonlinearity
Bits12Resolution
±0.5LSB±0.1Channel-to-Channel Offset
Error Matching
±10
LSB±1DNLDifferential Nonlinearity
LSB
Offset Error±5
UNITSMINTYPMAXSYMBOLPARAMETERBipolar
Unipolarppm/°C3Gain Temperature Coefficient
(Note 2)
±10LSB
Gain Error
(Note 2)
±10
MAX196B/MAX198B69SINADSignal-to-Noise + Distortion Ratio
Bipolar
Unipolar
Bipolar
MAX196B/MAX198B
MAX196B/MAX198B
Unipolar
MAX196B/MAX198B
MAX196B/MAX198B
MAX196A/MAX198A
MAX196A/MAX198A
MAX196A/MAX198A
MAX196A/MAX198A
ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, ±10Vp-p (MAX196) or ±4.096Vp-p (MAX198), fSAMPLE= 100ksps)
ultirange, Single +5V, 12-Bit DAS ith 12-Bit Bus Interface_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7μF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
MAX198
MAX196
MAX198
MAX196
IIN-1200720μA
±VREF/2 range
±VREFrange
±5V range
±10V range
Bipolar
Input Voltage Range
(see Table 3)VIN-10105MAX196
-VREFVREF
-VREF/2VREF/2MAX198
Bipolar
MAX196
MAX198
0V to 5V or 0V to VREF/2 range
0V to 10V or 0V to VREFrange
±5V or ±VREF/2 range
±10V or ±VREFrange
Buffer Voltage Gain1.6384V/V
REFADJ Adjustment Range±1.5%With recommended circuit (Figure 1)
Capacitive Bypass at REF4.7μF
REFADJ Output Voltage2.4652.5002.535V
Load Regulation10mV0mA to 0.5mA output current (Note 6)VREFVREF/2
Unipolar
Input ResistanceΔVIN
ΔIINkΩ16
Unipolar
Input Current
Bipolar
0V to 5V range
0V to 10V range
Unipolar
2.5Small-Signal Bandwidth
MHz
PARAMETERSYMBOLMINTYPMAXUNITS-3dB
rolloff
Track/Hold Acquisition Time3μs
Input Capacitance 40pF
REF Output VoltageVREF4.0764.0964.116V
REF Output Tempco
(Contact Maxim Applications for
guaranteed temperature drift
specifications)
ppm/°C
Output Short-Circuit Current30mA
CONDITIONS(Note 5)= +25°C
MAX196_C/MAX198_C
fCLK= 2.0MHz
TC VREFMAX196_M/MAX198_MMAX196_E/MAX198_E
ANALOG INPUT
INTERNAL REFERENCE
Input Capacitance
Multirange, Single +5V, 12-Bit DASith 12-Bit Bus Interface_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7μF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX; unless otherwise noted. Typical values are at TA= +25°C.)2.44.18Input Voltage Range400Input CurrentVREF=
4.18V1VDD- 50mVREFADJ Threshold for
Buffer Disable
Normal, or STANDBY power-down modekΩ10Input ResistanceFULL power-down mode5MΩ
Normal, or STANDBY
power-down mode
FULL power-down mode
Internal acquisition3.05.0
External reference = 4.096V
After FULLPD or STBYPD
External acquisition (Note 9)
CONDITIONSFULLpower-down mode (Note 7)
3.0tACQI
Acquisition Time
LSB±0.1±1/2PSRRPower-Supply Rejection Ratio
(Note 8)
3.0tACQE
External CLKμs4.755.25VDDSupply Voltage
6.0tCONVConversion TimeInternal CLK, CCLK= 100pF6.07.710.0
To 0.1mV REF bypass
capacitor fully dischargedms8Reference Buffer Settling120
Normal mode, bipolar ranges
Normal mode, unipolar ranges
UNITSMINTYPMAXSYMBOLPARAMETERSTANDBYpower-down mode18
IDDSupply Current610
Internal reference±1/2
CCLK= 100pFMHz1.251.562.00fCLKInternal Clock Frequency
0.12.0fCLKExternal Clock Frequency RangeMHz
External CLK
Internal CLK
Power-up (Note 10)μs200Bandgap Reference
Start-Up Time
External CLKksps100Throughput RateInternal CLK, CCLK= 100pF62
CREF= 4.7μF
CREF= 33μF
CIN15pF(Note 5)
Input Leakage CurrentIIN±10μAVIN= 0V or VDD
Input Low VoltageVINL0.8V
Input High VoltageVINH2.4V
POWER REQUIREMENTS
TIMING
REFERENCE INPUT(buffer disabled, reference input applied to REF pin)
DIGITAL INPUTS(D7–D0, CLK, RD, WR, CS) (Note 11)
ultirange, Single +5V, 12-Bit DAS ith 12-Bit Bus Interface_______________________________________________________________________________________5
Note 1:Accuracy specifications tested at VDD= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2:External reference: VREF= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3:Ground “on” channel; sine wave applied to all “off” channels.
Note 4:Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5:Guaranteed by design. Not tested.
Note 6:Use static loads only.
Note 7:Tested using internal reference.
Note 8:PSRR measured at full-scale.
Note 9:External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WRwith ACQMOD
= high control byte.
Note 10:Not subject to production testing. Provided for design guidance only.
Note 11:All input control signals specified with tR= tF= 5ns from a voltage level of 0.8V to 2.4V.
Note 12:tDOis measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13:tTRis defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7μF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX; unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; unipolar/bipolar range; external reference mode, VREF= 4.096V; 4.7μF at REF pin; external clock, fCLK= 2.0MHz
with 50% duty cycle; TA= TMINto TMAX; unless otherwise noted. Typical values are at TA= +25°C.)
Three-State Output CapacitanceCOUT15pF(Note 5)
Output High VoltageVOHVDD- 1VVDD= 4.75V, ISOURCE= 1mA
Output Low VoltageVOL0.4VVDD= 4.75V, ISINK= 1.6mA
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
DIGITAL OUTPUTS(D11–D0, INT)Low to Output Data ValidtDO120nsFigure 2, CL= 100pF (Note 12)
Data Valid to WRSetup
Data Valid to WRHoldtDH0ns
tDS60ns
CLK to WRSetup Time
CLK to WRHold TimetCWH50ns
tCWS100nsto RDSetup Timeto RDHold TimetCSRH0ns
tCSRS0nsto WRSetup Timeto WRHold TimetCSWH0ns
tCSWS0ns
WRPulse WidthtWR80ns
PARAMETERSYMBOLMINTYPMAXUNITSPulse WidthtCS80nsLow to INTHigh DelaytINT1120nsHigh to Output DisabletTR
CONDITIONSns(Note 13)
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX196/8-3
INPUT FREQUENCY (kHz)
TIV
ITS
fSAMPLE = 100kHz
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX196/8-1
DIGITAL CODE
LIN
ITY
(LS
Multirange, Single +5V, 12-Bit DASith 12-Bit Bus Interface_______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
-55-3545105125TEMPERATURE (°C)
F (V
REFERENCE OUTPUT VOLTAGE (VREF)
vs. TEMPERATURE
MAX196/8-4
REFADJ
AV = 1.6384
REF+2.5V
INTERNAL
REFERENCE
MAX196/8-6
-70-5050110130TEMPERATURE (°C)
-TO
T-E
(L
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX196/8-5
-70-5050110130TEMPERATURE (°C)
(LS
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
100Hz
120Hz
VDD = 5V ±0.25V
-70-5050110130TEMPERATURE (°C)
-TO
(L
CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE
MAX196/8-7
FFT PLOT
FREQUENCY (kHz)
LITU
(d
fTONE = 10kHz
fSAMPLE = 100kHz
MAX196/8-2
ultirange, Single +5V, 12-Bit DAS ith 12-Bit Bus Interface_______________________________________________________________________________________7
______________________________________________________________Pin DescriptionDigital GroundDGND28
+5V Supply. Bypass with 0.1μF capacitor to AGND.VDD27
In the internal acquisition mode, when CSis low, a rising edge on WRlatches in configuration data and starts an
acquisition plus a conversion cycle. In the external acquisition mode, when CSis low, the first rising edge on WR
starts an acquisition, and a second rising edge on WRends acquisition and starts a conversion cycle.26
PINChip Select, active lowCS2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode,
place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK= 1.56MHz typical
with CCLK= 100pF.
CLK1
FUNCTIONNAME100k
510k
24k
REFADJ
+5V
0.01mF
MAX196
MAX198
Figure 1. Reference-Adjust Circuit
DOUT
DOUT
+5V
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOL
CLOAD
CLOAD
Figure 2. Load Circuits for Enable Time
_______________Detailed Description
Converter OperationThe MAX196/MAX198 multirange, fault-tolerant ADCs
use successive approximation and internal input
track/hold (T/H) circuitry to convert an analog signal to
a 12-bit digital output. The 12-bit parallel-output format
provides easy interface to microprocessors (μPs).
Figure 3 shows the MAX196/MAX198 in the simplest
operational configuration.
Analog-Input Track/HoldIn the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode and unipolar mode (MAX196 only), a low-
impedance input source, which settles in less than
1.5μs, is required to maintain conversion accuracy at
the maximum conversion rate.
When the MAX198 is configured for unipolar mode, the
input does not need to be driven from a low-impedance
source. The acquisition time (tAZ) is a function of the
source output resistance (RS), the channel input resis-
tance (RIN), and the T/H capacitance.
Three-State Digital I/O, D11 = MSBD11–D03–14
Analog GroundAGND15
Analog Input ChannelsCH0–CH516–21
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01μF capacitor to AGND. Connect
to VDDwhen using an external reference at the REFpin.REFADJ22
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF23
INTgoes low when conversion is complete and output data is ready.INT24
If CSis low, a falling edge on RDwill enable a read operation on the data bus.RD25
Multirange, Single +5V, 12-Bit DASith 12-Bit Bus Interface_______________________________________________________________________________________Acquisition time is calculated as follows:
For 0V to VREF: tAZ= 9 x (RS+ RIN) x 16pF
For 0V to VREF/2: tAZ= 9 x (RS+ RIN) x 32pF
where RIN= 7kΩand tAZis never less than 2μs (0V to
VREFrange) or 3μs (0V to VREF/2 range).
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WRrising edge
and enters its hold mode when it detects the secondrising edge with D5 = 0 (see External Acquisition
section).
Input BandwidthThe ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and ProtectionFigure 4 shows the equivalent input circuit. The full-
scale input voltage depends on the voltage at the refer-
ence (VREF). The MAX196 uses a scaling factor, which
allows input voltage ranges of ±10V, ±5V, 0V to +10V,
or 0V to +5V with a 4.096V voltage reference (Table 1).
Program the desired range by setting the appropriate
control bits (D3, D4) in the control byte (Tables 2 and
3). The MAX198 does not use a scaling factor, so its
input voltage range directly corresponds with the refer-
ence voltage. It can be programmed for input voltages
of ±VREF, ±VREF/2, 0V to VREF, or 0V to VREF/2 (Table
3). When an external reference is applied at REFADJ,
the voltage at REF is given by VREF= 1.6384 x VREFADJ
(2.4V < VREF< 4.18V).
The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with VDD= 0V, the input resistive network provides
current-limiting that adequately protects the device.
Digital InterfaceInput data (control byte) and output data are multi-
plexed on a three-state parallel interface. This parallel
I/O can easily be interfaced with a μP. CS, WR, and RD
control the write and read operations. CSis the stan-
dard chip-select signal, which enables a μP to address
the MAX196/MAX198 as an I/O port. When high, it dis-
ables the WRand RDinputs and forces the interface
into a high-Z state.
DGND
VDD
REF
REFADJ
INT
CH5
CH4
CH3
CH2
CH1
CH0
AGND
4.7mF4.7mF
0.01mF0.01mF
+5V
OUTPUT STATUSmP
CONTROL
INPUTS
CLK
D11
D10
100pFP DATA BUS
ANALOG
INPUTS
MAX196
MAX198
Figure 3. Operational Diagram
5.12k
CH_
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
CHOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kW (MAX196) OR 5.12kW (MAX198)
R2 = 8.67kW (MAX196) OR ¥ (MAX198)
Figure 4. Equivalent Input Circuit
RANGE (V)ZERO SCALE (V)-FULL SCALE+FULL SCALE0 to +50—VREFx 1.2207
0 to +100—VREFx 2.4414—-VREFx 1.2207VREFx 1.2207
±10—-VREFx 2.4414VREFx 2.4414
Table 1. Full Scale and Zero Scale
(MAX196 only)
