MAX19538ETL+T ,12-Bit, 95Msps, 3.3V ADCfeatures a 63µW power-down mode to con-♦ Common-Mode Referenceserve power during idle periods.♦ CMO ..
MAX1953EUB ,Low-Cost / High-Frequency / Current-Mode PWM Buck ControllerApplicationsPrinters and ScannersILIM 1 10 BSTGraphic Cards and Video CardsCOMP 2 9 LXPCs and Serve ..
MAX1953EUB ,Low-Cost / High-Frequency / Current-Mode PWM Buck Controllerapplications where cost and MAX1953size are critical.1MHz Switching FrequencyThe MAX1953 operates ..
MAX1953EUB ,Low-Cost / High-Frequency / Current-Mode PWM Buck ControllerMAX1953/MAX1954/MAX195719-2373; Rev 0; 4/02Low-Cost, High-Frequency, Current-Mode PWMBuck Controller
MAX1953EUB+ ,Low-Cost, High-Frequency, Current-Mode PWM Buck Controllersfeatures a tracking output voltage range of0.4V to 0.86V and is capable of sourcing or sinking ♦ In ..
MAX1953EUB+T ,Low-Cost, High-Frequency, Current-Mode PWM Buck ControllersMAX1953/MAX1954/MAX195719-2373; Rev 0; 4/02Low-Cost, High-Frequency, Current-Mode PWMBuck Controller
MAX490EPA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversFeaturesThe MAX481, MAX483, MAX485, MAX487–MAX491, and' In µMAX Package: Smallest 8-Pin SOMAX1487 a ..
MAX490EPA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversApplications ______________Ordering InformationLow-Power RS-485 TransceiversPART TEMP. RANGE PIN-PA ..
MAX490EPA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversGeneral Description ________
MAX490EPA+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:EMI and reduce reflections caused by improperly termi-MAX3460–MAX3464: +5V, Fail-Safe, ..
MAX490ESA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversApplications ______________Ordering InformationLow-Power RS-485 TransceiversPART TEMP. RANGE PIN-PA ..
MAX490ESA ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX148719-0122; Rev 5; 2/96Low-Power, Slew-Rate-LimitedRS-485/RS ..
MAX19538ETL+T
12-Bit, 95Msps, 3.3V ADC
General DescriptionThe MAX19538 is a 3.3V, 12-bit, 95Msps analog-to-digi-
tal converter (ADC) featuring a fully differential wide-
band track-and-hold (T/H) input amplifier, driving a
low-noise internal quantizer. The analog input accepts
single-ended or differential signals. The MAX19538 is
optimized for low power, small size, and high dynamic
performance. Excellent dynamic performance is main-
tained from baseband to input frequencies of 175MHz
and beyond, making the MAX19538 ideal for intermedi-
ate frequency (IF) sampling applications.
Powered from a single 3.3V supply, the MAX19538 con-
sumes only 492mW while delivering a typical 68.4dB
signal-to-noise ratio (SNR) performance at a 175MHz
input frequency. In addition to low operating power, the
MAX19538 features a 63µW power-down mode to con-
serve power during idle periods.
A flexible reference structure allows the MAX19538 to use
the internal 2.048V bandgap reference or accept an
externally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.10V. The MAX19538 provides a com-
mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX19538 supports either a single-ended or differ-
ential input clock drive. The internal clock duty-cycle
equalizer accepts a wide range of clock duty cycles.
Analog-to-digital conversion results are available
through a 12-bit, parallel, CMOS-compatible output bus.
The digital output format is pin selectable to be either
two’s complement or Gray code. A data-valid indicator
eliminates external components that are normally
required for reliable digital interfacing. A separate digital
power input accepts a wide 1.7V to 3.6V supply allow-
ing the MAX19538 to interface with various logic levels.
The MAX19538 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to
+85°C) temperature range.
See the Pin-CompatibleVersionstable for a complete
family of 14-bit and 12-bit high-speed ADCs.
ApplicationsIF and Baseband Communication Receivers
Cellular, Point-to-Point Microwave, HFC
Medical Imaging Including Positron
Emission Tomography (PET)
Video Imaging
Portable Instrumentation
Low-Power Data Acquisition
FeaturesDirect IF Sampling Up to 400MHzExcellent Dynamic Performance
70.9dB/68.4dB SNR at fIN= 3MHz/175MHz
89.0dBc/76.2dBc SFDR at fIN= 3MHz/175MHz
-71.5dBFS Small-Signal Noise Floor3.3V Low-Power Operation
465mW (Single-Ended Clock Mode)
492mW (Differential Clock Mode)
63µW (Power-Down Mode)Fully Differential or Single-Ended Analog InputAdjustable Full-Scale Analog Input Range: ±0.35V
to ±1.10VCommon-Mode ReferenceCMOS-Compatible Outputs in Two’s Complement
or Gray CodeData-Valid Indicator Simplifies Digital DesignData Out-of-Range IndicatorMiniature 6mm x 6mm x 0.8mm 40-Pin Thin QFN
Package with Exposed PaddleEvaluation Kit Available (Order MAX1211EVKIT)
MAX19538
12-Bit, 95Msps, 3.3V ADC
Ordering Information19-3403; Rev 0; 10/04
Pin Configuration appears at end of data sheet.+Denotes lead-free package.
*All devices are specified over the -40°C to +85°C operating
range.
PART*PIN-PACKAGEPKG CODEMAX19538ETL40 Thin QFNT4066-3
MAX19538ETL+40 Thin QFNT4066-3
PART
SAMPLING
RATE
(Msps)
RESOLUTION
(BITS)
TARGET
APPLICATIONMAX125559514IF/Baseband
MAX125548014IF/Baseband
MAX125536514IF/Baseband
MAX195389512IF/BasebandMAX12098012IF
MAX12116512IF
MAX12088012Baseband
MAX12076512Baseband
MAX12064012Baseband
Pin-Compatible Versions
MAX19538
12-Bit, 95Msps, 3.3V ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +3.6V
OVDDto GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INP, INN to GND...-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN,
COM to GND.....-0.3V to the lower of (VDD+ 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
D11–D0, I.C., DAV,
DOR to GND........................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated
26.3mW/°C above +70°C)......................................2105.3mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)Resolution12Bits
Integral NonlinearityINLfIN = 3MHz-1.7±0.4+1.4LSB
Differential NonlinearityDNLfIN = 3M H z, no m i ssi ng codes over tem per atur e-0.55±0.30+0.95LSB
Offset ErrorVREFIN = 2.048V±0.10±0.58%FS
Gain ErrorVREFIN = 2.048V±0.6±4.9%FS
ANALOG INPUT (INP, INN)Differential Input Voltage RangeVDIFFDifferential or single-ended inputs±1.024V
Common-Mode Input VoltageVDD / 2V
CPARFixed capacitance to ground2Input Capacitance
(Figure 3)CSAMPLESwitched capacitance4.5pF
CONVERSION RATEMaximum Clock FrequencyfCLK95MHz
Minimum Clock Frequency5MHz
Data LatencyFigure 68.5Clock
cycles
DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2)Small-Signal Noise FloorSSNFInput at less than -35dBFS-71.5dBFS
fIN = 3MHz at -0.5dBFS (Note 3)67.270.9
fIN = 70MHz at -0.5dBFS70.4Signal-to-Noise RatioSNR
fIN = 175MHz at -0.5dBFS (Note 3)65.568.4
fIN = 3MHz at -0.5dBFS (Note 3)66.570.8
fIN = 70MHz at -0.5dBFS70.0Signal-to-Noise and DistortionSINAD
fIN = 175MHz at -0.5dBFS (Note 3)63.367.5
MAX19538
12-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfIN = 3MHz at -0.5dBFS (Note 3)73.589.0
fIN = 70MHz at -0.5dBFS83.5Spurious-Free Dynamic RangeSFDR
fIN = 175MHz at -0.5dBFS (Note 3)67.276.2
dBc
fIN = 3MHz at -0.5dBFS (Note 3)-86.3-72.9
fIN = 70MHz at -0.5dBFS-81.2Total Harmonic DistortionTHD
fIN = 175MHz at -0.5dBFS (Note 3)-74.7-66.2
dBc
fIN = 3MHz at -0.5dBFS-92.4
fIN = 70MHz at -0.5dBFS-91.3Second HarmonicHD2
fIN = 175MHz at -0.5dBFS-82.3
dBc
fIN = 3MHz at -0.5dBFS-89.6
fIN = 70MHz at -0.5dBFS-83.7Third HarmonicHD3
fIN = 175MHz at -0.5dBFS-76.2
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS-82.5
Intermodulation DistortionIMD
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS-73.6
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS-84.3
Third-Order IntermodulationIM3
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS-76.0
dBc
fIN1 = 68.5MHz at -7dBFS
fIN2 = 71.5MHz at -7dBFS84.7
Two-Tone Spurious Free
Dynamic RangeSFDRTT
fIN1 = 172.5MHz at -7dBFS
fIN2 = 177.5MHz at -7dBFS75.6
dBc
Aperture DelaytADFigure 41.2ns
Aperture JittertAJFigure 4<0.2psRMS
Output NoisenOUTINP = INN = COM0.36LSBRMS
Overdrive Recovery Time±10% beyond full scale1Clock
cycles
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)REFOUT Output VoltageVREFOUT1.9962.0482.063V
COM Output VoltageVCOMVDD / 21.65V
Differential-Reference Output
VoltageVREFVREF = VREFP - VREFN = VREFIN x 3/41.536V
REFOUT Load Regulation-1.0mA < IREFOUT < 0.1mA35mV/mA
REFOUT Temperature CoefficientTCREF+50ppm/°C
Short to VDD, sinking0.24REFOUT Short-Circuit CurrentShort to GND, sourcing2.1mA
MAX19538
12-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated
internally)REFIN Input VoltageVREFIN2.048V
REFP Output VoltageVREFP(VDD / 2) + (VREFIN x 3/8)2.418V
REFN Output VoltageVREFN(VDD / 2) - (VREFIN x 3/8)0.882V
COM Output VoltageVCOMVDD / 21.601.651.70V
Differential-Reference Output
VoltageVREFVREF = VREFP - VREFN = VREFIN x 3/41.4621.5361.594V
Differential-Reference
Temperature Coefficient±25ppm/°C
REFIN Input Resistance>50MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)COM Input VoltageVCOMVDD / 21.65V
REFP Input VoltageVREFP - VCOM+0.768V
REFN Input VoltageVREFN - VCOM-0.768Vi ffer enti al - Refer ence Inp ut V ol tag eVREFVREF = VREFP - VREFN = VREFIN x 3/41.536V
REFP Sink CurrentIREFPVREFP = 2.418V1.4mA
REFN Source CurrentIREFNVREFN = 0.882V1.0mA
COM Sink CurrentICOMVCOM = 1.65V1.0mA
REFP, REFN Capacitance13pF
COM Capacitance6pF
CLOCK INPUTS (CLKP, CLKN)Single-Ended-Input High
ThresholdVIHCLKTYP = GND, CLKN = GND0.8 x
VDDV
Single-Ended-Input Low
ThresholdVILCLKTYP = GND, CLKN = GND0.2 x
VDDV
Differential Input Voltage SwingCLKTYP = high1.4VP-P
Differential Input Common-Mode
VoltageCLKTYP = highVDD / 2V
Input ResistanceRCLKFigure 55kΩ
Input CapacitanceCCLK2pF
DIGITAL INPUTS (CLKTYP, DCE, G / TTTT , PD)
Input High ThresholdVIH0.8 x
OVDDV
Input Low ThresholdVIL0.2 x
OVDDV
VIH = OVDD±5Input Leakage CurrentVIL = 0±5µA
Input CapacitanceCDIN5pF
MAX19538
12-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL OUTPUTS (D11–D0, DAV, DOR)D11–D0, DOR, ISINK = 200µA0.2Output-Voltage LowVOLDAV, ISINK = 600µA0.2V
D11–D0, DOR, ISOURCE = 200µAOVDD -
Output-Voltage HighVOH
DAV, ISOURCE = 600µAOVDD -
Tri-State Leakage CurrentILEAK(Note 4)±5µA
D11–D0, DOR Tri-State Output
CapacitanceCOUT(Note 4)3pF
DAV Tri-State Output
CapacitanceCDAV(Note 4)6pF
POWER REQUIREMENTSAnalog Supply VoltageVDD3.153.303.60V
Digital Output Supply VoltageOVDD1.71.8VDD +
0.3VV
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,
differential clock
Analog Supply CurrentIVDD
Power-down mode clock idle PD = OVDD0.22
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS CLKTYP = OVDD,
differential clock
Analog Power DissipationPDISS
Power-down mode clock idle PD = OVDD0.063
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CL ≈ 5pF9.9mADigital Output Supply CurrentIOVDD
Power-down mode clock idle PD = OVDD1.0µA
MAX19538
12-Bit, 95Msps, 3.3V ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 95MHz (50% duty cycle), TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS (Figure 6)Clock Pulse-Width HightCH5.26ns
Clock Pulse-Width LowtCL5.26ns
Data-Valid DelaytDAVCL ≈ 5pF (Note 5)6.8ns
Data Setup Time Before Rising
Edge of DAVtSETUPCL ≈ 5pF (Notes 5, 6)5.7ns
Data Hold Time After Rising Edge
of DAVtHOLDCL ≈ 5pF (Notes 5, 6)4.2ns
Wake-Up Time from Power-DowntWAKEVREFIN = 2.048V10ms
Note 1:Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2:See definitions in the Parameter Definitionssection at the end of this data sheet.
Note 3:Limit specifications include performance degradations due to production test socket. Performance is improved when the
MAX19538 is soldered directly to the PC board.
Note 4:During power-down, D11–D0, DOR, and DAV are high impedance.
Note 5:Digital outputs settle to VIHor VIL.
Note 6:Guaranteed by design and characterization.
MAX19538
12-Bit, 95Msps, 3.3V ADC
Typical Operating Characteristics(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)MAX19538 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
HD4
fCLK = 95MHz
fIN = 3.00354004MHz
AIN = -0.519dBFS
SNR = 70.89dB
SINAD = 70.83dB
THD = -89.3dBc
SFDR = 93.6dBc
HD3
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)MAX19538 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
HD2
HD5
fCLK = 95MHz
fIN = 47.30285645MHz
AIN = -0.510dBFS
SNR = 70.80dB
SINAD = 70.41dB
THD = -81.0dBc
SFDR = 83.2dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)MAX19538 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
HD3
HD5
HD2
fCLK = 95MHz
fIN = 69.89318848MHz
AIN = -0.472dBFS
SNR = 70.65dB
SINAD = 70.35dB
THD = -82.1dBc
SFDR = 85.8dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)MAX19538 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
HD3
HD5HD2
fCLK = 95MHz
fIN = 174.8895264MHz
AIN = -0.521dBFS
SNR = 69.02dB
SINAD = 68.19dB
THD = -75.8dBc
SFDR = 76.8dBc
SINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)MAX19538 toc05
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
HD3HD5
HD2
fCLK = 95MHz
fIN = 224.8944092MHz
AIN = -0.531dBFS
SNR = 68.14dB
SINAD = 66.42dB
THD = -71.3dBc
SFDR = 72.4dBc
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)MAX19538 toc06
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
2 × fIN1 + fIN2fIN1 + fIN2
3 × fIN1 + 2 × fIN22 × fIN2 + fIN1
fIN2
fIN1fCLK = 95MHz
fIN1 = 68.50739MHz
AIN1 = -7.0dBFS
fIN2 = 71.51093MHz
AIN2 = -7.0dBFS
SFDRTT = 84.7dB
IMD = -82.4dBc
IM3 = -84.3dBc
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)MAX19538 toc07
FREQUENCY (MHz)
AMPLITUDE (dBFS)403035101520255
2 × fIN1 + fIN2
fIN1 + fIN2
fIN2 - fIN1
2 × fIN2 + fIN1
fIN2
fIN1
fCLK = 95MHz
fIN1 = 172.4716MHz
AIN1 = -7.0dBFS
fIN2 = 177.4698MHz
AIN2 = -7.0dBFS
SFDRTT = 75.5dBc
IMD = -73.6dBc
IM3 = -76.0dBc
INTEGRAL NONLINEARITYMAX19538 toc08
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX19538 toc09
DIGITAL OUTPUT CODE
DNL (LSB)
-1.04096
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
MAX19538
12-Bit, 95Msps, 3.3V ADC
SNR, SINAD vs. SAMPLING RATEMAX19538 toc10
fCLK (MHz)
SNR, SINAD (dB)
SNR
SINAD
fIN = 70MHz
SFDR, -THD vs. SAMPLING RATEMAX19538 toc11
fCLK (MHz)
SFDR, -THD (dBc)
SFDR
-THD
fIN = 70MHz
POWER DISSIPATION
vs. SAMPLING RATEMAX19538 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 70MHz
CL ≈ 5pF
SNR, SINAD vs. SAMPLING RATEMAX19538 toc13
fCLK (MHz)
SNR, SINAD (dB)
SNR
SINAD
fIN = 175MHz
SFDR, -THD
vs. SAMPLING RATEMAX19538 toc14
fCLK (MHz)
SFDR, -THD (dBc)
SFDR
-THD
fIN = 175MHz
POWER DISSIPATION
vs. SAMPLING RATEMAX19538 toc15
fCLK (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG INPUT FREQUENCYMAX19538 toc16
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
SNR
SINAD
fCLK = 95MHz
SFDR, -THD
vs. ANALOG INPUT FREQUENCYMAX19538 toc17
SFDR, -THD (dBc)
ANALOG INPUT FREQUENCY (MHz)
SFDR
-THD
fCLK = 95MHz
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCYMAX19538 toc18
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
CL ≈ 5pF
MAX19538
12-Bit, 95Msps, 3.3V ADC
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
SNR, SINAD
vs. ANALOG INPUT AMPLITUDEMAX19538 toc19
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD (dB)-10-20-15-30-25-35
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. ANALOG INPUT AMPLITUDEMAX19538 toc20
ANALOG INPUT AMPLITUDE (dBFS)
SFDR, -THD (dBc)-10-20-15-30-25-35
fCLK = 95MHz
fIN = 175MHz
SFDR
-THD
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDEMAX19538 toc21
ANALOG INPUT AMPLITUDE (dBFS)
POWER DISSIPATION (mW)-10-15-20-25-30-35
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 96MHz
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG SUPPLY VOLTAGEMAX19538 toc22
VDD (V)
SNR, SINAD (dB)
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. ANALOG SUPPLY VOLTAGEMAX19538 toc23
VDD (V)
SFDR, -THD (dBc)
SFDR
-THD
fCLK = 95MHz
fIN = 175MHz
POWER DISSIPATION
vs. ANALOG SUPPLY VOLTAGEMAX19538 toc24
VDD (V)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
fIN = 175MHz
CL ≈ 5pF
SNR, SINAD
vs. DIGITAL SUPPLY VOLTAGEMAX19538 toc25
OVDD (V)
SNR, SINAD (dB)
SNR
SINAD
fIN = 174.8953247MHz
fCLK = 95MHz
SFDR, -THD
vs. DIGITAL SUPPLY VOLTAGEMAX19538 toc26
SFDR, -THD (dBc)
OVDD (V)
SFDR
-THD
fIN = 174.8953247MHz
fCLK = 95MHz
POWER DISSIPATION
vs. DIGITAL SUPPLY VOLTAGEMAX19538 toc27
OVDD (V)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN = 175.8953247MHz
fIN = 95MHz
CL ≈ 5pF
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
MAX19538
12-Bit, 95Msps, 3.3V ADC
SNR, SINAD
vs. TEMPERATUREMAX19538 toc28
TEMPERATURE (°C)
SNR, SINAD (dB)3510-15
SNR
SINAD
fCLK = 95MHz
fIN = 175MHz
SFDR, -THD
vs. TEMPERATUREMAX19538 toc29
TEMPERATURE (°C)
SFDR, -THD (dBc)35-1510
SFDR
-THD
fCLK = 95MHz
fIN = 175MHz
POWER DISSIPATION
vs. TEMPERATUREMAX19538 toc30
TEMPERATURE (°C)
ANALOG POWER DISSIPATION (mW)3510-15
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 95MHz
fIN = 175MHz
CL ≈ 5pF
OFFSET ERROR
vs. TEMPERATUREMAX19538 toc31
TEMPERATURE (°C)
OFFSET ERROR (%FS)3510-15
VREFIN = 2.048V
GAIN ERROR
vs. TEMPERATUREMAX19538 toc32
TEMPERATURE (°C)
GAIN ERROR (%FS)3510-15
VREFIN = 2.048V
MAX19538
12-Bit, 95Msps, 3.3V ADC
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 1.8V, GND = 0, REFIN = REFOUT (internal reference), VIN= -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK≈95MHz (50% duty cycle), TA= +25°C, unless otherwise noted.
REFERENCE OUTPUT VOLTAGE
LOAD REGULATIONMAX19538 toc33
IREFOUT SINK CURRENT (mA)
REFOUT
(V)-0.5-1.0-1.5
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCEMAX19538 toc34
IREFOUT SINK CURRENT (mA)
REFOUT
(V)-1.0-2.0
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATUREMAX19538 toc35
TEMPERATURE (°C)
REFOUT
(V)3510-15
REFP, COM, REFN
LOAD REGULATION
MAX19538 toc36
SINK CURRENT (mA)
VOLTAGE (V)0-1
INTERNAL REFERENCE MODE AND
BUFFERED EXTERNAL REFERENCE MODE.
VREFP
VREFN
VCOM
REFP, COM, REFN
SHORT-CIRCUIT PERFORMANCEMAX19538 toc37
SINK CURRENT (mA)
VOLTAGE (V)40-4
INTERNAL REFERENCE MODE
AND BUFFERED EXTERNAL
REFERENCE MODE.
VREFP
VREFN
VCOM
MAX19538
12-Bit, 95Msps, 3.3V ADC
Pin Description
PINNAMEFUNCTIONREFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFP to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the
same side of the PC board.REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN) x 2/3. Bypass REFN to
GND with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP
and REFN. Place the 1µF REFP-to-REFN capacitor as close to the device as possible on the
same side of the PC board.COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM-to-
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on theopposite side of the PC board and connected to the MAX19538 through a via.
4, 7, 16, 35GNDGround. Connect all ground pins and EP together.INPPositive Analog InputINNNegative Analog InputDCEDuty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the
differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND),
apply the single-ended clock signal to CLKP and connect CLKN to GND.CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the
differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND),
apply the single-ended clock signal to CLKP and connect CLKN to GND.CLKTYPClock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input.
Connect CLKTYP to OVDD or VDD to define the differential clock input.
12–15, 36VDDAnalog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34OVDDOutput-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with
a parallel capacitor combination of ≥2.2µF and 0.1µF.DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the
analog input is within its full-scale range (Figure 6).D11CMOS Digital Output, Bit 11 (MSB)D10CMOS Digital Output, Bit 10D9CMOS Digital Output, Bit 9D8CMOS Digital Output, Bit 8D7CMOS Digital Output, Bit 7D6CMOS Digital Output, Bit 6D5CMOS Digital Output, Bit 5D4CMOS Digital Output, Bit 4D3CMOS Digital Output, Bit 3D2CMOS Digital Output, Bit 2
MAX19538
12-Bit, 95Msps, 3.3V ADCFigure1. Pipeline Architecture—Stage Blocks
MAX19538Σ+
DIGITAL ERROR CORRECTION
FLASH
ADC
T/H
DAC
STAGE 2
D11–D0
INP
INNSTAGE 1T/HSTAGE 9STAGE 10
END OF PIPE
OUTPUT
DRIVERS
D11–D0
Figure 2. Simplified Functional Diagram
MAX19538
INP
INN
12-BIT
PIPELINE
ADCDEC
REFERENCE
SYSTEMCOM
REFOUT
REFN
REFP
OVDD
DAVOUTPUT
DRIVERS
D11–D0
DOR
REFIN
T/H
POWER CONTROL
AND
BIAS CIRCUITS
CLKPCLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKN
CLKTYP
VDD
GND
DCE
G/T
Pin Description (continued)
PINNAMEFUNCTIOND1CMOS Digital Output, Bit 1D0CMOS Digital Output, Bit 0 (LSB)
31, 32I.C.Internally Connected. Leave I.C. unconnected.DAV
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX19538 output data into an
external back-end digital circuit.PDPower-Down Input. Force PD high for power-down mode. Force PD low for normal operation.REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to
REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND
with a ≥0.1µF capacitor.REFIN
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes VREFP - VREFN = VREFIN x 3/4. For unbuffered external
reference mode operation, connect REFIN to GND.G/ TOutput-Format-Select Input. Connect G/ T to GND for the two’s-complement digital output format.
Connect G/ T to OVDD or VDD for the Gray-code digital output format.
—EP
Exposed Paddle. The MAX19538 relies on the exposed paddle connection for a low-inductance
ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to
connect the top-side PC board ground plane to the bottom-side PC board ground plane.
Detailed DescriptionThe MAX19538 uses a 10-stage, fully differential,
pipelined architecture (Figure1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every half clock cycle. From input to
output, the total clock-cycle latency is 8.5 clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure2 shows the
MAX19538 functional diagram.
MAX19538
12-Bit, 95Msps, 3.3V ADC
Input Track-and-Hold (T/H) CircuitFigure3 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit. This input T/H circuit
allows for high analog input frequencies of 175MHz
and beyond and supports a VDD / 2 ±0.5V common-
mode input voltage.
The MAX19538 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure3), allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and they are open
(hold) when the sampling clock is low (Figure4). The
analog input signal source must be capable of provid-
ing the dynamic current necessary to charge and dis-
charge the sampling capacitors. To avoid signal degra-
dation, these capacitors must be charged to 1/2 LSB
accuracy within one half of a clock cycle.
The analog input of the MAX19538 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (VDD / 2). The MAX19538 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures10, 11, and 12.
Reference Output (REFOUT) An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX19538. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX19538 or when PD transitions from
high to low. REFOUT has approximately 17kΩto GND
when the MAX19538 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUTto be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
REFOUT sources up to 1.0mAand sinks up to 0.1mA
for external circuits with a load regulation of 35mV/mA.
Short-circuit protection limits IREFOUTto a 2.1mA
source current when shorted to GND and a 0.24mA
sink current when shorted to VDD.
Figure3. Simplified Input Track-and-Hold Circuit
MAX19538
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INP
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
4.5pF
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INN
*CSAMPLE
4.5pF
RSAMPLE =1
fCLK x CSAMPLE
Figure 4. T/H Aperture Timing
tAD
T/H
CLKN
CLKP
tAJ
TRACKHOLDTRACKHOLDTRACKHOLDTRACKHOLD
ANALOG
INPUT
SAMPLED
DATA
