MAX194ACWE ,14-Bit, 85ksps ADC with 10A ShutdownMAX19419-0345; Rev 4; 12/9714-Bit, 85ksps ADC with 10µA Shutdown_______________
MAX194BCPE ,14-Bit, 85ksps ADC with 10A ShutdownELECTRICAL CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f = 1.7MHz, V = +5V, T = T to T , ..
MAX194BCPE+ ,14-Bit, 85ksps ADC with 10µA ShutdownApplicationsMAX194AMDE -55°C to +125°C 16 Ceramic SBPortable Instruments Audio MAX194BMDE -55°C to ..
MAX194BCWE ,14-Bit, 85ksps ADC with 10A ShutdownApplicationsMAX194AMDE -55°C to +125°C 16 Ceramic SBPortable Instruments Audio MAX194BMDE -55°C to ..
MAX194BCWE+ ,14-Bit, 85ksps ADC with 10µA ShutdownMAX19419-0345; Rev 4; 12/9714-Bit, 85ksps ADC w ith 10μA Shutdow n_______________
MAX194BEPE+ ,14-Bit, 85ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, f = 1.7MHz, V = +5V, T = T to T , ..
MAX490ECPA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversMAX481E/MAX483E/MAX485E/MAX487E–MAX491E/MAX1487E19-0410; Rev 3; 7/96±15kV ESD-Protected, Slew-Rate- ..
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MAX490ECPA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversApplicationsMAX481EESA -40°C to +85°C 8 SOLow-Power RS-485 TransceiversOrdering Information continu ..
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MAX490ECSA ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 Transceiversapplications. For
MAX194ACPE-MAX194ACWE-MAX194BCPE-MAX194BCWE
14-Bit, 85ksps ADC with 10A Shutdown
_______________General DescriptionThe MAX194 is a 14-bit successive-approximation ana-
log-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry cor-
rects linearity and offset errors to maintain the full rated
performance over the operating temperature range
without external adjustments. The capacitive-DAC
architecture provides an inherent 85ksps track/hold
function.
The MAX194, with an external reference (up to +5V),
offers a unipolar (0V to VREF) or bipolar (-VREFto VREF)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state seri-
al-data output. The output can be read either during
conversion as the bits are determined, or following con-
version at up to 5Mbps using the serial clock (SCLK).
The end-of-conversion (EOC) output can be used to
interrupt a processor, or can be connected directly to
the convert input (CONV) for continuous, full-speed
conversions.
The MAX194 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages. The output data format
provides pin-for-pin and functional compatibility with
the 16-bit MAX195 ADC.
________________________ApplicationsPortable InstrumentsAudio
Industrial ControlsRobotics
Multiple Transducer Medical Signal
MeasurementsAcquisition
Vibrations AnalysisDigital Signal
Processing
____________________________FeaturesTrue 14-Bit Accuracy: 1⁄2LSB INL
82dB SINAD9.4µs Conversion Time10µA Shutdown ModeBuilt-In Track/HoldAC and DC SpecifiedUnipolar (0V to VREF) and Bipolar (-VREFto VREF)
Input RangeThree-State Serial-Data OutputSmall 16-Pin DIP, SO, and Ceramic SB PackagesPin-Compatible 16-Bit Upgrade (MAX195)
______________Ordering Information
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
________________Functional Diagram
__________________Pin Configuration
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDD to DGND.....................................................................+7V
VDDA to AGND......................................................................+7V
VSSD to DGND.........................................................+0.3V to -6V
VSSA to AGND.........................................................+0.3V to -6V
VDDD to VDDA, VSSD to VSSA..........................................±0.3V
AIN, REF....................................(VSSA - 0.3V) to (VDDA + 0.3V)
AGND to DGND..................................................................±0.3V
Digital Inputs to DGND...............................-0.3V, (VDDA + 0.3V)
Digital Outputs to DGND............................-0.3V, (VDDA + 0.3V)
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C)............842mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
Ceramic SB (derate 10.53mW/°C above +70°C)...........842mW
Operating Temperature Ranges
MAX194_C_E........................................................0°C to +70°C
MAX194_E_E.....................................................-40°C to +85°C
MAX194_MDE..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
ELECTRICAL CHARACTERISTICS (continued)(VDDD = VDDA = +5V, VSSD = VSSA = -5V, fCLK= 1.7MHz, VREF= +5V, TA= TMINto TMAX, unless otherwise noted. Typical
values are at TA= +25°C.)
TIMING CHARACTERISTICS(VDDD = VDDA = +5V, VSSD = VSSA = -5V, unless otherwise noted.)
Note 1:Accuracy and dynamic performance tests performed after calibration.
Note 2:Tested with 50% duty cycle. Duty cycles from 25% to 75% at 1.7MHz are acceptable.
Note 3:See External Clocksection.
Note 4:Guaranteed by design, not tested.
Note 5:Measured in shutdown mode with CLK and SCLK low.
Note 6:Settling time required after deasserting shutdown to achieve less than 0.1LSB additional error.
_______________Detailed DescriptionThe MAX194 uses a successive-approximation register
(SAR) to convert an analog input to a 14-bit digital
code, which outputs as a serial data stream. The data
bits can be read either during the conversion, at the
CLK clock rate, or between conversions asynchronous
with CLK, at the SCLK rate (up to 5Mbps).
The MAX194 includes a capacitive digital-to-analog
converter (DAC) that provides an inherent track/hold
input. The interface and control logic are designed for
easy connection to most microprocessors (µPs), limiting
the need for external components. In addition to the
SAR and DAC, the MAX194 includes a serial interface, a
sampling comparator used by the SAR, ten calibration
DACs, and control logic for calibration and conversion.
The DAC consists of an array of capacitors with binary
weighted values plus one “dummy sub-LSB” capacitor
(Figure 1). During input acquisition in unipolar mode,
the array’s common terminal is connected to AGND
and all free terminals are connected to the input signal
(AIN). After acquisition, the common terminal is discon-
nected from AGND and the free terminals are discon-
nected from AIN, trapping a charge proportional to the
input voltage on the capacitor array.
The free terminal of the MSB (largest) capacitor is con-
nected to the reference (REF), which pulls the common
terminal (connected to the comparator) positive.
Simultaneously, the free terminals of all other capaci-
tors in the array are connected to AGND, which drives
the comparator input negative. If the analog input is
near VREF, connecting the MSB’s free terminal to REF
only pulls the comparator input slightly positive.
However, connecting the remaining capacitor’s free ter-
minals to ground drives the comparator input well
below ground, so that the comparator input is negative,
the comparator output is low, and the MSB is set high.
If the analog input is near ground, the comparator out-
put is high and the MSB is low.
Following this, the next largest capacitor is disconnect-
ed from AGND and connected to REF, and the com-
parator determines the next bit. This continues until all
bits have been determined. For a bipolar input range,
the MSB capacitor is connected to REF rather than AIN
during input acquisition, which results in an input range
of VREFto -VREF.
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
______________________________________________________________Pin Description
MAX194
CalibrationIn an ideal DAC, each of the capacitors associated with
the data bits would be exactly twice the value of the
next smaller capacitor. In practice, this results in a
range of values too wide to be realized in an economi-
cally feasible size. The capacitor array actually consists
of two arrays, which are capacitively coupled to reduce
the LSB array’s effective value. The capacitors in the
MSB array are production trimmed to reduce errors.
Small variations in the LSB capacitors contribute
insignificant errors to the 14-bit result.
Unfortunately, trimming alone does not yield 14-bit per-
formance or compensate for changes in performance
due to changes in temperature, supply voltage, and
other parameters. For this reason, the MAX194 includes
a calibration DAC for each capacitor in the MSB array.
These DACs are capacitively coupled to the main DAC
output and offset the main DAC’s output according to
the value on their digital inputs. During calibration, the
correct digital code to compensate for the error in each
MSB capacitor is determined and stored. Thereafter,
the stored code is input to the appropriate calibration
DAC whenever the corresponding bit in the main DAC
is high, compensating for errors in the associated
capacitor.
The MAX194 calibrates automatically on power-up. To
reduce the effects of noise, each calibration experiment
is performed many times and the results are averaged.
Calibration requires about 14,000 clock cycles, or
8.2ms at the highest clock (CLK) speed (1.7MHz). In
addition to the power-up calibration, bringing RESET
low halts MAX194 operation, and bringing it high again
initiates a calibration (Figure 2).
14-Bit, 85ksps ADC with 10µA ShutdownFigure 1. Capacitor DAC Functional Diagram
Figure 2. Initiating Calibration
If the power supplies do not settle within the MAX194’s
power-on delay (500ns minimum), power-up calibration
may begin with supply voltages that differ from the final
values and the converter may not be properly calibrat-
ed. If so, recalibrate the converter (pulse RESETlow)
before use. For best DC accuracy, calibrate the
MAX194 any time there is a significant change in sup-
ply voltages, temperature, reference voltage, or clock
characteristics (see External Clocksection) because
these parameters affect the DC offset. If linearity is the
only concern, much larger changes in these parame-
ters can be tolerated.
Because the calibration data is stored digitally, there is
no need either to perform frequent conversions to main-
tain accuracy or to recalibrate if the MAX194 has been
held in shutdown for long periods. However, recalibra-
tion is recommended if it is likely that supply voltages or
ambient temperature has significantly changed since
the previous calibration.
Digital InterfaceThe digital interface pins consist of BP/UP/SHDN, CLK,
SCLK, EOC, CS, CONV, and RESET.
BP/UP/SHDNis a three-level input. Leave it floating to
configure the MAX194’s analog input in bipolar mode
(AIN = -VREFto VREF) or connect it high for a unipolar
input (AIN = 0V to VREF). Bringing BP/UP/SHDNlow
places the MAX194 in its 10µA shutdown mode.
A logic low on RESEThalts MAX194 operation. The ris-
ing edge of RESETinitiates calibration as described in
the Calibrationsection above.
Begin a conversion by bringing CONVlow. The convert
signal must be synchronized with CLK. The falling edge
of CONVmust occur during the period shown in
Figures 3 and 4. When CLK is not directly controlled by
your processor, two methods of ensuring synchroniza-
tion are to drive CONVfrom EOC(continuous conver-
sions) or to gate the conversion-start signal with the
conversion clock so that CONVcan go low only while
CLK is low (Figure 5). Ensure that the maximum propa-
gation delay through the gate is less than 40ns.
The MAX194 automatically ensures four CLK periods
for track/hold acquisition. If, when CONVis asserted, at
least three clock (CLK) cycles have passed since the
end of the previous conversion, a conversion will begin
on CLK’s next falling edge and EOCwill go high on the
following falling CLK edge (Figure 3). After conversion
begins, additional convert start pulses are ignored. If,
when convert is asserted, less than three clock cycles
have passed, a conversion will begin on the fourth
falling clock edge after the end of the previous conver-
MAX194
14-Bit, 85ksps ADC with 10µA ShutdownFigure 3. Initiating Conversions—At least 3 CLK cycles since end of previous conversion.
MAX194sion and EOCwill go high on the following CLK falling
edge (Figure 4). CONVis ignored during conversions.
External ClockThe conversion clock (CLK) should have a duty cycle
between 25% and 75% at 1.7MHz (the maximum clock
frequency). For lower frequency clocks, ensure the
minimum high and low times exceed 150ns. The mini-
mum clock rate for accurate conversion is 125Hz for
temperatures up to +70°C or 1kHz at +125°C due to
leakage of the sampling capacitor array. In addition,
CLK should not remain high longer than 50ms at tem-
peratures up to +70°C or 500µs at +125°C. If CLK is
held high longer than this, RESETmust be pulsed low
to initiate a recalibration because it is possible that
state information stored in internal dynamic memory
may be lost. The MAX194’s clock can be stopped
indefinitely if it is held low.
If the frequency, duty cycle, or other aspects of the
clock signal’s shape change, the offset created by cou-
pling between CLK and the analog inputs (AIN and
REF) changes. Recalibration corrects for this offset and
restores DC accuracy.
Output DataThe conversion result is clocked out MSB first, format-
ted as 14 data bits plus two sub-LSBs. Serial data is
available on DOUT only when CSis held low.
Otherwise, DOUT is in a high-impedance state. There
are two ways to read the data on DOUT. To read the
data bits as they are determined (at the CLK clock
rate), hold CSlow during the conversion. To read
results between conversions, hold CSlow and clock
SCLK at up to 5MHz.
If you read the serial data bits as they are determined
(at the conversion-clock rate), EOCframes the data bits
(Figure 6). Conversion begins with the first falling CLK
edge, after CONVgoes low and the input signal has
been acquired. Data bits are shifted out of DOUT on
subsequent falling CLK edges. Clock data in on CLK’s
rising edge or, if the clock speed is greater than 1MHz,
on the following falling edge of CLK to meet the maxi-
mum CLK-to-DOUT timing specification. See the
Operating Modes and SPI™/QSPI™ Interfacessection
for additional information. Reading the serial data dur-
ing the conversion results in the maximum conversion
throughput, because a new conversion can begin
immediately after the input acquisition period following
the previous conversion.
14-Bit, 85ksps ADC with 10µA ShutdownFigure 4. Initiating Conversions—Less than 3 CLK cycles since end of previous conversion.
SPI/QSPI are trademarks of Motorola Corp.
If you read the data bits between conversions, you can
1) count CLK cycles until the end of the conversion, or
2) poll EOCto determine when the conversion is
finished, or
3) generate an interrupt on EOC’s falling edge.
Note that the MSBconversion result appears at DOUT
after CSgoes low but beforethe first SCLK pulse. Each
subsequent SCLK pulse shifts out the next conversion
bit. The 15th SCLK pulse shifts out the sub-LSB (S0).
Additional clock pulses shift out zeros.
Data is clocked out on SCLK’s falling edge. Clock data
in on SCLK’s rising edge or, for clock speeds above
2.5MHz, on the following falling edge to meet the maxi-
mum SCLK-to-DOUT timing specification (Figure 7).
The maximum SCLK speed is 5MHz. See the Operating
Modes and SPI/QSPI Interfacessection for additional
information. When the conversion clock is near its maxi-
MAX194
14-Bit, 85ksps ADC with 10µA ShutdownFigure 5. Gating CONVto Synchronize with CLK
Figure 6. Output Data Format, Reading Data During Conversion (Mode 1)
MAX194mum (1.7MHz), reading the data after each conversion
(during the acquisition time) results in lower throughput
(about 70ksps max) than reading the data during con-
versions, because it takes longer than the minimum
input acquisition time (four cycles at 1.7MHz) to clock
16 data bits at 5Mbps. After the data has been clocked
in, leave some time (about 1µs) for any coupled noise
on AIN to settle before beginning the next conversion.
Whichever method is chosen for reading the data, con-
versions can be individually initiated by bringing CONV
low, or they can occur continuously by connecting EOC
to CONV. Figure 8 shows the MAX194 in its simplest
operational configuration.
14-Bit, 85ksps ADC with 10µA ShutdownFigure 7. Output Data Format, Reading Data Between Conversions (Mode 2)
Figure 8. MAX194 in the Simplest Operating Configuration
MAX194
14-Bit, 85ksps ADC with 10µA ShutdownFigure 9. Ratiometric Measurement Without an Accurate Reference
Table 1. Low-ESR Capacitor Suppliers
__________Applications Information
ReferenceThe MAX194 reference voltage range is 0V to VDDA.
When choosing the reference voltage, the MAX194’s
equivalent input noise (40µVRMSin unipolar mode,
80µVRMSin bipolar mode) should be considered. Also, if
VREFexceeds VDDA, errors will occur due to the internal
protection diodes that will begin to conduct, so use cau-
tion when using a reference near VDDA (unless VREF
and VDDA are virtually identical). VREFmust never
exceed its absolute maximum rating (VDDA + 0.3V).
The MAX194 needs a good reference to achieve its
rated performance. The most important requirement is
that the reference must present a low impedance to the
REF input. This is often achieved by buffering the refer-
ence through an op amp and bypassing the REF input
with a large (1µF to 47µF), low-ESR capacitor in parallel
with a 0.1µF ceramic capacitor. Low-ESR capacitors
are available from the manufacturers listed in Table 1.
The reference must drive the main conversion DAC
capacitors as well as the capacitors in the calibration
DACs, all of which may be switching between GND and
REF at the conversion clock frequency. The total
capacitive load presented can exceed 1000pF and,
unlike the analog input (AIN), REF is sampled continu-
ously throughout the conversion.
The first step in choosing a reference circuit is to
decide what kind of performance is required. This often
suggests compromises made in the interests of cost
and size. It is possible that a system may not require an
accurate reference at all. If a system makes a ratiomet-
ric measurement such as Figure 9’s bridge circuit, any
relatively noise-free voltage that presents a low imped-
ance at the REF input will serve as a reference. The
+5V analog supply suffices if you use a large, low-
impedance bypass capacitor to keep REF stable dur-
ing switching of the capacitor arrays. Do not place a
resistance between the +5V supply and the bypass
capacitor, because it will cause linearity errors due to
the dynamic REF input current, which typically ranges
from 300µA to 400µA.
Figure 10 shows a more typical scheme that provides
good AC accuracy. The MAX874’s initial accuracy can
MAX194be improved by trimming, but the drift is too great to
provide good stability over temperature. The MAX427
buffer provides the necessary drive current to stabilize
the REF input quickly after capacitance changes.
The reference inaccuracies contribute additional full-
scale error. A reference with less than 1⁄214total error
(61 parts per million) over the operating temperature
range is required to maintain full 14-bit accuracy. The
MAX6241 achieves a drift specification of 1ppm/°C
(typ) and easily drives the REF input directly. This
allows large temperature changes with less than 1LSB
error. While the MAX6241’s initial-accuracy specifica-
tion (0.02%) results in a maximum error of about
±4LSB, the reference voltage can be trimmed or the
offset can be corrected in software if absoluteDC
accuracy is essential. Figure 11’s circuit provides out-
standing temperature stability and also provides excel-
lent DC accuracy if the initial error is corrected.
14-Bit, 85ksps ADC with 10µA ShutdownFigure 10. Typical Reference Circuit for AC Accuracy
Figure 11. High-Accuracy Reference
