MAX1932ETC+T ,Digitally Controlled, 0.5% Accurate, Safest APD Bias SupplyElectrical Characteristics(V = 3.3V, CS = SCLK = D = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, T ..
MAX1935ETA ,500mA, Low-Voltage Linear Regulator in Tiny QFNApplications 8 Thin QFNMAX1935ETA* -40°C to +85°CNotebook Computers3mm x 3mmCellular and Cordless T ..
MAX1935ETA ,500mA, Low-Voltage Linear Regulator in Tiny QFNFeaturesThe MAX1935 low-dropout linear regulator operates Guaranteed 500mA Output Currentfrom a 2. ..
MAX1935ETA ,500mA, Low-Voltage Linear Regulator in Tiny QFNELECTRICAL CHARACTERISTICS(V = V + 500mV or V = 2.25V whichever is greater, SET = GND, SHDN = IN, T ..
MAX1935ETA+ ,500mA, Low-Voltage Linear Regulator in Tiny QFNELECTRICAL CHARACTERISTICS(V = V + 500mV or V = 2.25V whichever is greater, SET = GND, SHDN = IN, T ..
MAX1935ETA+T ,500mA, Low-Voltage Linear Regulator in Tiny QFNApplications 8 Thin QFNMAX1935ETA* -40°C to +85°CNotebook Computers3mm x 3mmCellular and Cordless T ..
MAX489EESD ,【15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversMAX481E/MAX483E/MAX485E/MAX487E–MAX491E/MAX1487E19-0410; Rev 3; 7/96±15kV ESD-Protected, Slew-Rate- ..
MAX489EESD+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplicationsMAX481EESA -40°C to +85°C 8 SOIndustrial-Control Local Area Networks MAX483ECPA 0°C to ..
MAX489EESD+T ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:state. The receiver input has a fail-safe feature that guar-MAX3440E–MAX3444E: ±15kV E ..
MAX489EPD ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX489EPD+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:EMI and reduce reflections caused by improperly termi-MAX3460–MAX3464: +5V, Fail-Safe, ..
MAX489ESD ,Low-Power / Slew-Rate-Limited RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX148719-0122; Rev 5; 2/96Low-Power, Slew-Rate-LimitedRS-485/RS ..
MAX1932ETC+T
Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias SupplyEVALUATION KIT AVAILABLE
General DescriptionThe MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.
The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy cali-
bration of the APD operating point by indicating the pre-
cise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.
The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applica-
tions that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.
ApplicationsOptical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply
Benefits and FeaturesUnique Architecture Delivers Excellent Accuracy for
Improved System Performance0.5% Accurate OutputLow Ripple Output (< 1mV)
Protection Features Guarantee Safe OperationAccurate High-Side Current LimitAvalanche Indicator Flag
Output-Voltage Flexibility Facilitates Multiple
Applications and Design Approaches4.5V to 90V OutputSet Output Voltage via 8-Bit SPI-Compatible
Internal DAC, External DAC, or External Resistors
Small Circuit Footprint Reduces Equipment Size12-Pin, 4mm x 4mm Thin QFN PackageCircuit Height < 2mm
Commonly Available 2.7V to 5.5V Input Voltage
Range
Ordering InformationPART TEMP RANGE PIN-PACKAGEMAX1932ETC-40°C to +85°C12 Thin QFN
MAX1932
INPUT
2.7V TO 5.5V
APD BIAS OUTPUT
4.5V TO 90V
DAC INPUTS
AVALANCHE
INDICATOR
FLAG
VIN
COMP
SCLK
GNDFB
CS-
CS+
GATE
DACOUT
DIN
Typical Application CircuitMAX19321056
SCLKGND
COMP
CS+
CS-
DACOUT
VIN
DIN
Pin Configuration
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Absolute Maximum Ratings
Electrical Characteristics(VIN= 3.3V, CS= SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA
= 0°C to +85°C, unless otherwise noted.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VIN to GND...............................................................-0.3V to +6V
DIN, SCLK, CS, FB to GND......................................-0.3V to +6V
COMP, DACOUT, GATE, CLto GND...........-0.3V to (VIN+0.3V)
CS+, CS- to GND.................................................-0.3V to +110V
Continuous Power Dissipation (TA= +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C).1349mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERALInput Supply RangeVIN2.75.5V
VIN Undervoltage LockoutUVLOBoth rise/fall, hysteresis = 100mV2.12.6V
Operating Supply CurrentIIN0.51mA
VIN Shutdown Supply CurrentISHDN00 hex loaded to DAC2565µA
Input Resistance for CS+/CS-Resistance from either pin to ground0.512.0MΩ
Current-Limit Threshold
for CS+/CS-1.802.002.20V
Common-Mode Rejection
of Current ThresholdCS+ = 3V to 100V±0.005%/V
Gate-Driver ResistanceGate high or low, IGATE = ±50mA510Ω
FB Input Bias Current-25+25nA
TA = +25°C1.243751.25001.25625FB VoltageVFBTA = 0°C to +85°C1.242501.25001.25750V
FB Voltage
Temperature CoefficientTCVFB0.0007%/°C
FB to COMP TransconductanceCOMP = 1.5V50110200µS
COMP Pulldown Resistance
in ShutdownDAC code = 00 hex100ΩAC OU T to FB V ol tag e D i ffer enceDAC code = FF hex-3+3mVAC OU T Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex,
DAC guaranteed monotonic-1+1LSBAC OU T Voltage Temperature
CoefficientTCVDACOUT0.0007%/°C
DACOUT Load RegulationDAC code = 0F to FF hex, source or sink
50µA-1+1mV
Switching FrequencyfOSC250300340kHz
GATE Maximum On-TimetON3µs
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Electrical Characteristics (continued)(VIN= 3.3V, CS= SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA
= 0°C to +85°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (DIN, SCLK, CS)Input Low Voltage0.6V
Input High Voltage1.4V
Input Hysteresis200mV
TA = +25°C-1+1µAInput Leakage CurrentTA = 0°C to +85°C10nA
Input Capacitance5pF
DIGITAL OUTPUT (CL)Output Low VoltageISINK = 1mA0.1V
Output High VoltageISOURCE = 0.5mAVIN - 0.5V
SPI TIMING (FIGURE 5)SCLK Clock FrequencyfSCLK2MHz
SCLK Low PeriodtCL125ns
SCLK High PeriodtCH125ns
Data Hold TimetDH0ns
Data Setup TimetDS125ns
CS Assertion to SCLK
Rising Edge Setup TimetCSS0200ns
CS Deassertion to SCLK
Rising Edge Setup TimetCSS1200ns
SCLK Rising Edge
to CS DeassertiontCSH1200ns
SCLK Rising Edge
to CS AssertiontCSH0200ns
CS High PeriodtCSW300ns
Electrical Characteristics(VIN= 3.3V, CS= SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERALInput Supply RangeVIN2.75.5V
VIN Undervoltage LockoutUVLOBoth rise/fall, hysteresis = 100mV2.12.6V
Operating Supply CurrentIIN1mA
VIN Shutdown Supply CurrentISHDN00 hex loaded to DAC65µA
Input Resistance for CS+/CS-Resistance from either pin to ground0.52MΩ
Current-Limit Threshold
for CS+/CS-1.802.20V
Gate-Driver ResistanceGate high or low, IGATE = ±50mA10Ω
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Note 1:DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2:Specifications to -40°C are guaranteed by design and not production tested.
Electrical Characteristics (continued)(VIN= 3.3V, CS= SCLK = DIN= 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFB VoltageVFB1.238751.26125V
FB to COMP TransconductanceCOMP = 1.5V50200µS
COMP Pulldown Resistance
in ShutdownDAC code = 00 hex100ΩAC OU T to FB V ol tag e D i ffer enceDAC code = FF hex-4+4mVAC OU T Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex, DAC
guaranteed monotonic-1+1LSBAC OU T Load RegulationDAC code = 0F to FF hex, source or sink
50µA-1+1mV
Switching FrequencyfOSC240360kHz
DIGITAL INPUTS (DIN, SCLK, CS)Input Low Voltage0.6V
Input High Voltage1.4V
DIGITAL OUTPUT (CL)Output Low VoltageISINK = 1mA0.1V
Output High VoltageISOURCE = 0.5mAVIN - 0.5V
SPI TIMING (FIGURE 5)SCLK Clock FrequencyfSCLK2MHz
SCLK Low PeriodtCL125ns
SCLK High PeriodtCH125ns
Data Hold TimetDH0ns
Data Setup TimetDS125ns
CS Assertion to SCLK
Rising Edge Setup TimetCSS0200ns
CS Deassertion to SCLK
Rising Edge Setup TimetCSS1200ns
SCLK Rising Edge
to CS DeassertiontCSH1200ns
SCLK Rising Edge
to CS AssertiontCSH0200ns
CS High PeriodtCSW300ns
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
SWITCHING WAVEFORMSMAX1932 toc01
1μs/div
0.05A/div
50V/div
0.002V/div
VLX
VOUT RIPPLE (AC-COUPLED)
VOUT = 90V
SWITCHING WAVEFORM WITH LC FILTERMAX1932 toc02
1μs/div
0.05A/div
50V/div
0.002V/div
VLX
VOUT RIPPLE (AC-COUPLED)
VOUT = 90V, L = 300μH, C = 1μF, FIGURE 7
STARTUP AND SHUTDOWN WAVEFORMSMAX1932 toc03
20ms/div
50mA/div
50V/div
INPUT
CURRENT
OUTPUT
VOLTAGE
OUTPUT VOLTAGE vs. INPUT VOLTAGEMAX1932 toc04
INPUT VOLTAGE (V)
VFB vs. TEMPERATURE
MAX1932 toc05
TEMPERATURE (°C)60-40-200204060100
OUTPUT VOLTAGE vs. LOAD CURRENTMAX1932 toc06
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
CURRENT LIMIT
ACTIVATED
VCC = 5V, INDUCTOR = 100μH,
R1 = 806Ω
FEEDBACK DIVIDER CURRENT AND CS-
CURRENT INCLUDED
OUTPUT VOLTAGE STEP-DOWN
DUE TO DAC CHANGEMAX1932 toc07
10ms/div
1V/div
OFFSET = 62.962V = 88 hex
STEP DOWN FROM 80 hex TO 88 hex
OUTPUT VOLTAGE STEP-UP
DUE TO DAC CHANGEMAX1932 toc08
10ms/div
1V/div
OFFSET = 62.962V = 88 hex
STEP VALUE = 64.233 = 80 hex
OUTPUT VOLTAGE STEP
DUE TO DACOUT CHANGEMAX1932 toc09
20ms/div
20V/div
0.5V/div
DACOUT EXTERNAL SOURCE
Typical Operating Characteristics(VIN= 5V, Circuit of Figure 2, TA=+25°C, unless otherwise noted)
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Detailed Description
Fixed Frequency PWMThe MAX1932 uses a constant frequency, PWM, con-
troller architecture. This controller sets the switch on-
time and drives an external N-channel MOSFET (see
Figure 1). As the load varies, the error amplifier sets the
inductor peak current necessary to supply the load and
regulate the output voltage.
Output Current Limit The MAX1932 uses an external resistor at CS+ and CS-
to sense the output current (see Figure 2). The typical
current-limit threshold is 2V. CLis designed to help find
the optimum APD bias point by going low to indicate
when the APD reaches avalanche and that current limit
has been activated. To minimize noise, CLonly
changes state on an internal oscillator edge.
Output Control DAC An internal digital-to-analog converter can be used to
control the output voltage of the DC-DC converter
(Figure 2). The DAC output is changed through an SPI™
serial interface using an 8-bit control byte. On power-up,
the DAC defaults to FF hex (1.25V), which corresponds
to a minimum boost converter output voltage.
Alternately, the output voltage can be set with external
resistors, an external DAC, or a voltage source. Output
span and offset are independently settable with exter-
nal resistors. See the Applications Informationsection
for output control equations.
SPI Interface/ShutdownUse an SPI-compatible 3-wire serial interface with the
MAX1932 to control the DAC output voltage and to shut
down the MAX1932. Figures 4 and 5 show timing diagrams
for the SPI protocol. The MAX1932 is a write-only device
and uses CSalong with SCLK and DIN to communicate.
The serial port is always operational when the device is
powered. To shut down the DC-DC converter portion only,
update the DAC registers to 00 hex.
Applications Information
Voltage Feedback Sense PointFeedback can be taken from in front of, or after, the cur-
rent-limit sense resistor. The current-limit sense resistor
forms a lowpass filter with the output capacitor. Taking
feedback after the current-limit sense resistor (see Figure
2), optimizes the output voltage accuracy, but requires
overcompensation, which slows down the control loop
response. For faster response, the feedback can be
taken from in front of the current-sense resistor (see
Figure 3). This configuration however, makes the output
voltage more sensitive to load variation and degrades
output accuracy by an amount equal to the load current
times the current-sense resistor value.
Pin Description
PINNAMEFUNCTIONSCLKDAC Serial Clock InputDINDAC Serial Data InputCLCurrent-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN.CS+Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential
threshold is 2V. CS+ has typically 1MΩ resistance to ground.CS-Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground.DACOUTInternal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or
sink 50µA.
7FBFeedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the
output voltage. The feedback set point is 1.25V.COMPCompensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is
actively discharged to ground during shutdown or undervoltage conditions.GNDGroundGATEGate-Driver Output for External N-FETVINIC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor.CSDAC Chip-Select Input
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Output and DAC Adjustments RangeMany biasing applications require an adjustable output
voltage, which is easily obtained using the MAX1932’s
DAC output (Figure 2).
The DAC output voltage is given by the following equation:
On power-up, DACOUTdefaults to FF hex or 1.25V,
which corresponds to the minimum VOUToutput voltage.
The voltage generated at DACOUTis coupled to FB
through R6. DACOUTcan sink only 50µA so:
Select the minimum output voltage (VOUTFF), and the
maximum output voltage (VOUT01) for the desired
adjustment range. R5 sets the adjustment span using
the following equation:
R5 = (VOUTFF- VOUT01) (R6/1.25V)
R8 sets the minimum output of the adjustment range
with the following equation:
R8 = (1.25V ✕R5)/(VOUTFF)
Setting the Output Voltage without
the DAC Adjust the output voltage by connecting a voltage-
divider from the output (VOUT) to FB (Figure 2 with R6
omitted). Select R8 between 10kΩto 50kΩ. Calculate
R5 with the following equation:
Inductor SelectionOptimum inductor selection depends on input voltage,
output voltage, maximum output current, switching fre-
quency, and inductor size. Inductors are typically spec-
ified by their inductance (L), peak current (IPK), and
resistance (LR).
The inductance value is given by:
where VINis the input voltage, IOUT(MAX)is the maxi-
mum output current delivered, VOUTis the output volt-
age, and T is the switching period (3.3µs), ηis the
estimated power conversion efficiency, and D is the
maximum duty cycle:
D < (VOUT - VIN)/VOUTup to a maximum of 0.9
Since the L equation factors in efficiency, for inductor cal-
culation purposes, an ηof 0.5 to 0.75 is usually suitable.
For example, with a maximum DC load current of 2.5mA,
a 90V output, VIN= 5V, D = 0.9, T = 3.3µs, and ηesti-
mated at 0.75, the above equation yields an L of 111µH,
so 100µH would be a suitable value.
The peak inductor current is given by:
These are typical calculations. For worst case, refer to
the article titled “Choosing the MAX1932 External
Indicator, Diode, Current Sense Resistor, and Output
Filter Capacitor for Worst Case Conditions” located on
the Maxim website in the Application Notes section (visit
/an1805).
External Power-Transistor SelectionAn N-FET power switch is required for the MAX1932. The
N-FET switch should be selected to have adequate on-
resistance with the MOSFET VGS= VIN(MIN). The break-
down voltage of the N-FET must be greater than VOUT.
For higher-current output applications (such as 5mA at
90V), SOT23 high-voltage low-gate-threshold N-FETs
may not have adequate current capability. For example,
with a 5V input, a 90V, 5mA output requires an inductor
peak of 240mA. For such cases it may be necessary to
simply parallel two N-FETs to achieve the required cur-
rent rating. With SOT23 devices this often results in
smaller and lower cost than using a larger N-FET device.
Diode SelectionThe output diode should be rated to handle the output
voltage and the peak switch current. Make sure that the
diode’s peak current rating is at least IPKand that its
breakdown voltage exceeds VOUT. Fast reverse recov-
ery time (trr< 10ns) and low junction capacitanceVDTPKIN=××VDT
OUTMAXOUT()×××2VOUT581251=−⎛⎜⎞⎟.V6125≥μCODEVV
DACOUT=×⎛⎜⎞⎟+⎛⎜⎞⎟125
256
MAX1932Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
(<10pF) are recommended to minimize losses. A small-
signal silicon switching diode is suitable if efficiency is
not critical.
Output Filter Capacitor SelectionThe output capacitors of the MAX1932 must have high
enough voltage rating to operate with the VOUT
required. Output capacitor effective series resistance
(ESR) determines the amplitude of the high-frequency
ripple seen on the output voltage. In the typical appli-
cation circuit, a second RC formed by R1 and C3 fur-
ther reduces ripple.
Input Bypass Capacitor SelectionThe input bypass capacitor reduces the peak currents
drawn from the voltage source and reduces noise
caused by the MAX1932’s switching action. The input
source impedance determines the size of the capacitor
required at the input (VIN). A low ESR capacitor is rec-
ommended. A 1µF ceramic capacitor is adequate for
most applications. Place the bypass capacitor as close
as possible to the VIN and GND pins.
Current-Sense Resistor SelectionCurrent limit is used to set the maximum delivered out-
put current. In the typical application circuit, MAX1932
is designed to current limit at:
Note that ILIMITmust include current drawn by the
feedback divider (if sensing feedback after R1) and the
input current of CS-.
Stability and Compensation
Component SelectionCompensation components, R7 and C4, introduce a
pole and a zero necessary to stabilize the MAX1932
(see Figure 6). The dominant pole, POLE1, is formed by
the output impedance of the error amplifier (REA) and
C4. The R7/C4 zero, ZERO1, is selected to cancel the
pole formed by the output filter cap C3 and output load
RLD, POLE2. The additional pole of R1/C3, POLE3,
should be at least a decade past the crossover fre-
quency to not affect stability:
POLE1 (dominant pole) = 1 / (2π✕REA✕C4)
ZERO1 (integrator zero) = 1 / (2π✕R7 ✕C4)
POLE2 (output load pole) = K1 / (2π✕RLD✕(C2 + C3))
POLE3 (output filter pole) = 1 / (2π✕R1 ✕C3)
The DC open-loop gain is given by:
AOL= K2 ✕Gm ✕REA
where REA= 310MΩ, = 110µS,
RLDis the parallel combination of feedback network
and the load resistance.
A properly compensated MAX1932 results in a gain vs.
frequency plot that crosses 0dB with a single pole
slope (20dB per decade). See Figure 6.
Table 1 lists suggested component values for several
typical applications.
Further Noise ReductionThe current-limit sense resistor is typically used as part
of an output lowpass filter to reduce noise and ripple.
For further reduction of noise, an LC filter can be added
as shown in Figure 7. Output ripple and noise with and
without the LC filter are shown in the Typical Operating
Characteristics. If a post LC filter is used, it is best to
use a coil with fairly large resistance (or a series resis-
tor) so that ringing at the response peak of the LC filter
is damped. For a 330µH and 1µF filter, 22Ωaccom-
plishes this, but a resistor is not needed if the coil resis-
tance is greater than 15Ω.
Output Accuracy and Feedback
Resistor SelectionThe MAX1932 features 0.5% feedback accuracy. The
total voltage accuracy of a complete APD bias circuit is
the sum of the FB set-point accuracy, plus resistor ratio
error and temperature coefficient. If absolute accuracy
is critical, the best resistor choice is an integrated net-
work with specified ratio tolerance and temperature
coefficient. If using discrete resistors in high-accuracy
applications, pay close attention to resistor tolerance
and temperature coefficients.
Temperature CompensationAPDs exhibit a change in gain as a function of temper-
ature. This gain change can be compensated with an
appropriate adjustment in bias voltage. For this reason
it may be desirable to vary the MAX1932 output voltageVVolts
VoltsTondHenriesIN
OUTIN
OUT
OUTIN075×××⎜⎞⎟×⎜⎟()
secVV
OUTIN
OUTIN2=×-VLIMIT2=
