MAX192BEAP+ ,Low-Power, 8-Channel, Serial 10-Bit ADCELECTRICAL CHARACTERISTICS(V = 5V ±5%, f = 2.0MHz, external clock (50% duty cycle), 15 clocks/conve ..
MAX192BEAP+ ,Low-Power, 8-Channel, Serial 10-Bit ADCELECTRICAL CHARACTERISTICS(V = 5V ±5%, f = 2.0MHz, external clock (50% duty cycle), 15 clocks/conve ..
MAX192BEPP ,Low-Power, 8-Channel, Serial 10-Bit ADCGeneral DescriptionInputsThe MAX192 is a low-cost, 10-bit data-acquisition system' Single +5V Opera ..
MAX192BEPP+ ,Low-Power, 8-Channel, Serial 10-Bit ADCFeaturesCH5 6 15 DOUTCH6 7 14 DGNDCH7 8 13 AGNDSee last page for Typical Operating Circuit.12AGND 9 ..
MAX192BEPP+ ,Low-Power, 8-Channel, Serial 10-Bit ADCFeaturesCH5 6 15 DOUTCH6 7 14 DGNDCH7 8 13 AGNDSee last page for Typical Operating Circuit.12AGND 9 ..
MAX192BEWP ,Low-Power, 8-Channel, Serial 10-Bit ADCFeaturesCH5 6 15 DOUTCH6 7 14 DGNDCH7 8 13 AGNDSee last page for Typical Operating Circuit.12AGND 9 ..
MAX489CSD+ ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversMAX481/MAX483/MAX485/MAX487–MAX491/MAX1487Low-Power, Slew-Rate-LimitedRS-485/RS-422 Transceivers
MAX489CSD+T ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversELECTRICAL CHARACTERISTICS(V = 5V ±5%, T = T to T , unless otherwise noted.) (Notes 1, 2)CC A MIN M ..
MAX489CSD-T ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsguarantees a logic-high output if the input is open circuit.MAX3030E–MAX3033E: ±15kV E ..
MAX489ECPD ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 TransceiversGeneral Description ________
MAX489ECPD+ ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:EMI and reduce reflections caused by improperly termi-MAX3460–MAX3464: +5V, Fail-Safe, ..
MAX489ECSD ,15kV ESD-Protected / Slew-Rate-Limited / Low-Power / RS-485/RS-422 Transceiversapplications that are not ESD sen-MAX481ECPA 0°C to +70°C 8 Plastic DIPsitive see the pin- and func ..
MAX192ACAP+-MAX192AEAP+-MAX192AEPP+-MAX192BCAP+-MAX192BCAP+T-MAX192BCPP+-MAX192BEAP+-MAX192BEPP+-MAX192BEWP+
Low-Power, 8-Channel, Serial 10-Bit ADC
________________General DescriptionThe MAX192 is a low-cost, 10-bit data-acquisition system
that combines an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and ultra-low power consumption. The device
operates with a single +5V supply. The analog inputs are
software configurable for single-ended and differential
(unipolar/bipolar) operation.
The 4-wire serial interface connects directly to SPI™,
QSPI™, and Microwire™ devices, without using external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The MAX192
uses either the internal clock or an external serial-
interface clock to perform successive approximation A/D
conversions. The serial interface can operate beyond
4MHz when the internal clock is used. The MAX192 has
an internal 4.096V reference with a drift of ±30ppm typi-
cal. A reference-buffer amplifier simplifies gain trim and
two sub-LSBs reduce quantization errors.
The MAX192 provides a hardwired SHDNpin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the device, and
the quick turn-on time allows the MAX192 to be shutown between conversions. By powering down
between conversions, supply current can be cut to
under 10μA at reduced sampling rates.
The MAX192 is available in 20-pin DIP and SO pack-
ages, and in a shrink-small-outline package (SSOP)
that occupies 30% less area than an 8-pin DIP. The
data format provides hardware and software compati-
bility with the MAX186/MAX188. For anti-aliasing filters,
consult the data sheets for the MAX291–MAX297.
________________________ApplicationsAutomotive
Pen-Entry Systems
Consumer Electronics
Portable Data Logging
Robotics
Battery-Powered Instruments, Battery
Management
Medical Instruments
____________________________Features8-Channel Single-Ended or 4-Channel Differential
InputsSingle +5V OperationLow Power:1.5mA (operating)
2μA (power-down)Internal Track/Hold, 133kHz Sampling RateInternal 4.096V Reference4-Wire Serial Interface is Compatible
with SPI, QSPI, Microwire, and TMS32020-Pin DIP, SO, SSOP PackagesPin-Compatible 12-Bit Upgrade (MAX186/MAX188)
_______________Ordering Information
Low-Power, 8-Channel,rial 10-Bit ADCTOP VIEW
DIP/SO/SSOPVDD
SCLK
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREFSHDN
AGND
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX192
___________________Pin ConfigurationSPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Corp.
19-0247; Rev. 1; 4/97
PARTTEMP. RANGEMAX192ACPP0°C to +70°C
MAX192BCPP0°C to +70°C
MAX192ACWP0°C to +70°C20 Wide SO
20 Plastic DIP
20 Plastic DIP
PIN-PACKAGEMAX192BCWP0°C to +70°C20 Wide SO
MAX192ACAP0°C to +70°C20 SSOP
MAX192BCAP0°C to +70°C20 SSOP
±1/2
±1/2
INL (LSB)±1/2
MAX192AEPP-40°C to +85°C20 Plastic DIP±1/2
MAX192BEPP-40°C to +85°C20 Plastic DIP±1
MAX192AEWP-40°C to +85°C20 Wide SO±1/2
MAX192BEWP-40°C to +85°C20 Wide SO±1
MAX192AEAP-40°C to +85°C20 SSOP±1/2
MAX192BEAP-40°C to +85°C20 SSOP±1
MAX192AMJP-55°C to +125°C20 CERDIP±1/2
MAX192BMJP-55°C to +125°C20 CERDIP±1
See last page for Typical Operating Circuit.
Low-Power, 8-Channel,rial 10-Bit ADCVDDto AGND...........................................................-0.3V to +6V
AGND to DGND....................................................-0.3V to +0.3V
CH0–CH7 to AGND, DGND......................-0.3V to (VDD+ 0.3V)
CH0–CH7 Total Input Current..........................................±20mA
VREF to AGND..........................................-0.3V to (VDD+ 0.3V)
REFADJto AGND......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SO (derate 10.00mW/°C above +70°C)......................800mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX192_C_P.....................................................0°C to +70°C
MAX192_E_P..................................................-40°C to +85°C
MAX192_MJP...............................................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%, fCLK= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7μF capacitor at VREF pin,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGSMAX192A
-3dB rolloff
65kHz, VIN= 4.096Vp-p (Note 3)
External reference, 4.096V
MAX192B
No missing codes over temperature
External reference, 4.096V
CONDITIONSkHz800Full-Power Bandwidth
MHz4.5Small-Signal Bandwidth-75Channel-to-Channel Crosstalk70SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
(up to the 5th harmonic)66SINADSignal-to-Noise + Distortion Ratio
±1/2
Bits10Resolution
LSB±0.1Channel-to-Channel
Offset Matching
ppm/°C±0.8Gain Temperature Coefficient
LSB±1Relative Accuracy (Note 2)
LSB±1DNLDifferential Nonlinearity
LSB±2Offset Error
LSB±2Gain Error
UNITSMINTYPMAXSYMBOLPARAMETERInternal clock5.510Conversion Time (Note 4)tCONVExternal clock, 2MHz, 12 clocks/conversion6μs
Track/Hold Acquisition TimetAZ1.5μs
Aperture Delay10ns
Aperture Jitter<50ps
Internal Clock Frequency1.7MHz
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock)
CONVERSION RATE
Low-Power, 8-Channel,rial 10-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%, fCLK= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7μF capacitor at VREF pin,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Internal compensation
0mA to 0.5mA output load= +25°C (Note 7)
(Note 5)
On/off leakage current; VIN= 0V, 5V
Bipolar
Used for data transfer only
Internal compensation (Note 5)
External compensation, 4.7μF
Single-ended range (unipolar only)
Common-mode range (any input)
CONDITIONS2.5Load Regulation (Note 8)
ppm/°C±30VREF Tempco30VREF Short-Circuit Current4.0664.0964.126VREF Output Voltage16Input Capacitance±0.01±1Multiplexer Leakage Current
-VREF+VREF2
Analog Input Voltage
(Note 6)0VREFVREFVDD
MHz
External Clock Frequency0.10.4
UNITSMINTYPMAXSYMBOLPARAMETER
Capacitive Bypass at VREFExternal compensation4.7μF
Internal compensation0.01Capacitive Bypass at REFADJExternal compensation0.01μF
REFADJ Adjustment Range±1.5%
Input Voltage Range2.5VDD +
50mVV
Input Current200350μA
Input Resistance1220kΩ
Shutdown VREF Input Current1.510μA
Buffer Disable Threshold
REFADJ
VDD -
50mVV
Unipolar
Differential range
Internal compensation mode0Capacitive Bypass at VREFExternal compensation mode4.7μF
Reference-Buffer Gain1.678V/V
REFADJ Input Current±50μA
ANALOG INPUT
INTERNAL REFERENCE(reference buffer enabled)
EXTERNAL REFERENCE AT VREF(buffer disabled, VREF = 4.096V)
EXTERNAL REFERENCE AT REFADJ
Note 1:Tested at VDD= 5.0V; single-ended, unipolar.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Grounded on-channel; sine wave applied to all off channels.
Note 4:Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 5:Guaranteed by design. Not subject to production testing.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Sample tested to 0.1% AQL.
Note 8:External load should not change during conversion for specified accuracy.
Note 9:Measured at VSUPPLY+ 5% and VSUPPLY- 5% only.
Low-Power, 8-Channel,rial 10-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%, fCLK= 2.0MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (133ksps), 4.7μF capacitor at VREF pin,= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ISINK= 16mA
ISINK= 5mA
SHDN= open
SHDN= open
SHDN= 0V
SHDN= VDD
(Note 5)
VIN= 0V or VDD
CONDITIONS0.3VOLOutput Voltage Low0.4-100100SHDNMax Allowed Leakage,
Mid Input2.75VFLTSHDNVoltage, Floating1.5VDD - 1.5VIMSHDNInput Mid Voltage-4.0IINLSHDNInput Current, Low4.0IINHSHDNInput Current, High0.5VINLSHDNInput Low VoltageVDD - 0.5VINHSHDNInput High Voltage15CINDIN,SCLK,CSInput Capacitance±1IINDIN, SCLK,CSInput Leakage0.15VHYSTDIN, SCLK,CSInput Hysteresis0.8VINLDIN,SCLK, CSInput Low Voltage2.4VINHDIN,SCLK, CSInput High Voltage
UNITSMINTYPMAXSYMBOLPARAMETEROutput Voltage HighVOHISOURCE= 1mA4V
Three-State Leakage CurrentILCS= 5V±10μA
Three-State Leakage CapacitanceCOUTCS= 5V (Note 5)15pF
Positive Supply VoltageVDD5 ±5%V
Operating mode1.52.5mA
Fast power-down3070Positive Supply CurrentIDD
Full power-down210μA
Positive Supply Rejection
(Note 9)PSRVDD= 5V ±5%; external reference, 4.096V;
full-scale input±0.06±0.5mV
EXTERNAL REFERENCE AT REFADJDIGITAL INPUTS (DIN, SCLK, –C—S–, –S—H—D—N–)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
Note 5:Guaranteed by design. Not subject to production testing.
Low-Power, 8-Channel,rial 10-Bit ADC
TIMING CHARACTERISTICS(VDD= 5V ±5%, TA= TMINto TMAX, unless otherwise noted.)
CLOAD= 100pF
External clock mode only, CLOAD= 100pF
CLOAD= 100pF
CLOAD= 100pF
CLOAD= 100pF
External clock mode only, CLOAD= 100pF
CONDITIONS200tSTRCSRise to SSTRB Output
Disable (Note 5)Fall to SSTRB Output Enable
(Note 5)ns200tSDV0tDHDIN to SCLK Hold100tDS1.5tAZAcquisition Time
DIN to SCLK Setup200tSSTRBSCLK Fall to SSTRB200tCLSCLK Pulse Width Low200tCHSCLK Pulse Width High0tCSHCSto SCLK Rise Hold20150tDO100tDV100tTR
SCLK Fall to Output Data Valid100tCSSCSto SCLK Rise Setup
UNITSMINTYPMAXSYMBOLPARAMETERSSTRB Rise to SCLK Rise
(Note 5)tSCKInternal clock mode only0nsRise to Output DisableFall to Output Enable
__________________________________________Typical Operating CharacteristicsCHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (°C)
(L100
POWER-SUPPLY REJECTION
vs. TEMPERATURE
TEMPERATURE (°C)
(L
VDD = +5V ±5%2.456
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURETEMPERATURE (°C)
(V
-40-20020406080100120-60140
Low-Power, 8-Channel,rial 10-Bit ADCs+5V
CLOAD
DGND
DOUT
CLOAD
DGND
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOL+3V
CLOAD
DGND
DOUT
CLOAD
DGND
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 1. Load Circuits for Enable TimeFigure 2. Load Circuits for Disabled Time
Pin Description
PINNAMEFUNCTION1–8CH0–CH7Sampling Analog Inputs
9, 13AGNDAnalog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins to
analog ground.SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10μA (max) supply cur-
rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifi-
er in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external
compensation mode.VREF
Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.
Add a 4.7μF capacitor to ground when using external compensation mode. Also functions as an
input when used with a precision external reference.REFADJReference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to VDD.DGNDDigital GroundDOUTSerial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CSis
high.SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/D
conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. SSTRB is high impedance when CSis high
(external mode).DINSerial Data Input. Data is clocked in at the rising edge of SCLK.CSActive-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT
is high impedance.SCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)VDDPositive Supply Voltage, +5V ±5%
Low-Power, 8-Channel,rial 10-Bit ADCINPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.46V
REFERENCE
T/HANALOG
INPUTMUX
SAR
ADC
DOUT
SSTRB
VDD
DGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
AGND
REFADJ
VREF
OUT
REF
CLOCK
+4.096V
20k 1.65
SHDNAGND9
MAX192
Figure 3.Block Diagram
tailed DescriptionThe MAX192 uses a successive-approximation conver-
sion technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX192.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7 and IN-is switched to AGND. In
differential mode, IN+ and IN-are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Refer
to Tables 1 and 2 to configure the channels.
In differential mode, IN-and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1μF capacitor from AIN-(the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is
simply AGND. This unbalances node ZERO at the input
of the comparator. The capacitive DAC adjusts during
the remainder of the conversion cycle to restore its
node ZERO to 0V within the limits of its resolution. This
action is equivalent to transferring a charge of
16pF x (VIN+ -VIN-) from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
CSWITCH
TRACK
T/H
SWITCH
10k
CHOLD
HOLD
CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.
DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4.Equivalent Input Circuit
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for single-ended
inputs, IN-is connected to AGND, and the converter
samples the “+” input. If the converter is set up for differ-
ential inputs, IN-connects to the “-” input, and the differ-
ence of IN+ -IN-is sampled. At the end of the conver-
sion, the positive input connects back to IN+, and
CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acquisi-
tion time lengthens and more time must be allowed
between conversions. Acquisition time is calculated by:
tAZ= 9 (RS+ RIN) 16pF
where RIN= 5kΩ, RS= the source impedance of the
input signal, and tAZ is never less than 1.5μs. Note that
source impedances below 5kW do not significantly affect
the AC performance of the ADC. Higher source imped-
ances can be used if an input capacitor is connected to
the analog inputs, as shown in Figure 5. Note that the
input capacitor forms an RC filter with the input source
impedance, limiting the ADC’s signal bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
See the data sheets for the MAX291–MAX297 filters.
Analog Input Range and Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from AGND -0.3V to VDD+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV, or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.The MAX192 can be configured for differential (unipolar
or bipolar) or single-ended (unipolar only) inputs, as
selected by bits 2 and 3 of the control byte (Table 3).
In the single-ended mode, set the UNI/BIP bit to unipolar.
In this mode, analog inputs are internally referenced to
AGND, with a full-scale input range from 0V to VREF.
In differential mode, both unipolar and bipolar settings
can be used. Choosing unipolar mode sets the differen-
tial input range at 0V to VREF. The output code is invalid
(code zero) when a negative differential input voltage is
applied. Bipolar mode sets the differential input range to
±VREF/ 2. Note that in this differential mode, the com-
mon-mode input range includes both supply rails. Refer
to Tables 4a and 4b for input voltage ranges.
Quick LookTo evaluate the analog performance of the MAX192
quickly, use Figure 5’s circuit. The MAX192 requires aontrol byte to be written to DIN before each
conversion. Tying DIN to +5V feeds in control bytes of
Low-Power, 8-Channel,rial 10-Bit ADC
Table 1.Channel Selection in Single-Ended Mode (SGL/DIF= 1)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7AGND00+–00+–01+–01+–10+–10+–11+–11+ –
Low-Power, 8-Channel,rial 10-Bit ADC
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BitNameDescription7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the eight channels are used for the conversion.SEL1See Tables 1 and 2.SEL0UNI/BIP
1= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in differential bipolar
mode, the differential signal can range from -VREF / 2 to +VREF / 2. Select differential
operation if bipolar mode is used.SGL/DIF
1= single ended, 0= differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. Select unipolar operation
if single-ended mode is used. See Tables 1 and 2. PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode
0Full power-down (IQ= 2μA)
1Fast power-down (IQ= 30μA)
0Internal clock mode
1External clock mode
Table 3.Control-Byte Format
Table 2.Channel Selection in Differential Mode (SGL/DIF= 0)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH700+–01+–10+–11+–00–+01–+10–+11–+
Low-Power, 8-Channel,rial 10-Bit ADC$FF (HEX), which trigger single-ended conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result comes
out of DOUT. Varying the analog input to CH7 should
alter the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a ConversionA conversion is started on the MAX192 by clocking
a control byte into DIN. Each rising edge on SCLK,
with CSlow, clocks a bit from DIN into the MAX192’s
internal shift register. After CSfalls, the first arriving
logic “1” bit defines the MSB of the control byte. Until
this first “start” bit arrives, any number of logic “0” bits
can be clocked into DIN with no effect. Table 3 shows
the control-byte format.
The MAX192 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire and SPI both
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Example: Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode,
call it TB1. TB1 should be of the format:
1XXXXX11 binary, where the Xs denote the par-
ticular channel and conversion-mode selected.Use a general-purpose I/O line on the CPU to
pull CSon the MAX192 low.Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 HEX) and
simultaneously receive byte RB2.Transmit a byte of all zeros ($00 HEX) and
simultaneously receive byte RB3.Pull CSon the MAX192 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero, two sub-LSB bits, and
three trailing zeros. The total conversion time is a func-
tion of the serial clock frequency and the amount of
dead time between 8-bit transfers. Make sure that the
total conversion time does not exceed 120μs, to avoid
excessive T/H droop.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 15). For bipolar inputs in differential mode, the
output is twos-complement (Figure 16). Data is clocked
out at the falling edge of SCLK in MSB-first format.
Internal and External Clock ModesThe MAX192 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX192. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7 through 10
show the timing characteristics common to both
modes.
REFERENCEZERO
SCALEFULL SCALEInternal Reference0V+4.096V
External
Reference
VREF
at REFADJ
at VREF0V
VREFADJ(1.678)
Table 4a.Unipolar Full Scale and Zero
Scale
Table 4b.Differential Bipolar Full Scale,
Zero Scale, and Negative Full Scale
REFERENCENEGATIVE
FULL SCALEFULL SCALEInternal Reference-4.096V / 2+4.096V / 2
External
Reference
-1/2VREFADJ
(1.678)
+1/2VREF
REFADJ
0.at VREF-1/2VREF
+1/2VREFADJ
(1.678)
ZERO
SCALEExternal ClockIn external clock mode, the external clock not only
shifts data in and out, it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte.
Successive-approximation bit decisions are made and
appear at DOUT on each of the next 12 SCLK falling
edges (see Figure 6). The first 10 bits are the true data
bits, and the last two are sub-LSB bits.
SSTRB and DOUT go into a high-impedance state whengoes high; after the next CSfalling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10μs, or if serial-clock interruptions
could cause the conversion interval to exceed 120μs.
Internal ClockIn internal clock mode, the MAX192 generates its own
conversion clock internally. This frees the microproces-
sor from the burden of running the SAR conversion
clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the
conversion is complete. SSTRB will be low for a maxi-
mum of 10μs, during which time SCLK should remain
low for best noise performance. An internal register
stores data when the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the
next falling clock edge will produce the MSB of the
conversion at DOUT, followed by the remaining bits in
MSB-first format (Figure 9). CSdoes not need to be
held low once a conversion is started.
Low-Power, 8-Channel,rial 10-Bit ADC0.1μF
VDD
DGND
AGND
AGND
SCLK
DIN
DOUT
SSTRB
SHDN
+5V
N.C.
0.01μF
CH7
REFADJ
VREFC2
0.01μF
+2.5V
REFERENCE
4.7μF
0V TO
4.096V
ANALOG
INPUT
+2.5V**
OSCILLOSCOPE
CH1CH2CH3CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**OPTIONAL. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
MAX192
+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5.Quick-Look Circuit
Low-Power, 8-Channel,rial 10-Bit ADCSSTRB
SCLK
DIN
DOUT4812162024
STARTSEL2SEL1SEL0UNI/
BIP
SGL/
DIFPD1PD0MSBB8B7B6B5B4B3B2B1B0LSBS1SO
ACQUISITION
1.5µs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1
RB1RB2RB3
RB2RB3
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDOtTR
tCSH
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
Pulling CShigh prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when CSgoes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
and out of the MAX192 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time,
tAZ, is kept above 1.5μs.
Data FramingThe falling edge ofCSdoes notstart a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN withCSlow any-
time the converter is idle, e.g. after VDDis applied.
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
If a falling edge onCSforces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CSis low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.
