MAX191BCWG+ ,Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Downfeatures a logic power-downinput, which reduces the 3mA V supply current to ♦ 24-Pin Narrow DIP and ..
MAX191BCWG+ ,Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-DownELECTRICAL CHARACTERISTICS(V = 5V ±5%, V = 0V or -5V ±5%, f = 1.6MHz, 50% duty cycle, AIN- = AGND, ..
MAX191BCWG+T ,Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-DownMAX19119-4506; Rev 4; 2/97Low -Pow er, 12-Bit Sampling ADCw ith Internal Reference and Pow er-Dow n
MAX191BENG ,Low-Power / 12-Bit Sampling ADC with Internal Reference and Power-DownFeatures
. 12-Bit Resolution, 1/2LSB Linearity
. +5V or 15V Operation (MAX191)
. Built-InT ..
MAX191BENG+ ,Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-DownApplicationsMAX191AEWG -40°C to +85°C 24 Wide SO ±1/2Battery-Powered Data LoggingMAX191BEWG -40°C t ..
MAX191BENG+ ,Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-DownELECTRICAL CHARACTERISTICS(V = 5V ±5%, V = 0V or -5V ±5%, f = 1.6MHz, 50% duty cycle, AIN- = AGND, ..
MAX487ESA+T ,±15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplications:ceivers on the bus. The MAX488E–MAX491E areMAX3483E/MAX3485E/MAX3486E/MAX3488E/designe ..
MAX4885ETJ+ ,Ultra Low-Capacitance VGA Switch with ±15kV ESDELECTRICAL CHARACTERISTICS (continued)(V = +5.0V ±10%, V = +2V to +5.5V, T = T to T , unless otherw ..
MAX4885ETJ+T ,Ultra Low-Capacitance VGA Switch with ±15kV ESDELECTRICAL CHARACTERISTICS(V = +5.0V ±10%, V = +2V to +5.5V, T = T to T , unless otherwise noted. T ..
MAX4888ETI , 2.5Gbps PCI Express Passive Switches
MAX4889BETO+T ,2.5/5.0/8.0Gbps PCIe Passive Switch
MAX4889ETO+ ,2.5Gbps PCI Express Passive Switches
MAX191ACWG+-MAX191BCNG+-MAX191BCWG+-MAX191BCWG+T-MAX191BENG+-MAX191BEWG+
Low-Power, 12-Bit Sampling ADC with Internal Reference and Power-Down
General DescriptionThe MAX191 is a monolithic, CMOS, 12-bit analog-to-
digital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial μP interface. The
MAX191 has a 7.5μs conversion time, a 2μs acquisition
time, and a guaranteed 100ksps sample rate.
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA VDDsupply current to
50μA max, including the internal-reference current.
Decoupling capacitors are the only external compo-
nents needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is com-
patible with SPITM, QSPITM, and MICROWIRETM serial-
interface standards.
________________________ApplicationsBattery-Powered Data Logging
PC Pen Digitizers
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
Telecommunications
Digital Signal Processing (DSP)
____________________________Features12-Bit Resolution, 1/2LSB Linearity+5V or ±5V OperationBuilt-In Track/HoldInternal Reference with Adjustment CapabilityLow Power: 3mA Operating Mode
20μA Power-Down Mode100ksps Tested Sampling RateSerial and 8-Bit Parallel μP Interface24-Pin Narrow DIP and Wide SO Packages
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-DownVDD
CLK/SCLK
PAR
HBENAIN-
AIN+
VSS
TOP VIEW
D7/DOUT
D6/SCLKOUTBIP
AGND
REFADJ
VREF
D5/SSTRB
D3/D11
D2/D10DGND
D1/D9
D0/D8
BUSY
DIP/SOMAX191
Pin Configuration2.46V
REFREFOUT
12-BIT
SAR ADC
OSC
CONTROL
LOGIC
3-STATE
OUTPUT
8-BIT
BUS
AND
SERIAL
I/O
D7/DOUT
D6/SCLKOUT
D5/SSTRB
D3/D11
D2/D10
D1/D9
D0/D8
BUSY
HBEN
REFADJ
VREF
AIN +
AIN -23
VDDCLK/SCLK12228
AGNDDGND
PARBIP
MAX191
VSS
Functional Diagram19-4506; Rev 4; 2/97
PARTTEMP. RANGEPIN-PACKAGEMAX191ACNG0°C to +70°C
24 Narrow Plastic DIP
24 Wide SO
±1/2
±1/2
ERROR
(LSB)24 Narrow Plastic DIP
MAX191BCNG
MAX191ACWG
0°C to +70°C
0°C to +70°C
MAX191BCWG0°C to +70°C24 Wide SO±1
MAX191BC/DDice*±10°C to +70°C
MAX191AENG-40°C to +85°C24 Narrow Plastic DIP±1/2
MAX191BENG-40°C to +85°C24 Narrow Plastic DIP±1
MAX191AEWG-40°C to +85°C24 Wide SO±1/2
MAX191AMRG24 Narrow CERDIP**±1/2
MAX191BMRG24 Narrow CERDIP**±1
-55°C to +125°C
-55°C to +125°C
MAX191BEWG-40°C to +85°C24 Wide SO±1
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
EVALUATION KIT MANUAL
FOLLOWS DATA SHEET* Dice are specified at TA= +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Ordering Information
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%, VSS= 0V or -5V ±5%, fCLK= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.DDto DGND............................................................-0.3V to +7V
VSSto AGND............................................................-7V to +0.3VDDto VSS..............................................................................12V
AGND, VREF, REFADJ to DGND................-0.3V to (VDD+ 0.3V)
AIN+, AIN-, PDto VSS.................................-0.3V to (VDD+ 0.3V)
CS, RD, CLK, BIP, HBEN, PAR, to DGND....-0.3V to (VDD+ 0.3V)
BUSY, D0–D7 to DGND..............................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
Wide SO (derate 11.76mW/°C above +70°C)......................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C)........1000mW
Operating Temperature Ranges
MAX191_C_ _................................................................0°C to +70°C
MAX191_E_ _.............................................................-40°C to +85°C
MAX191_M_ _..........................................................-55°C to +125°C
Storage Temperature Range.....................................-65°C to +160°C
Lead Temperature (soldering, 10sec).....................................+300°C
PARAMETERCONDITIONSMINTYPMAXUNITSOffset ErrorMAX191B±2LSBMAX191A±1
Differential NonlinearityNo missing codes over temperature±1LSB
Integral NonlinearityMAX191B±1LSB
MAX191A±2Gain Error (Note 3)MAX191B±3LSB
Resolution12Bits
MAX191A±1/2
Gain-Error Tempco (Note 4)Excludes internal-reference drift±0.2ppm/°C
1kHz input signal, TA= +25°C70dB
1kHz input signal, TA= +25°C-80dB
Spurious-Free Dynamic Range1kHz input signal, TA= +25°C80dB
Synchronous CLK (12 to 13 CLKs)Conversion Time (Note 5)Internal CLK, CL= 120pF61218μs
Track/Hold Acquisition Time2μs
Aperture Delay25ns
Aperture Jitter50ps
0.11.6MHz
Signal-to-Noise plus Distortion
Ratio
Total Harmonic Distortion
(up to the 5th Harmonic)
External Clock Frequency
Range (Note 6)
SYMBOLDNL
INL
SINAD
SFDR
THD
tCONV
fCLK
DC ACCURACY (Note 2)
DYNAMIC ACCURACY(sample rate = 100kHz, VIN= 4Vp-p)
CONVERSION RATE
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%, VSS= 0V or -5V ±5%, fCLK= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMINto TMAX, unless otherwise noted.) (Note 1)External Leakage for Float
State (Note 12)FLTV2.8Reference compensation mode—externalPDFloating-State Voltage±100Maximum current allowed for “floating state”
IINμA±20PD= 0V to VDD(Note 11)PDInput Current
±200PD= high/floatIINμA±0.1PD= lowInput Current CLK
CINpF10Input Capacitance (Note 6)
VILV0.5PDInput Low Voltage
VIHV4.5PDInput High Voltage
IINμA±10VIN= 0V to VDDInput Current
VIHV2.4CS, RD, CLK, HBEN, PAR, BIPInput High VoltageILV0.8CS, RD, CLK, HBEN, PAR, BIPInput Low Voltage510External-reference modeInput Resistance1External-reference = 5VInput Current
REFADJ Input Adjustment Range
(Note 10)2.55.0External-reference modeInput Voltage Range60REFADJ = 5VREFADJ Input Current2.4REFADJ Output Voltage4.5REFADJ Disable Threshold-6030±300VDD= ±5%, VSS= ±5%Power-Supply Rejection4.7Reference compensation mode—externalCapacitive Load Required18Output Short-Circuit Current4TA= +25°C, IOUT= 0mA to 2mALoad Regulation
SYMBOLUNITSMINTYPMAXCONDITIONSPARAMETERInput Voltage Range (Note 7)VVSSVDD
Input Capacitance (Note 6)pF4580
Input Leakage CurrentμA±10VIN= VSSto VDDMAX191_C
VREF Output VoltageV4.0764.0964.116TA= +25°C
Small-Signal BandwidthMHz2MAX191_E
Output Current Capability (Note 9)mA2TA= +25°C
VREF Output Tempco (Note 8)ppm/°CMAX191_M
ANALOG INPUT
INTERNAL REFERENCE
REFERENCE INPUT
LOGIC INPUTS
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%, VSS= 0V or -5V ±5%, fCLK= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, TA= TMINto TMAX, unless otherwise noted.) (Note 1)
PARAMETERPulse Width
CONDITIONSUNITSMAX191C/E
MINTYPMAX
150ns
MAX191M
MINTYPMAX
160= 100pF120ns100ns120t8
110120100nst7
10012080nst60CSto RDHold Time0nst5
SYMBOLto BUSYDelayto RD Setup Time0ns= 50pF120ns
TIMING CHARACTERISTICS (Figures 6–10)(VDD=5V ±5%, VSS= 0V or -5V ±5%, TA= TMINto TMAX, unless otherwise noted.) (Note 14)
Aperture DelayJitter < 50ps25nst1222
200200200nst10
HBEN to RDHold Time00ns0t9
Data Access Time (Note 15)
Data Setup Time After
BUSY(Note 15)
Bus-Relinquish Time (Note 16)
HBEN to RDSetup Time
Delay Between Read
Operations (Note 6)
200230ns260t13CLK to BUSYDelay (Note 6)
100130ns150t14SCLKOUTto SSTRB
Rise Delay
SCLKOUTto SSTRB
Fall Delay100130ns150t15
= +25°C
MINTYPMAXt11Delay Between Conversions
VSSV-5.250Negative Supply Voltage
IDD
VDD
VOL
VOH
COUT20500.4IOUT= 1.6mA354.755.25Positive Supply Voltage
Output Low Voltage
SYMBOL= low= high/float= low
LSB±1/2FS change, VSS= -5V ±5%Negative Supply Rejection (Note 13)
LSB±1/2FS change, VDD= 5V ±5%Positive Supply Rejection (Note 13)
ISSμA
4.0IOUT= -200μAOutput High Voltage20
CS = RD= VDD,
AIN = 5V, D0/D8–D7/
DOUT = 0V or VDD,
HBEN = PAR = BIP
= 0V or VDD
Positive Supply Current= high/float
Three-State Output
Capacitance (Note 6)100
Negative Supply Current
UNITS±10D0/D8-D7/DOUT
MINTYPMAXCONDITIONSThree-State Leakage Current
PARAMETER
LOGIC OUTPUTS
POWER REQUIREMENTS
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
PARAMETERSCLK to SCLKOUTDelay
CONDITIONSUNITSto DOUT Three-State100ns
SYMBOLor RDSetup Timeor RDHold Timens
150ns
t20
t19
t17
t16
TIMING CHARACTERISTICS (Figures 6–10) (continued)(VDD=5V ±5%, VSS= 0V or -5V ±5%, TA= TMINto TMAX, unless otherwise noted.) (Note 14)
MAX191C/E
MINTYPMAXMAX191M
MINTYPMAX
310350SCLK to SSTRB Delay260nst23
260280SCLK to DOUT Delay240nst22
130SCLKOUTto DOUT Delay100nst21150
Note 1:Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
Note 2:VDD= 5V, VSS= 0V, FS = VREF.
Note 3:FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Note 4:Gain-Error Tempco = ΔGE is the gain-error change from TA= +25°C to TMINor TMAX.
Note 5:Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6:Guaranteed by design, not production tested.
Note 7:AIN+, AIN- must not exceed supplies for specified accuracy.
Note 8:VREF TC = ΔT, where ΔVREF is reference-voltage change from TA= +25°C to TMINor TMAX.
Note 9:Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
Note 10:REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
Note 11:This current is included in the PDsupply current specification.
Note 12:Floating the PDpin guarantees external compensation mode.
Note 13:VREF= 4.096V, external reference.
Note 14:All input control signals are specified with tr= tf= 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
Note 15:t3and t6are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 16:t7is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
= +25°C
MINTYPMAX
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
__________________________________________Typical Operating CharacteristicsCLOCK FREQUENCY
vs. TIMING CAPACITOR
TIMING CAPACITOR (nF)
(M
SEE FIGURE 5
TA = +25˚C
GR191-A
TEMPERATURE (°C)
(m
VDD = +5V
VSS = -5V
PD = 0V
ISS
IDD
POWER-DOWN SUPPLY CURRENT
vs. TEMPERATUREGR191-B
TEMPERATURE (°C)
ISS
(m
NEGATIVE SUPPLY CURRENT
vs. TEMPERATURE
GR191-C
TEMPERATURE (°C)
(m
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
GR191-D
1kHz FFT PLOT
191-E
FREQUENCY (kHz)
(d
-20fIN = 1kHz
fS = 100kHz
SNR = 72dB
TA = +25˚C
-94.3dB-96.1dB-98.0dB-93.8dB
10kHz FFT PLOT
GR191-F
FREQUENCY (kHz)
(d
-20fIN = 10kHz
fS = 100kHz
SNR = 71.2dB
TA = +25˚C202535
-86.0dB-90.8dB
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down
Pin DescriptionClock Input/Serial Clock Input in serial mode. An external TTL-/CMOS-compatible clock may be applied to
this pin, or a capacitor (120pF nominal) may be connected between CLK and DGND to operate the internal
oscillator.
High-Byte Enable Input. In parallel mode, HBEN = high multiplexes the 4 MSBs of the conversion result
into the lower bit outputs. HBEN = high also disables conversion starts. HBEN = low places the 8 LSBs
onto the data bus. In serial mode, HBEN = low enables SCLKOUTto operate during the conversion only,
HBEN = high enables SCLKOUTto operate continuously, provided CSis low.
Chip-Select Input must be low for the ADC to recognize RDand HBEN inputs in parallel mode. The falling
edge of CSstarts a conversion in serial mode. CS= high in serial mode forces SCLKOUT, SSTRB, and
DOUT into a high-impedance state.
Read Input. In parallel mode, a low signal starts a conversion when CSand HBEN are low (memory
mode). RD also enables the outputs when CSis low. In serial mode, RD= low enables SCLKOUTand
SSTRB when CS is low. RD= high forces SCLKOUTand SSTRB into a high-impedance state.
D6/SCLKOUTAnalog GroundAGNDPositive Supply, +5V ±5%VDDCLK/SCLKSets the output mode. PAR = high selects parallel output mode. PAR = low selects serial output mode.PARHBENCSRDThree-State Data Output/Data Output in serial modeD7/DOUTThree-State Data OutputsD2/D10Three-State Data Outputs: MSB = D11D3/D11Three-State Data OutputD4Three-State Data Output/Serial Strobe Output in serial modeD5/SSTRBThree-State Data Output/Serial Clock Output in serial modeThree-State Data Outputs: LSB = D0D0/D8Three-State Data OutputsD1/D9Digital GroundDGND
Power-Down Input. A logic low at PDdeactivates the ADC—only the bandgap reference is active. A logic
high selects normal operation, internal-reference compensation mode. An open-circuit condition selects
normal operation, external-reference compensation mode.
PINBUSYOutput is low during a conversion.BUSY
BIP = low selects unipolar mode
BIP = high selects bipolar mode (see Gain and Offset Adjustment section)BIP
Reference Adjust. Connect to VDDto use an extended reference at VREF.REFADJ
Reference-Buffer Output for Internal Reference. Input for external reference when REFADJ is connected to
VDD.VREF
Analog Input Return. Pseudo-differential (see Gain and Offset Adjustment section).AIN-
Sampled Analog InputAIN+
Negative Supply, 0V to -5.25VVSS
FUNCTIONNAME
_______________Detailed DescriptionThe MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (μPs), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1μF capacitor from AIN- to AGND.
Analog Input—Track/HoldThe T/H enters its tracking mode when the ADC is des-
elected (CSpin is held high and BUSYpin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-DownCL
DGND
+5V
DGND
a. High-Z to VOH and VOL to VOHb. High-Z to VOL and VOH to VOLFigure 1. Load Circuits for Access Time10pF
DGND
+5V
10pF
DGND
a. VOH to High-Zb. VOL to High-ZFigure 2. Load Circuits for Bus-Relinquish Time
AIN+
AIN-
VREF
REFADJ
AGND
BIP
BUSY
DO/DB
D1/D9
DGNDVSS
VDD
CLK/SCLK
PAR
HBEN
D7/DOUT
D6/SCLKOUT
D5/SSTRB
D3/D11
D2/D10
OPEN
OUTPUT
STATUS
4.7mF0.1mF
0.1mF
0V TO -5V
+5V
SERIAL/PARALLEL
INTERFACE MODEP CONTROL
INPUTSMAX191
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.P DATA BUS
Figure 3. Operational Diagram
various interface modes.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by: tACQ = 10(RS+ RIN)CHOLD(but never less
than 2μs), where RIN= 2kΩ, RS = source impedance of
the input signal, and CHOLD= 32pF (see Figure 4).
Input BandwidthThe ADC’s input tracking circuitry has a 1MHz typical
large-signal bandwidth characteristic, and a 30V/μs
slew rate. It is possible to digitize high-speed transients
and measure periodic signals with bandwidths exceed-
ing the ADC’s sample rate of 100ksps by using under-
sampling techniques. Note that if undersampling is
used to measure high-frequency signals, special care
must be taken to avoid aliasing errors. Without ade-
quate input bandpass filtering, out-of-band signals and
noise may be aliased into the measurement band.
Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand VSS , allow AIN+ to swing from (VSS- 0.3V) toDD+ 0.3V) with no risk of damage to the ADC.
However, for accurate conversions near full scale, AIN+
should not exceed the power supplies by more than
50mV because ADC accuracy is affected when the pro-
tection diodes are even slightly forward biased.
Digital Interface
Starting a ConversionIn parallel mode, the ADC is controlled by the CS, RD,
and HBEN inputs, as shown in Figure 6. The T/H
enters hold mode and a conversion starts at the falling
edge of CSand RDwhile HBEN (not shown) is low.
BUSYgoes low as soon as the conversion starts. On
the falling edge of the 13th input clock pulse after the
conversion starts, BUSYgoes high and the conversion
result is latched into three-state output buffers. In seri-
al mode, the falling edge of CSinitiates a conversion,
and the T/H enters hold mode. Data is shifted out seri-
ally as the conversion proceeds (Figure 10). See the
Parallel Digital-Interface Mode andSerial-Interface
Modesections for details.
Internal/External ClockFigure 5 shows the MAX191 clock circuitry. The ADC
includes internal circuitry to generate a clock with an
external capacitor. As indicated in the Typical
Operating Characteristics, a 120pF capacitor con-
nected between the CLK and DGND pins generates
a 1MHz nominal clock frequency (Figure 5).
Alternatively, an external clock (between 100kHz and
1.6MHz) can be applied to CLK. When using an exter-
nal clock source, acceptable clock duty cycles are
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-Down12-BIT DAC
TRACKCHOLDCOMPARATOR
HOLD32pF
HOLD
CSWITCH
10pF
CPACKAGE
5pF
AIN +
AIN -
RIN
Figure 4. Equivalent Input Circuit
CEXT
DGND
CLK
+1.6V
CLOCK
MAX191
NOTE: CEXT = 120pF GENERATES 1MHz NOMINAL CLOCKFigure 5. Internal Clock Circuit
between 45% and 55%.
Clock and Control SynchronizationFor best analog performance on the MAX191, the clock
should be synchronized to the conversion start signals
(CSand RD) as shown in Figure 6. A conversion should
not be started in the 50ns before a clock edge nor in
the 100ns after it. This ensures that CLK transitions are
not coupled to the analog input and sampled by the
T/H. The magnitude of this feedthrough can be a few
millivolts. When the clock and conversion start signals
are synchronized, small end-point errors (offset and
full-scale) are the most that can be generated by clock
feedthrough. Even these errors (which can be trimmed
out) can be avoided by ensuring that the start of a con-
version (RDor CSfalling edge) does not occur close to
a clock transition (Figure 6), as described above.
Parallel Digital-Interface Mode
Output-Data FormatThe data output from the MAX191 is straight binary in
the unipolar mode. In the bipolar mode, the MSB is
inverted (see Figure 22). The 12 data bits can be out-
put either in two 8-bit bytes or as a serial output. Table
1 shows the data-bus output format.
A 2-byte read uses outputs D7–D0. Byte selection is
controlled by HBEN. When HBEN is low, the lower 8
bits appear at the data outputs. When HBEN is high,
the upper 4 bits appear at D0-D3 with the leading 4 bits
low in locations D4–D7.
Timing and ControlConversion-start and data-read operations are con-
trolled by the HBEN, CS, and RDdigital inputs. A logic
low is required on all three inputs to start a conversion,
and once the conversion is in progress it cannot be
restarted. BUSYremains low during the entire conver-
sion cycle.
The timing diagrams of Figures 7–10 outline two paral-
lel-interface modes and one serial mode.
Slow-Memory ModeIn slow-memory mode, the device appears to the μP as
a slow peripheral or memory. Conversion is initiated
with a read instruction (see Figure 7 and Table 2). Set
the PAR pin high for parallel interface mode. Beginning
with HBEN low, taking CSand RDlow starts the con-
version. The analog input is sampled on the falling
edge of RD. BUSYremains low while the conversion is
in progress. The previous conversion result appears at
the digital outputs until the end of conversion, when
BUSYreturns high. The output latches are then updat-
ed with the newest results of the 8 LSBs on D7–D0. A
second read operation with HBEN high places the 4
MSBs, with 4 leading 0s, on data outputs D7–D0. The
second read operation does not start a new conversion
because HBEN is high.
ROM ModeAs in slow-memory mode, D7–D0 are used for 2-byte
reads. A conversion starts with a read instruction with
HBEN and CSlow. The T/H samples the input on the
falling edge of RD(see Figure 8 and Table 3). PAR is set
high. At this point the data outputs contain the 8 LSBs
from the previous conversion. Two more read operations
are needed to access the conversion result. The first
occurs with HBEN high, where the 4 MSBs with 4 leading
0s are accessed. The second read, with HBEN low, out-
puts the 8 LSBs and also starts a new conversion.
Figure 9 and Table 4 show how to read output data
within one conversion cycle without starting another
conversion. Trigger the falling edge of a read on the ris-
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-DowntCONV
CS + RD
BUSY
t16
CLK
t17
t13t2
tCONV
Figure 6. CS, RD, and CLK Synchronous Operation
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-DownDATA
HOLD*
TRACK
NEW DATA
D11–D8
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
tCONV
BUSY
HBEN
t12
NEW DATA
D7–D0
OLD DATA
D7–D0t7t3t7
t10
t11
t10
t12t1t5t5t8t9
Figure 7. Slow-Memory Mode Timing
HBEN
BUSY
DATA
HOLD*
TRACK
t12t7
t12t7t3t7
t11
t10t2t2tCONVt4t1t5t4t1t5t4t1t9t8t9t8t9
OLD DATA
D7–D0
NEW DATA
D11–D8
NEW DATA
D7–D0
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High.
Figure 8. ROM Mode Timing
Low-Power, 12-Bit Sampling ADCith Internal Reference and Power-DownHBEN
CLK
BUSY
DATA
HOLD*
TRACKt4t5tCONV
t12t7t3t7
t10t8
*INTERNAL SIGNAL. TRACKING INPUT SIGNAL WHEN HOLD = Low, HOLDING WHEN HOLD = High
NEW DATA
D7–D0
NEW DATA
D11–D8t3
OLD DATA
D7–D0
Figure 9. ROM Mode Timing, Reading Data without Starting a Conversion
SCLKOUT
SCLK
SSTRB
DOUT
t20t20
t22
t16
t23
t14
t15
t22
t21
t19
THREE STATE
THREE STATE
t23
t17
t12
12 SCLK CYCLESHOLD
TRACK
THREE STATE
THREE STATE
Figure 10. Serial-Interface Mode Timing Diagram (RD= low)
