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MAX1907AETL-MAX1907AETL+-MAX1907AETL+T-MAX1981AETL+
Quick-PWM Master Controllers for Voltage-Positioned CPU Core Power Supplies (IMVP-IV)
General DescriptionThe MAX1907A/MAX1981A are single-phase, Quick-
PWM™ master controllers for IMVP-IV™ CPU core sup-
plies. Multi-phase operation is achieved using a
Quick-PWM slave controller (MAX1980). Multiphase
operation reduces input ripple current requirements
and output voltage ripple while easing component
selection and layout difficulties. The MAX1907A/
MAX1981A include active voltage positioning with
adjustable gain and offset, reducing power dissipation
and bulk output capacitance requirements.
The MAX1907A/MAX1981A are intended for two differ-
ent notebook CPU core applications: either bucking
down the battery directly, or 5V system supply to create
the core voltage. The single-stage conversion method
allows these devices to directly step down high-voltage
batteries for the highest possible efficiency.
Alternatively, two-stage conversion (stepping down the
5V system supply instead of the battery) at higher
switching frequency provides the minimum possible
physical size.
The MAX1907A/MAX1981A meet the IMVP-IV specifica-
tions and include logic to interface with the CPU power
good signals from the VCCPand VCCMCHrails within the
system. The regulator features power-up sequencing,
automatically ramping up to the Intel-specified boot volt-
age. The MAX1907A/MAX1981A feature independent
four-level logic inputs for setting the boot voltage
(B0–B2) and the suspend voltage (S0–S2).
The MAX1907A/MAX1981A include output undervoltage
protection, thermal protection, and system power-OK
(SYSPOK) input/output. When any of these protection fea-
tures detect a fault, the MAX1907A/MAX1981A immedi-
ately shut down. Additionally, the MAX1907A includes
overvoltage protection.
The MAX1907A/MAX1981A are available in a thin 40-pin
QFNpackage.
ApplicationsIMVP-IV™ Notebook Computers
Single-Phase CPU Core Supply
Multiphase CPU Core Supply
Voltage-Positioned Step-Down Converters
Servers/Desktop Computers
FeaturesQuick-PWM Master ControllersMultiphase Conversion with Slave Controller
(MAX1980)Active Voltage Positioning with Adjustable Gain
and OffsetAdjustable Slew Rate Control±0.75% VOUTAccuracy Over Line, Load, and
Temperature6-Bit On-Board DAC (16mV Increments)0.700V to 1.708V Output Adjust RangeSelectable 200kHz/300kHz/550kHz/1000kHz
Switching Frequency2V to 28V Battery Input Voltage RangeDrive Large Synchronous Rectifier MOSFETsOutput Overvoltage Protection (MAX1907A Only)Undervoltage and Thermal Fault ProtectionPower Sequencing and Selectable Boot VoltageLow-Profile 40-Pin Thin QFN, 6mm ✕✕
6mm
Package
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Ordering Information
40-Pin,6mmx6mmThinQFN3938373612131415
TOP VIEW
MAX1907A
MAX1981A
VDDB0S2SHDNREFILIMVCC
DDOD1D2D3D4D5
PGND
OAIN+
OAIN-
CSP
CSN
DPSLP
NEGPOS
GND
TONTIMECLKENIMVPOKSYSPOK
SUS
BST
Pin Configuration19-2678; Rev 0; 9/02
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
IMVP-IV is a trademark of Intel Corp.
PARTTEMP RANGEPIN-PACKAGE
MAX1907AETL-40°C to +100°C40- QFN Thi n 6m m x 6m m
MAX1981AETL-40°C to +100°C40- QFN Thi n 6m m x 6m m
Typical Operating Circuit appears at end of data sheet.
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM= VCC, SUS = D5 = D1= D0= S0 = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= 0°C to +85°C, unlessotherwise specified.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +30V
VCC, VDDto GND.....................................................-0.3V to +6V
SYSPOK, IMVPOK, CLKENto GND.........................-0.3V to +6V
DPSLP, SUS, D0–D5 to GND...................................-0.3V to +6V
REF, ILIM, CSP, CSN to GND.....................-0.3V to (VCC+ 0.3V)
FB, POS, NEG, OAIN+, CC
OAIN- to GND.........................................-0.3V to (VCC+ 0.3V)
B0–B2, S0–S2, TON,
TIME to GND..........................................-0.3V to (VCC+ 0.3V)
DL, DDO, to PGND.....................................-0.3V to (VDD+ 0.3V)
DH to LX....................................................-0.3V to (VBST+ 0.3V)
SHDNto GND...........................................................-0.3 to +18V
BST to GND..............................................................-0.3 to +36V
LX to BST..................................................................-6V to +0.3V
GND to PGND.......................................................-0.3V to +0.3V
REF Short-Circuit Duration.........................................Continuous
Continuous Power DIssipation
40-Pin 6mm ✕6mm Thin QFN
(derate 26.3mW/°C above +70°C).............................2105mW
Operating Temperature Range.........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLERBattery Voltage, V+228Input Voltage RangeVCC, VDD4.55.5V
DAC codes from
1.276V to 1.708V-0.75+0.75
DAC codes from
0.844V to 1.260V-1.25+1.25DC Output Voltage Accuracy
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.444V to 0.828V-3.0+3.0
Line Regulation ErrorVCC = 4.5V to 5.5V, V+ = 4.5V to 28V5mV
IFBFB-1+1Input Bias CurrentIPOS, INEGPOS, NEG-0.2+0.2µA
POS, NEG Common-Mode
RangeDPSLP = GND02V
POS, NEG Differential RangeVPOS - VNEG, DPSLP = GND-200+200mV
POS, NEG Offset GainAOFFΔVFB/(VPOS - VNEG), (VPOS - VNEG) =
100mV, DPSLP = GND0.951.001.05mV/mV
POS, NEG Enable Time
Measured from the time DPSLP goes low to
the time in which POS, NEG affect a change
in the set point (VDAC)
0.1µs
640kHz nominal, RTIME = 23.5kΩ580640700
320kHz nominal, RTIME = 47kΩ295320345TIME Frequency Accuracy
64kHz nominal, RTIME = 235kΩ586470
kHz
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM= VCC, SUS = D5 = D1= D0= S0 = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= 0°C to +85°C, unlessotherwise specified.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSV+ = 5V, VFB = 1.2V, TON = GND
(1000kHz)250270290
TON = REF (550kHz)165190215
TON = open (300kHz)320355390
On-Time (Note 1)tON
V+ = 12V,
VFB = 1.2V
TON = VCC = (200kHz)465515565
TON = GND (1000kHz)300375ns
Minimum Off-Time (Note 1)tOFF(MIN)TON = VCC, open or REF (200kHz, 300kHz,
or 550kHz)400475ns
DDO Delay TimetDDO
Measured from the time FB reaches the
voltage set by S0–S2, clock speed set by
RTIMEclks
SKIP Delay TimetSKIP
Measured from the time when DDO is
asserted to the time in which the controller
begins pulse-skipping operationclks
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point1.32.0mA
Quiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation0.15µA
Quiescent Battery Supply
Current (V+)IV+Measured at V+2140µA
Shutdown Supply Current (VCC)Measured at VCC, SHDN = GND0.15µA
Shutdown Supply Current (VDD)Measured at VDD, SHDN = GND0.15µA
Shutdown Battery Supply
Current (V+)
Measured at V+, SHDN = GND,
VCC = VDD = 0 or 5V0.15µA
Reference VoltageVREFVCC = 4.5V to 5.5V, IREF = 01.9902.0002.010V
Reference Load RegulationΔVREFIREF = -10µA to 100µA-10+10mV
FAULT PROTECTIONOutput Overvoltage
Protection Threshold
Measured at FB with respect to unloaded
output voltage, DAC code = 0.7V to 1.708V131619%
Output Overvoltage
Propagation DelaytOVPFB forced 2% above trip threshold10µs
Output Undervoltage
Protection Threshold
With respect to unloaded output voltage
DAC Code = 0.7V to 1.708V677073%
Output Undervoltage
Propagation DelaytUVPFB forced 2% below trip threshold10µs
Output Fault Blanking TimetBLANKThe clock speed is set by RTIME (Note 2)32clks
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM= VCC, SUS = D5 = D1= D0= S0 = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= 0°C to +85°C, unlessotherwise specified.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLower threshold
(undervoltage)-12-10-8
IMVPOK, CLKEN Threshold
SYSPOK = VCC;
measured at FB with
respect to unloaded
output voltage
Upper threshold
(overvoltage)81012
CLKEN DelaytCLKENFB in regulation, measured from the rising
edge of SYSPOK305090µs
IMVPOK, CLKEN Transition
Blanking Time
Measured from the time when FB reaches
the voltage set by the DAC code, clock
speed set by RTIMEclks
IMVPOK DelaytIMVPOKFB in regulation, measured from the falling
edge of CLKEN357ms
IMVPOK, CLKEN, Output Low
VoltageISINK = 3mA0.3V
IMVPOK, CLKEN, Leakage
CurrentHigh state, IMPOK, CLKEN forced to 5.5V1µA
VCC Undervoltage
Lockout ThresholdVUVLO(VCC)Rising edge, hysteresis = 20mV,
PWM disabled below this level4.04.4V
Thermal Shutdown ThresholdHysteresis = 10°C160°C
CURRENT LIMITCurrent-Limit Threshold Voltage
(Positive, Default)CSP - CSN, ILIM = VCC475053mV
VILIM = 0.3V273033Current-Limit Threshold Voltage
(Positive, Adjustable)CSP - CSNVILIM = 1V97100103mV
Current-Limit Threshold Voltage
(Negative)
CSP - CSN; ILIM = VCC, SUS = GND and
DPSLP = VCC-68-63-58mV
Current-Limit Threshold Voltage
(Zero Crossing)GND - LX; SUS = VCC or DPSLP = GND4mV
CSP, CSN Input Ranges02V
CSP, CSN Input CurrentVCSP = VCSN = 0 to 5V-1+1µA
ILIM Input CurrentVILIM = 0 to 5V0.01200nA
Current-Limit Default
Switchover ThresholdILIM3VCC - 1VCC - 0.4V
GATE DRIVERSDH Gate-Driver On-ResistanceRON(DH)BST - LX forced to 5V1.24.0Ω
High state (pullup)1.24.0DL Gate-Driver On-ResistanceRON(DL)Low state (pulldown)0.51.5Ω
DH Gate-Driver Source/Sink
CurrentDH forced to 2.5V, BST - LX forced to 5V1.6A
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM= VCC, SUS = D5 = D1= D0= S0 = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= 0°C to +85°C, unlessotherwise specified.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDL Gate-Driver Source CurrentDL forced to 2.5V2A
DL rising35Dead TimeDH rising26ns
VOLTAGE-POSITIONING AMPLIFIERInput Offset VoltageVOSVCM = 0-1+1mV
Input Bias CurrentIBIASOAIN+, OAIN-<0.1200nA
Op Amp Disable ThresholdOAIN-3VCC - 1VCC - 0.4V
Common-Mode Input
Voltage RangeVCMGuaranteed by CMRR test02.5V
Common-Mode Rejection RatioCMRRVOAIN+ = VOAIN- = 0 to 2.5V70115dB
Power-Supply Rejection RatioPSRRVCC = 4.5V to 5.5V75100dB
Large-Signal Voltage GainAOARL = 1kΩ to VCC/280112
VCC - VOH100300Output Voltage Swing|VOAIN+ - VOAIN-| ≤ 10mV,
RL = 1kΩ to VCC/2VOL70200mV
Input Capacitance11pF
Gain-Bandwidth Product3MHz
Slew Rate0.3V/µs
Capacitive-Load StabilityNo sustained oscillations400pF
LOGIC AND I/OLogic Input High VoltageVIHSUS, DPSLP, SHDN, SYSPOK2.4V
Logic Input Low VoltageVILSUS, DPSLP, SHDN, SYSPOK0.8V
Logic Input CurrentSUS, DPSLP, SHDN, SYSPOK-1+1µA
SHDN No Fault ThresholdTo enable No-Fault Mode1215V
DAC Input High VoltageVVID(HIGH)D0–D50.7V
DAC Input Low VoltageVVID(LOW)D0–D50.3V
DAC Input CurrentD0–D5-1+1µA
Driver-Disable Output
High VoltageDDO, ILOAD = 1mA2.4V
Driver-Disable Output
Low VoltageDDO, ILOAD = 1mA0.3V
HighVCC - 0.4
Open3.153.85
REF1.652.35Four-Level Input Logic LevelsTON, S0–S2, B0–B2
Low0.5
Four-Level Input CurrentTON, S0–S2, B0–B2 forced to GND or VCC-3+3µA
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM = VCC, SUS = D5 = D1= D0 = SO = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= -40°C to +100°C, unlessotherwise specified.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBattery voltage, V+228Input Voltage RangeVCC, VDD4.55.5V
DAC codes from
1.276V to 1.708V-1.00+1.00
DAC codes from
0.844V to 1.260V-1.5+1.5DC Output Voltage Accuracy
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.444V to 0.828V-3.5+3.5
POS, NEG Offset GainAOFFΔVFB/(VPOS - VNEG), (VPOS - VNEG) =
100mV, DPSLP = GND0.951.05mV/mV
640kHz nominal, RTIME = 23.5kΩ580700
320kHz nominal, RTIME = 47kΩ295305TIME Frequency Accuracy
64kHz nominal, RTIME = 235kΩ5870
kHz
V+ = 5V, VFB = 1.2V, TON = GND
(1000kHz)250290
TON = REF
(550kHz)165215
TON = open
(300kHz)320390
On-Time (Note 1)tON
V+ = 12V,
VFB = 1.2V
TON = VCC
(200kHz)465565
TON = GND (1000kHz)375ns
Minimum Off-Time (Note 1)tOFF(MIN)TON = VCC, open, or REF (200kHz, 300kHz,
or 550kHz)475ns
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point2.0mA
Quiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation20µA
Quiescent Battery
Supply Current (V+)IV+Measured at V+40µA
Shutdown Supply Current (VCC)Measured at VCC, SHDN = GND20µA
Shutdown Supply Current (VDD)Measured at VDD, SHDN = GND20µA
Shutdown Battery
Supply Current (V+)
Measured at V+, SHDN = GND,
VCC = VDD = 0 or 5V20µA
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM = VCC, SUS = D5 = D1= D0 = SO = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= -40°C to +100°C, unlessotherwise specified.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSReference VoltageVREFVCC = 4.5V to 5.5V, IREF = 01.9852.015V
FAULT PROTECTIONOutput Overvoltage Protection
Threshold
Measured at FB with respect to unloaded
output voltage1319%
Output Undervoltage Protection
ThresholdWith respect to unloaded output voltage6773%
lower threshold
(undervoltage)-12-8%
IMVPOK, CLKEN Threshold
SYSPOK = VCC;
measured at FB with
respect to unloaded
output voltage
upper threshold
(overvoltage)+8+12%
CLKEN DelaytCLKENFB in regulation, measured from the rising
edge of SYSPOK30µs
IMVPOK DelaytIMVPOKFB in regulation, measured from the falling
edge of CLKEN3ms
VCC Undervoltage
Lockout ThresholdVUVLO(VCC)Rising edge, hysteresis = 20mV, PWM
disabled below this level3.954.45V
CURRENT LIMITCurrent-Limit Threshold Voltage
(Positive, Default)CSP - CSN, ILIM = VCC4555mV
VILIM = 0.3V2535Current-Limit Threshold Voltage
(Positive, Adjustable)CSP - CSNVILIM = 2V (REF)95105mV
Current-Limit Threshold Voltage
(Negative)
CSP - CSN; ILIM = VCC, SUS = GND and
DPSLP = VCC-70-56mV
GATE DRIVERSDH Gate-Driver On-ResistanceRON(DH)BST - LX forced to 5V4.5Ω
High state (pullup)4.5DL Gate-Driver On-ResistanceRON(DL)Low state (pulldown)2.0Ω
VOLTAGE-POSITIONING AMPLIFIERInput Offset VoltageVOSVCM = 0-2+2mV
VCC - VOH300Output Voltage Swing|VOAIN+ - VOAIN-| ≤ 10mV,
RL = 1kΩ to VCC/2VOL200mV
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VDPSLP= VBI= VOAIN- = 5V, VFB= VCSP= VCSN= VOAIN+= VNEG= VPOS
= 1.26V, ILIM = VCC, SUS = D5 = D1= D0 = SO = S1 = S2 = B0 = GND, VD4= VD3= VD2= 1V, VB2= 2V. TA
= -40°C to +100°C, unlessotherwise specified.)
Note 1:On-time specifications are measured from 50% to 50% at the DH pin, with LX forced to GND, BST forced to 5V, and a
500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due
to MOSFET switching speeds.
Note 2:The output fault blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During power-up, the regulation voltage is set by the boot DAC code (B0–B2). During normal operation (SUS = low), the
regulation voltage is set by the VID DAC inputs (D0–D5). During suspend mode (SUS = high), the regulation voltage is set
by the suspend DAC inputs (S0–S2).
Note 3:Specifications to TA= -40°C to +100°C are guaranteed by design and are not production tested.
PARAMETERSYMBOLCONDITIONSMINMAXUNITSVCC – VOH300Output Voltage Swing|VOAIN+ – VOAIN-| ≤ 10mV,
RL = 1kΩ to VCC/2VOL200
LOGIC AND I/ODAC Input High VoltageVVID(HIGH)D0–D50.7V
DAC Input Low VoltageVVID(LOW)D0–D50.3V
High VCC - 0.4
Open3.153.85
REF1.652.35Four-Level Input Logic LevelsTON, S0–S2, B0–B2
Low0.5
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Typical Operating Characteristics(Circuit of Figure 1, V+ = 12V, VCC= VDD= 5V, B0–B2 set to 1.276V, S0–S2 set to 0.748V.)
VOLTAGE-POSITIONED OUTPUT
vs. LOAD CURRENT (VOUT = 1.436V)MAX1907A/81A toc01
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)302010
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.436V)
MAX1907A/81A toc02
LOAD CURRENT (A)
EFFICIENCY (%)1
VIN = 20V
VIN = 12V
VIN = 5V
VIN = 8V
MAX1907A/81A toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)2015105
VOLTAGE-POSITIONED OUTPUT
vs. LOAD CURRENT (VOUT = 0.844V)
EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.844V)
MAX1907A/81A toc04
LOAD CURRENT (A)
EFFICIENCY (%)1
VIN = 20V
VIN = 12V
VIN = 5V
VIN = 8V
MAX1907A/81A toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)15105
VOLTAGE-POSITIONED OUTPUT
vs. LOAD CURRENT (VOUT = 0.748V)
SUS = VCC
EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.748V)MAX1907A/81A toc06
LOAD CURRENT (A)
EFFICIENCY (%)1
VIN = 20V
VIN = 12V
VIN = 5V
VIN = 8V
SUS = VCC
OUTPUT VOLTAGE SHIFT
vs. TEMPERATUREMAX1907A/81A toc07
TEMPERATURE (°C)
OUT
(mV)6040200-20
NO LOAD
20A LOAD
FREQUENCY vs. LOAD CURRENTMAX1907A/81A toc08
LOAD CURRENT (A)
FREQUENCY (kHz)2051015
FORCED PWM
SKIP OPERATION
SINGLE PHASE
FREQUENCY vs. INPUT VOLTAGEMAX1907A/81A toc09
INPUT VOLTAGE (V)
FREQUENCY (kHz)2015105
SINGLE PHASE
IOUT = 20A
NO LOAD
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Typical Operating Characteristics (continued)(Circuit of Figure 1, V+ = 12V, VCC= VDD= 5V, B0–B2 set to 1.276V, S0–S2 set to 0.748V.)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PULSE SKIPPING)MAX1907A/81A toc12
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)2015105
MAX1907A/MAX1981A ONLY
DPSLP = GND
ICC + IDD
OUTPUT OFFSET VOLTAGE
vs. POS-NEG DIFFERENTIAL VOLTAGEMAX1907A/81A toc14
POS-NEG DIFFERENTIAL VOLTAGE (mV)
OUTPUT OFFSET VOLTAGE (mV)
1.260V OUTPUT VOLTAGE DISTRIBUTION
MAX1907A/81A toc15
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
REFERENCE VOLTAGE DISTRIBUTION
MAX1907A/81A toc16
SAMPLE PERCENTAGE (%)
POS-NEG OFFSET GAIN DISTRIBUTION
MAX1907A/81A toc17
SAMPLE PERCENTAGE (%)
0.1101001000110,000
VOLTAGE-POSITIONING AMPLIFIER
GAIN AND PHASE vs. FREQUENCY MAX1907A/81A toc18
FREQUENCY (kHz)
GAIN (dB)
PHASE (DEGREES)
GAIN
PHASE
FREQUENCY vs. TEMPERATUREMAX1907A/81A toc10
TEMPERATURE (°C)
FREQUENCY (kHz)6040200-20
20A LOAD
NO LOAD
SINGLE PHASE
VOUT = 1.436V
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATUREMAX1907A/81A toc11
TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (A)6040200-20
SINGLE PHASE
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FORCED-PWM MODE)MAX1907A/81A toc12
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)2015105
ICC = IDD
MAX1907A/MAX1981A ONLY
SOFT-STARTMAX1907A/81A toc22
100μs/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 0 to 0.844V, 500mV/div
C. ILM, 10A/div
D. ILS, 10A/div
80mΩLOADVBOOT
VID
IMPVOK DELAYMAX1907A/81A toc23
1ms/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 0 to 0.844V, 500mV/div
C. IMPVOK 5V/div
D. CLKEN, 5V/div
VBOOT
POWER-UP SEQUENCE
(HIGHEST FREQUENCY)MAX1907A/81A toc20
100μs/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 0 to 1.436V, 500mV/div
C. DDO, 5V/div
D. CLKEN, 5V/div
VBOOT
VID
POWER-UP SEQUENCE
(LOWEST FREQUENCY)MAX1907A/81A toc21
100μs/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 0 to 0.844V, 500mV/div
C. DDO, 5V/div
D. CLKEN, 5V/div
NOLOAD
VBOOTVID
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
VPS AMPLIFIER OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGEMAX1907A/81A toc19
COMMON-MODE VOLTAGE (V)
OFFSET VOLTAGE (321
VPS AMPLIFIER
DISABLED
SHUTDOWN SEQUENCEMAX1907A/81A toc24
100μs/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 1.436V to 0, 1V/div
C. IMPVOK 5V/div
D. CLKEN, 5V/div
E. DDO, 5V/div
1.436V
Typical Operating Characteristics (continued)(Circuit of Figure 1, V+ = 12V, VCC= VDD= 5V, B0–B2 set to 1.276V, S0–S2 set to 0.748V.)
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
SOFT SHUTDOWNMAX1907A/81A toc25
40μs/div
A. VSHDN = 0 to 5V, 5V/div
B. VOUT = 0.844V to 0, 1V/div
C. ILM, 10A/div
D. ILS,10A/div
80mΩLOAD
ENTERING DEEP-SLEEP MODEMAX1907A/81A toc26
20μs/div
A. VDPSLP = 0 to 5V, 5V/div
B. VOUT = 1.436V to 1.398V, 50mV/div
C. MAX1907A/MAX1981A LX, 10V/div
D. MAX1980 LX, 10V/div
SUS=GND,IOUT=1.0A
1.398V
1.436V
EXITING DEEP-SLEEP MODEMAX1907A/81A toc27
20μs/div
A. VDPSLP = 0 to 5V, 5V/div
B. VOUT = 1.398V to 1.436V, 50mV/div
C. MAX1907A/MAX1981A LX, 10V/div
D. MAX1980 LX, 10V/div
SUS=GND,IOUT=1.0A
1.398V
1.436V
ENTERING SUSPEND MODEMAX1907A/81A toc28
20μs/div
A. VSUS = 0 to 5V, 5V/div
B. VOUT = 1.398V to 0.748V, 500mV/div
C. MAX1907A/MAX1981A LX, 10V/div
D. MAX1980 LX, 10V/div
DPSLP=GND,IOUT=0.5A
0.748V
1.398V
EXITING SUSPEND MODEMAX1907A/81A toc29
20μs/div
A. VSUS = 0 to 5V, 5V/div
B. VOUT = 0.748V to 1.398V, 500mV/div
C. MAX1907A/MAX1981A LX, 10V/div
D. MAX1980 LX, 10V/div
DPSLP=GND,IOUT=0.5A
0.748V
1.398V
LOAD TRANSIENT
(LOWEST FREQUENCY)MAX1907A/81A toc30
20μs/div
A. IOUT = 0 to 10A, 10A/div
B. VOUT = 0.844V (NO LOAD), 50mV/div
C. ILM, 10A/div
D. ILS, 10A/div
0.844V
10A
Typical Operating Characteristics (continued)(Circuit of Figure 1, V+ = 12V, VCC= VDD= 5V, B0–B2 set to 1.276V, S0–S2 set to 0.748V.)
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
LOAD TRANSIENT
(HIGHEST FREQUENCY)MAX1907A/81A toc31
20μs/div
A. IOUT = 0 to 30A, 20A/div
B. VOUT = 1.436V (NO LOAD), 100mV/div
C. ILM, 10A/div
D. ILS, 10A/div
1.436V
30A
DYNAMIC VID TRANSITION
(DO = 16mV)MAX1907A/81A toc32
20μs/div
A. VDO = 0 to 1V, 1V/div
B. VOUT = 1.436V to 1.420V,, 20mV/div
C. ILM, 10A/div
D. ILS, 10A/div
1.436V
DYNAMIC VID TRANSITION
(D3 = 128mV)MAX1907A/81A toc33
40μs/div
A. VD3 = 0 to 1V, 1V/div
B. VOUT = 1.436V to 1.308V, 100mV/div
C. ILM, 10A/div
D. ILS, 10A/div
1.436V
1.308V
Typical Operating Characteristics (continued)(Circuit of Figure 1, V+ = 12V, VCC= VDD= 5V, B0–B2 set to 1.276V, S0–S2 set to 0.748V.)
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Pin Description
PINNAMEFUNCTION1, 2, 3B0–B2 Boot-Mode Voltage Select Inputs. B0–B2 are four-level digital inputs that select the boot-mode VID code
(Table 6) for the boot-mode multiplexer inputs. During power-up, the boot-mode VID code is delivered to
the DAC (see the Internal Multiplexers section).
4, 5, 6S0–S2 Suspend-Mode Voltage Select Inputs. S0–S2 are four-level digital inputs that select the suspend-mode VID
code (Table 5) for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID code is
delivered to the DAC (see the Internal Multiplexers section).SHDNShutdown Control Input. This input cannot withstand the battery voltage. Connect to VCC for normal
operation. Connect to ground to put the IC into its 10µA (max) shutdown state. During the transition from
normal operation to shutdown the output voltage is ramped down at the output voltage slew rate
programmed by the TIME pin. In shutdown mode, DL is forced to VDD to clamp the output to ground.
Forcing SHDN to 12V~15V disables both overvoltage protection and undervoltage protection circuits, and
clears the fault latch. Do not connect SHDN to >15V.REF 2V Reference Output. Bypass to GND with 0.22µF or greater ceramic capacitor. The reference can source
50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load
regulation error.ILIM Current-Limit Adjustment. The current-limit threshold defaults to 50mV if ILIM is tied to VCC. In adjustable
mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM over a 100mV to 1.5V
range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V.VCCAnalog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a
series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC as possible.GND Analog GroundCC Integrator Capacitor Connection. Connect a 47pF to 1000pF (270pF typ) capacitor from CC to GND to set
the integration time constant.POS Feedback Offset Adjust Positive Input. The output shifts by 100% (typ) of the differential input voltage
appearing between POS and NEG when DPSLP is low. The common-mode range of POS and NEG is 0 to
2V. POS and NEG should be generated from resistor dividers from the output.NEG Feedback Offset Adjust Negative Input. The output shifts by 100% (typ) of differential input voltage
appearing between POS and NEG when DPSLP is low. The common-mode range of POS and NEG is 0 to
2V. POS and NEG should be generated from resistor dividers from the output.FB Feedback Input. FB is internally connected to both the feedback input and the output of the voltage-
positioning op amp (Figure 2). Connect a resistor between FB and OAIN- (Figure 1) to set the voltage-
positioning gain (see the Setting Voltage Positioning section).OAIN-Dual-Mode Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for
additional voltage-positioning gain (Figure 1), connect to the negative terminal of current-sense resistor
through a 1kΩ ±1% resistor as described in the Setting Voltage Positioning section. Connect OAIN- to VCC
to disable op amp. The logic threshold to disable the op amp is approximately VCC - 1V.OAIN+ Op Am p N oni nver ti ng Inp ut. When usi ng the i nter nal op am p for ad d i ti onal vol tag e- p osi ti oni ng g ai n ( Fi g ur e 1) ,
connect to the p osi ti ve ter m i nal of cur r ent- sense r esi stor thr oug h a r esi stor as d escr i b ed i n the S etti ng V ol tag eosi ti oni ng secti on.CSP Positive Current-Limit Input. Connect to the positive terminal of the current-sense resistor.
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Pin Description(continued)
PINNAMEFUNCTIONCSN Negative Current-Limit Input. Connect to the negative terminal of the current-sense resistor.DPSLPDeep-Sleep Control Input. When DPSLP is low the system enters the deep-sleep state and the regulator
applies the appropriate deep-sleep offset. The MAX1907A/MAX1981A adds the offset measured at the POS
and NEG pins to the output. 32 clock cycles after the deep-sleep transition is completed, DDO goes low
(see the Driver Disable and Low-Power Pulse Skipping section). Another 32 clock cycles later, the
MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.
21–26D5–D0Low-Voltage VID DAC Code Inputs. D0 is the LSB, and D5 is the MSB of the internal 6-bit VID DAC (Table
4). The D0–D5 inputs do not have internal pullups. These 1V logic inputs are designed to interface directly
with the CPU. In all normal active modes (modes other than suspend and boot), the output voltage is set by
the VID code indicated by the D0–D5 logic-level voltages on D0–D5. In suspend mode (SUS = high), the
decoded state of the four-level S0–S2 inputs sets the output voltage. In boot mode (see the Power-Up
Sequence section), the decoded state of the four-level B0–B2 inputs set the output voltage.DDODriver-Disable Output. This TTL-logic output can be used to disable the driver outputs on slave-switching
regulator controllers. This forces a high-impedance condition and makes it possible for the
MAX1907A/MAX1981A master controller to operate in low current SKIP mode. DDO goes low 32 RTIME
clock cycles after the MAX1907A/MAX1981A completes a transition to the suspend mode or deep-sleep
voltage (see the Driver Disable and Low-Power Pulse Skipping section). Another 30 clock cycles later, the
MAX1907A/MAX1981A enters automatic pulse-skipping operation.PGND Power Ground. Ground connection for the DL gate driver.DL Low-Side Gate Driver Output. DL swings from PGND to VDD. DL is forced high after the
MAX1907A/MAX1981A powers down (SHDN = GND) or when the controller detects a fault. The MAX1981A
does not include overvoltage protection.VDD Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (4.5V to 5.5V). Bypass to
PGND with a 1µF or greater ceramic capacitor, as close to the IC as possible.BST Boost Flying Capacitor Connection. An optional resistor in series with BST allows the DH pullup current to
be adjusted.LX Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It connects to the
skip-mode zero-crossing comparator.DH High-Side Gate Driver. Output swings LX to BST.V+ Battery Voltage Sense Connection. Used only for PWM one-shot timing. DH on-time is inversely proportional
to input voltage over a range of 2V to 28V.SUSSuspend-Mode Control Input. When SUS is high the regulator slews to the suspend voltage level. This level
is set with four-level logic signals at the S0–S2 inputs. 32 clock cycles after the transition to the suspend-
mode voltage is completed, DDO goes low (see the Driver Disable and Low-Power Pulse Skipping section).
Another 32 clock cycles later, the MAX1907A/MAX1981A is allowed to enter pulse-skipping operation.SYSPOKSystem Power-Good Input. Primarily, SYSPOK serves as the wired NOR junction of the open-drain power-
good signals for the VCCP and VCCMCH supplies. A falling edge on SYSPOK shuts down the
MAX1907A/MAX1981A and sets the fault latch. Toggle SHDN or cycle VCC power below 1V to restart the
controller.
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Table 1. Component Selection for Standard Multiphase Applications (Figure 1)
DESIGNATIONCOMPONENTInput Voltage Range*8V to 24V
VID Output Voltage (D5–D0)1.308V (D5–D0 = 011001)
Boot Voltage (B0–B2)
1.004V
(B2 = OPEN, B1 = VCC,
B0 = GND)
Suspend Voltage (S0–S2)
0.748V
(S2 = OPEN, S1 = VCC,
S0 = GND)
Deep-Sleep Offset Voltage
(POS, NEG)-50mV
Maximum Load Current40A
Inductor (per phase)
0.6µH
Sumida CDEP134H-0R6,
Panasonic ETQP6F0R6BFA, or
BI Technologies HM73-30R60
Switching Frequency300kHz (TON = float)
High-Side MOSFET
(NH, per phase)
International Rectifier
(2) IRF7811W or
Siliconix (2) Si4892DY
*Input voltages less than 8V requires additional input capacitance.
DESIGNATIONCOMPONENTLow-Side MOSFET
(NL, per phase)
International Rectifier
(2) IRF7822,
Fairchild (3) FDS7764A, or
Siliconix (2) Si4860DY
Input Capacitor (CIN)
(6) 10µF 25V
Taiyo Yuden
TMK432BJ106KM or
TDK C4532X5R1E106M
Output Capacitor (COUT)(5) 330µF 2.5V Panasonic
EEFUE0E331XR
Current-Sense Resistor
(RSENSE, per phase)
1.5mΩ
Panasonic ERJM1WTJ1M5U
Schottky Diodes
(D1, D2, D3)
Central Semiconductor
CMPSH-3
Pin Description(continued)
PINNAMEFUNCTIONIMVPOKOpen-Drain Power Good Output. After output voltage transitions, except during power-up and power-down,
if OUT is in regulation then IMVPOK is high impedance. IMVPOK is pulled high whenever the slew-rate
control is active (output voltage transitions). IMVPOK is forced low in shutdown. A pullup resistor on
IMVPOK will cause additional finite shutdown current. IMVPOK also reflects the state of SYSPOK and
includes a 3ms (min) delay for power-up. IMVPOK is forced high during VID transitions.CLKEN Clock Enable Logic Output. This inverted logic output indicates when SYSPOK is high and the output
voltage sensed at FB is in regulation. CLKEN is forced low during VID transitions.TIME Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 235kΩ
to 23.5kΩ resistor sets the clock from 64kHz to 640kHz, fSLEW = 320kHz ✕ 47kΩ/RTIME.TON On-Time Selection Control Input. This four-level input sets the K-factor value (Table 3) used to determine
the DH on-time (see the On-Time One-Shot section). GND = 1000kHz, REF = 550kHz, OPEN = 300kHz,
VCC = 200kHz.
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)OFF
BST
VDDVCC
DAC INPUTS
(1V LOGIC)
REF
CREF
0.22μF
CCC
270pF
PGND
TIME
RTIME
28kΩ
NEGSUSPEND INPUTS
(4-LEVEL LOGIC)
POS
ILIM
SUSMODE
CONTROL
1.5kΩ
100pF
301kΩ
R10
200kΩ
POWER GROUND
ANALOG GROUND
(MASTER)
ANALOG GROUND
(SLAVE)
GNDBOOT INPUTS
(4-LEVEL LOGIC)
OAIN-
OAIN+
CSN
CSP
IMVPOK
SYSPOK
R13
100kΩ
R14
100kΩ
R12
100kΩ
1μF
TONFLOAT
(300kHz)
TRIG
CM+
CM-
CS+CS-
CONNECT TO SLAVE
CONTROLLER FOR
MULTIPHASE OPERATION
(SEE FIGURE 1A)
CONNECT TO SLAVE
CONTROLLER FOR
MULTIPHASE OPERATION
(SEE FIGURE 1A)
ILIM
(MAX1980)
LIMIT
POWER-GOODLOGIC SIGNALS
100kΩ
2.74kΩ
750Ω
750Ω
1.0kΩ
1.0kΩ
49.9kΩ
470pF
100pF
C11
1000pF
* LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE
INPUT*
8V TO 24V
OUTPUTLM
NH(M)
NL(M)
RCM
COUT
CBST(M)
0.1μF
CIN
(3) 10μF 25V CERAMIC
R11
10Ω
5V BIAS
SUPPLY
1μF
(MAX1980)
DDO
SHDN
DPSLP
CLKEN
MAX1907A
MAX1981A
R23200Ω
R22
200Ω
Figure 1. Standard Multiphase Application Circuit
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)INPUT*
8V TO 24V
BST
PGND
OUTPUT
GND
CS+
CS-
POL
LIMIT
CM+
CM-
TON
ILIM
FLOAT
(300kHz)
MAX1980
REF
(MASTER)
COMPOUTPUTLS
NH(S)
NL(S)
RCS
CBST(S)
0.1μF
CIN
(3) 10μF 25V CERAMIC
0.22μF
R15
10Ω
RCOMP
20kΩ
CCOMP
270pF
R17
49.9kΩ
R16
200kΩ
100pFR18
200Ω
R19
200Ω
R20
200Ω
R21
200Ω
4700pF
C10
4700pF
TRIG
5V BIAS
SUPPLY
VDDVCC
1μF
CS+
CS-
(MASTER)
CONNECT TO
MAX1907A/MAX1981A
(SEE FIGURE 1)
ILIM
(MASTER)
DDO
(MASTER)
CM+
CM-
CONNECT TO
MAX1907A/MAX1981A
(SEE FIGURE 1)
POWER GROUND
ANALOG GROUND
(MASTER)
ANALOG GROUND
(SLAVE)
* LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE
Figure 1A. Standard Multiphase Application Circuit (continued)
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)
Detailed Description
5V Bias Supply (VCCand VDD)The MAX1907A/MAX1981A require an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95% efficient 5V system
supply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V supply can be
generated with an external linear regulator.
The 5V bias supply must provide VCC(PWM controller)
and VDD(gate-drive power), so the maximum current
drawn is:
IBIAS= ICC+ fSW(QG(LOW)+ QG(HIGH))
= 10mA to 60mA (typ)
where ICCis 1.3mA (typ), fSWis the switching frequen-
cy, and QG(LOW)and QG(HIGH)are the MOSFET data
sheet’s total, gate-charge specification limits at VGS=
5V.
V+ and VDDcan be tied together if the input power
source is a fixed 4.5V to 5.5V supply. If the 5V bias
supply is powered up prior to the battery supply, the
enable signal (SHDNgoing from low to high) must be
delayed until the battery voltage is present to ensure
startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed-ForwardThe Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
with voltage feed-forward (Figure 2). This architecture
relies on the output filter capacitor’s ESR to act as the
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined
solely by a one-shot whose period is inversely propor-
tional to input voltage and directly proportional to out-
put voltage. Another one-shot sets a minimum off-time
(400ns, typ). The on-time one-shot is triggered if the
error comparator is low, the low-side switch current is
below the current-limit threshold, and the minimum off-
time one-shot has timed out.
On-Time One-Shot (TON)The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V+ input, and proportional
to the output voltage:
tON= K(VFB+ 0.075V) / VIN
where K is set by the TON pin-strap connection (Table
3) and 0.075V is an approximation to accommodate the
SUPPLIERPHONEWEBSITEBI Technologies714-447-2345 (USA)www.bitechnologies.com
Central Semiconductor631-435-1110 (USA)www.centralsemi.com
Coilcraft800-322-2645 (USA)www.coilcraft.com
Coiltronics561-752-5000 (USA)www.coiltronics.com
Fairchild Semiconductor888-522-5372 (USA)www.fairchildsemi.com
International Rectifier310-322-3331 (USA)www.irf.com
Kemet408-986-0424 (USA)www.kemet.com
Panasonic847-468-5624 (USA)www.panasonic.com
Sanyo408-749-9714 (USA) 65-281-3226 (Singapore)www.secc.co.jp
Siliconix (Vishay)203-268-6261 (USA)www.vishay.com
Sumida408-982-9660 (USA)www.sumida.com
Taiyo Yuden408-573-4150 (USA) 03-3667-3408 (Japan)www.t-yuden.com
TDK847-803-6100 (USA) 81-3-5201-7241 (Japan)www.component.tdk.com
Toko858-675-8013 (USA)www.tokoam.com
Table 2. Component Suppliers
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)VDD
ON-TIME
COMPUTEMAX1907A
MAX1981A
TRIGQ
ONE-SHOT
INTERNAL MULTIPLEXERS
AND SLEW-RATE CONTROL
TIME
D0–D5
S0–S2B0–B2
PGND
BST
TON
TRIGQ
ONE-SHOTCSP
CSN
ILIM
ON-TIMEMINIMUM
OFF-TIME
REF
OAIN-
OAIN+
NEG
POS
VCC
REF
GND
SYSPOK
IMVPOK
DDO
SUS
SKIP-MODE
LOGIC
POWER-GOOD
LOGIC
0.9 x REF
1.1 x REF
FAULT
PROTECTION
REF
(2V)
SHDN
DPSLP
CLKEN
R-2R
DIVIDER
Figure 2. MAX1907A/MAX1981A Functional Diagram
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)expected drop across the low-side MOSFET switch.
This algorithm results in a nearly constant switching fre-
quency despite the lack of a fixed-frequency clock gen-
erator. The benefits of a constant switching frequency
are twofold: 1) the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band; 2)
the inductor ripple-current operating point remains rela-
tively constant, resulting in easy design methodology
and predictable output voltage ripple.
The on-time one-shot has good accuracy at the operat-
ing points specified in the Electrical Characteristics
(±10% at 200kHz and 300kHz, ±12% at 550kHz and
1000kHz). On-times at operating points far removed
from the conditions specified in the Electrical
Characteristicscan vary over a wider range. For exam-
ple, the 1000kHz setting will typically run about 10%
slower with inputs much greater than 5V due to the very
short on-times required.
On-times translate only roughly to switching frequen-
cies. The on-times guaranteed in the Electrical
Characteristicsare influenced by switching delays in
the external high-side MOSFET. Resistive losses,
including the inductor, both MOSFETs, output capacitor
ESR, and PC board copper losses in the output and
ground tend to raise the switching frequency at higher
output currents. Also, the dead-time effect increases
the effective on-time, reducing the switching frequency.
It occurs only in PWM mode (SUS = low, DPSLP= low)
and during dynamic output voltage transitions when the
inductor current reverses at light or negative load cur-
rents. With reversed inductor current, the inductor’s
EMF causes LX to go high earlier than normal, extend-
ing the on-time by a period equal to the DH-rising dead
time.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency is:
where VDROP1is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and tONis the on-time calculat-
ed by the MAX1907A/MAX1981A.
Integrator Amplifiers/
Output Voltage OffsetsTwo transconductance amplifiers provide a fine adjust-
ment to the output regulation point (Figure 2). One
amplifier forces the DC average of the feedback volt-
age to equal the VID DAC setting. The second amplifier
is used to create small positive or negative offsets to
the feedback voltage, using the POS and NEG pins.
The feedback amplifier integrates the feedback volt-
age, allowing accurate DC output voltage regulation
regardless of the output ripple voltage. The feedback
amplifier has the ability to shift the output voltage by
±8%. The differential input voltage range is at least
±80mV total, including DC offset and AC ripple. The
integration time constant can be set easily with one
capacitor at the CC pin. Use a capacitor value of 47pF
to 1000pF (270pF, typ).
The POS/NEG amplifier is used to add small offsets to
the VID DAC setting in deep-sleep mode (DPSLP=
low). The offset amplifier is summed directly with the
feedback voltage, making the offset gain independent
of the DAC code. This amplifier has the ability to offset
the output by ±200mV. To create an output offset, bias
POS and NEG to a voltage (typically VOUTor REF) with-
in their 0 to 2V common-mode range, and offset them
from one another with a resistive divider (Figure 1). If
VPOSis higher than VNEG, then the output is shifted in
the positive direction. If VNEGis higher than VPOS, then
the output is shifted in the negative direction. The output
offset equals the voltage difference from POS to NEG.
Forced-PWM Operation (Normal Mode)During normal mode, when the CPU is actively running
(SUS = low and DPSLP= high), the MAX1907A/
MAX1981A operates with the low-noise, forced-PWM
control scheme. Forced-PWM operation disables the
zero-crossing comparator, forcing the low-side gate-
drive waveform to constantly be the complement of the
high-side gate-drive waveform. The benefit of forced-
PWM mode is to keep the switching frequency fairly
constant.SW
OUTDROPINDROPDROPVV()−()
TON
CONNECTION
FREQUENCY
SETTING
(kHz)
K-FACTOR
(µs)
MAX
K-FACTOR
ERROR (%)VCC2005±10
Float3003.3±10
REF5501.8±12.5
GND10001.0±12.5
Table 3. Approximate K-Factor Errors
MAX1907A/MAX1981A
Quick-PWM Master Controllers for Voltage-
Positioned CPU Core Power Supplies (IMVP-IV)Forced-PWM operation comes at a cost: the no-load 5V
bias supply current remains between 10mA to 40mA,
depending on the external MOSFETs and switching fre-
quency. To maintain high efficiency under light load
conditions, the MAX1907A/MAX1981A automatically
switches to the low-power pulse skipping control
scheme after entering suspend or deep-sleep mode.
During all output voltage and mode transitions, the
MAX1907A/MAX1981A uses forced-PWM operation in
order to ensure fast, accurate transitions. Since forced-
PWM operation disables the zero-crossing comparator,
the inductor current reverses under light loads, quickly
discharging the output capacitors. The controller main-
tains forced-PWM operation for 30 clock cycles (set by
RTIME) after the controller sets the last DAC code value
to guarantee the output voltage settles properly before
entering pulse-skipping operation.
Low-Power Pulse SkippingDuring deep-sleep mode (DPSLP= low) or low-power
suspend (SUS = high), the MAX1907A/MAX1981A uses
an automatic pulse-skipping control scheme.
For deep-sleep mode, when the CPU pulls DPSLPlow,
the MAX1907A/MAX1981A shifts the output voltage to
incorporate the offset voltage set by the POS and NEG
inputs. The controller pulls the driver-disable output
(DDO) low 32 RTIMEclock cycles after DPSLPgoes low.
Another 30 RTIMEclock cycles later, the MAX1907A/
MAX1981A enters low-power operation, allowing auto-
matic pulse skipping under light loads. When the CPU
drives DPSLPhigh, the MAX1907A/MAX1981A immedi-
ately enters forced-PWM operation, forces DDOhigh,
and eliminates the output offset, slewing the output to
the operating voltage set by the D0–D5 inputs. When
either DPSLPtransition occurs, the MAX1907A/
MAX1981A forces IMVPOK high and CLKENlow for 32
RTIMEclock cycles.
When entering suspend mode (SUS driven high), the
MAX1907A/MAX1981A slews the output down to the
suspend output voltage set by SO–S2 inputs. 32 RTIME
clock cycles after the slew-rate controller reaches the
last DAC code (see the Output Voltage Transition
Timingsection), the driver-disable output (DDO) is
asserted low. After another 30 RTIMEclock cycles, the
MAX1907A/MAX1981A enters low-power operation,
allowing pulse skipping under light loads. When the
CPU pulls SUS low, the MAX1907A/MAX1981A immedi-
ately enters forced-PWM operation, forces DDOhigh,
and slews the output up to the operating voltage set by
the D0–D5 inputs. When either SUS transition occurs,
the MAX1907A/MAX1981A blanks IMVPOK and CLKEN,
preventing IMVPOK from going low and CLKENfrom
going high. The blanking remains until the slew-rate
controller has reached the last DAC code and 32
RTIME clock pulses have passed.
In multiphase applications, the driver-disable signal is
used to force one or more slave regulators into a high-
impedance state. When the master’s DDOoutput is dri-
ven low, the slave controller with driver disable
(MAX1980) forces its DL (SLAVE) and DH (SLAVE) gate
drivers low, effectively disabling the slave controller.
Disabling the slave controller for single-phase opera-
tion allows the MAX1907A/MAX1981A to enter low-
power pulse-skipping operation under low-power
conditions, improving light-load efficiency. When DDO
is driven high, the slave controller (MAX1980) enables
the drivers, allowing normal forced-PWM operation.
Automatic Pulse-Skipping SwitchoverIn skip mode (SUS = high, or DPSLP= low), an inherent
automatic switchover to PFM takes place at light loads
(Figure 3). This switchover is effected by a comparator
that truncates the low-side switch on-time at the induc-
tor current’s zero crossing. The zero-crossing compara-
tor senses the inductor current across the low-side
MOSFET. Once VLX- VPGNDdrops below 4mV (typ),
the comparator forces DL low (Figure 2). This mecha-
nism causes the threshold between pulse-skipping
PFM and non-skipping PWM operation to coincide with
the boundary between continuous and discontinuous
inductor-current operation. The load-current level at
which PFM/PWM crossover occurs, ILOAD(SKIP), is
equal to 1/2 the peak-to-peak ripple current, which is a
function of the inductor value (Figure 4). For a battery
range of 8V to 24V, this threshold is relatively constant,
with only a minor dependence on battery voltage:
where K is the on-time scale factor (Table 3). For exam-
ple, in the standard application circuit this becomes:
The crossover point occurs at a lower value if a swing-
ing (soft-saturation) inductor is used. The switching
waveforms may appear noisy and asynchronous when
light loading causes pulse-skipping operation, but this
is a normal operating condition that results in high light-
load efficiency. Trade-offs in PFM noise vs. light-load
efficiency are made by varying the inductor value.
Generally, low inductor values produce a broader effi-3368013028...VsA×⎜⎟⎛⎜⎞⎟=μVKLOADSKIPOUTBATTOUT
BATT()=⎛⎜⎞⎟−⎛⎜⎟2
