MAX186DEWP ,Low-Power, 8-Channel, Serial 12-Bit ADCsElectrical Characteristics). When ordering, please specify grade.Contact factory for availability o ..
MAX187 ,+5V, Low-Power, 12-Bit Serial ADCsApplicationsMAX187BC/D 0°C to +70°C Dice* ±1Portable Data LoggingOrdering Information continued on ..
MAX1870AETJ+ ,Step-Up/Step-Down Li+ Battery ChargerElectrical Characteristics(Circuit of Figure 2, V = V = V = V = V = 18V, V = V = V = V = 12V, V = 3 ..
MAX1870AETJ+ ,Step-Up/Step-Down Li+ Battery ChargerFeaturesThe MAX1870A step-up/step-down multichemistry• Highly Flexible Input Voltage Range Works wi ..
MAX1873REEE ,Simple Current-Limited Switch-Mode Li Charger ControllerELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V = V = V = 18V, V = V , V = V /2. MAX1873R: V = V ..
MAX1873REEE+ ,Simple Current-Limited Switch-Mode Li+ Charger ControllerFeaturesThe low-cost MAX1873R/S/T provides all functions♦ Low-Cost and Simple Circuitneeded to simp ..
MAX480EPA ,High-Precision, Low-Voltage, Micropower Op Ampapplications. The MAX480 operates' 140µV Max Input Offset Voltagewith either a single supply rangin ..
MAX480ESA ,High-precision, low-voltage, micropower op amp.ELECTRICAL CHARACTERISTICS(V = ±1.5V to ±15V, T = +25°C, unless otherwise noted.)ASPARAMETER SYMBOL ..
MAX480ESA ,High-precision, low-voltage, micropower op amp.Applications MAX480CPA 0°C to +70°C 8 Plastic DIPMAX480CSA 0°C to +70°C 8 SOPrecision Micropower Am ..
MAX480ESA+ ,High Precision, Low-Voltage, Micropower Op AmpApplications MAX480CPA 0°C to +70°C 8 Plastic DIPMAX480CSA 0°C to +70°C 8 SOPrecision Micropower Am ..
MAX4810CTN+ ,Dual, Unipolar/Bipolar, High-Voltage Digital PulsersApplications GC2C 47 24 INP2DC2Ultrasound Medical Flaw DetectionV 23 EN248EE2ImagingPiezoelectric D ..
MAX481CPA ,Low-Power, Slew-Rate-Limited RS-485/RS-422 TransceiversApplicationsIndustrial-Control Local Area Networks Ordering Information appears at end of data shee ..
MAX186ACAP-MAX186ACPP-MAX186ACWP-MAX186AEAP-MAX186AEPP-MAX186AEWP-MAX186AMJP-MAX186BCAP-MAX186BCPP-MAX186BCWP-MAX186BEAP-MAX186BEWP-MAX186CCAP-MAX186CCPP-MAX186CCWP-MAX186CEAP-MAX186CEPP-MAX186CEWP-MAX186DCAP-MAX186DCPP-MAX186DEAP-MAX186DEPP-MAX186DEWP
Low-Power, 8-Channel, Serial 12-Bit ADCs
_______________General DescriptionThe MAX186/MAX188 are 12-bit data-acquisition sys-
tems that combine an 8-channel multiplexer, high-band-
width track/hold, and serial interface together with high
conversion speed and ultra-low power consumption.
The devices operate with a single +5V supply or dual
±5V supplies. The analog inputs are software config-
urable for unipolar/bipolar and single-ended/differential
operation.
The 4-wire serial interface directly connects to SPI™,
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320
family digital signal processors. The MAX186/MAX188
use either the internal clock or an external serial-interface
clock to perform successive-approximation A/D conver-
sions. The serial interface can operate beyond 4MHz
when the internal clock is used.
The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts
have a reference-buffer amplifier that simplifies gain
trim .
The MAX186/MAX188 provide a hard-wired SHDNpin
and two software-selectable power-down modes.
Accessing the serial interface automatically powers up
the devices, and the quick turn-on time allows the
MAX186/MAX188 to be shut down between every
conversion. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
The MAX186/MAX188 are available in 20-pin DIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin DIP.
For applications that call for a parallel interface, see the
MAX180/MAX181 data sheet. For anti-aliasing filters,
consult the MAX274/MAX275 data sheet.
________________________ApplicationsPortable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments
____________________________Features8-Channel Single-Ended or 4-Channel
Differential InputsSingle +5V or ±5V OperationLow Power:1.5mA (operating mode)
2µA (power-down mode)Internal Track/Hold, 133kHz Sampling RateInternal 4.096V Reference (MAX186)SPI-, QSPI-, Microwire-, TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP, SO, SSOP PackagesEvaluation Kit Available
______________Ordering Information
Ordering Information continued on last page.† NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
* Dice are specified at +25°C, DCparameters only.
* * Contact factory for availability and processing to MIL-STD-883.
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
____________________Pin ConfigurationSPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.
19-0123; Rev. 4; 8/96
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND............................................................-0.3V to +6V
VSSto AGND............................................................+0.3V to -6V
VDDto VSS..............................................................-0.3V to +12V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND, DGND.............(VSS- 0.3V) to (VDD+ 0.3V)
CH0–CH7 Total Input Current ..........................................±20mA
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C)...........889mW
SO (derate 10.00mW/°C above +70°C)........................800mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
CERDIP (derate 11.11mW/°C above +70°C)................889mW
Operating Temperature Ranges:
MAX186_C/MAX188_C........................................0°C to +70°C
MAX186_E/MAX188_E......................................-40°C to +85°C
MAX186_M/MAX188_M..................................-55°C to +125°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
Note 1:Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4:Ground on-channel; sine wave applied to all off channels.
Note 5:Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:Measured at VSUPPLY+5% and VSUPPLY-5% only.
Note 9:The common-mode range for the analog inputs is from VSSto VDD.
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
TIMING CHARACTERISTICS(VDD= 5V ±5%; VSS =0V or -5V, TA= TMINto TMAX, unless otherwise noted.)
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
__________________________________________Typical Operating CharacteristicsPOWER-SUPPLY REJECTION
vs. TEMPERATURE
TEMPERATURE (°C)
PSR (LSBs)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
VREFADJ (V)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET MATCHING (LSBs)100
_____________________________________________________________Pin Description
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCsFigure 1.Load Circuits for Enable Time
Figure 2.Load Circuits for Disabled Time
Figure 3.Block Diagram
________________________________________________Pin Description (continued)
MAX186/MAX188
_______________Detailed DescriptionThe MAX186/MAX188 use a successive-approximation
conversion technique and input track/hold (T/H) circuit-
ry to convert an analog signal to a 12-bit digital output.
A flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX186/MAX188.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0-CH7 and IN-is switched to AGND. In
differential mode, IN+ and IN-are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7.
Configure the channels with Table 3 and Table 4.
In differential mode, IN-and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN-(the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply AGND. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) -(VIN-)] from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for
single-ended inputs, IN-is connected to AGND, and
the converter samples the “+” input. If the converter is
set up for differential inputs, IN-connects to the “-”
input, and the difference of |IN+ -IN-|is sampled. At
the end of the conversion, the positive input connects
back to IN+, and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by:
tAZ= 9 x (RS+ RIN) x 16pF,
where RIN= 5kΩ, RS= the source impedance of the
input signal, and tAZis never less than 1.5µs. Note that
source impedances below 5kWdo not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Analog Input Range and Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand VSS, allow the channel input pins to
swing from VSS-0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV, or be
lower than VSSby 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on-channel.The full-scale input voltage depends on the voltage at
VREF. See Tables 1a and 1b.
Quick LookTo evaluate the analog performance of the
MAX186/MAX188 quickly, use the circuit of Figure 5.
The MAX186/MAX188 require a control byte to be writ-
ten to DIN before each conversion. Tying DIN to +5V
feeds in control bytes of $FF (HEX), which trigger
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs* A = 1.678 for the MAX186, 1.638 for the MAX188
Table 1b.Bipolar Full Scale, Zero Scale, and
Negative Full Scale
Table 1a.Unipolar Full Scale and Zero Scale* A = 1.678 for the MAX186, 1.638 for the MAX188
MAX186/MAX188single-ended unipolar conversions on CH7 in external
clock mode without powering down between conver-
sions. In external clock mode, the SSTRB output pulses
high for one clock period before the most significant bit
of the 12-bit conversion result comes out of DOUT.
Varying the analog input to CH7 should alter the
sequence of bits from DOUT. A total of 15 clock cycles
is required per conversion. All transitions of the SSTRB
and DOUT outputs occur on the falling edge of SCLK.
How to Start a ConversionA conversion is started on the MAX186/MAX188 by
clocking a control byte into DIN. Each rising edge on
SCLK, with CSlow, clocks a bit from DIN into the
MAX186/MAX188’s internal shift register. After CSfalls,
the first arriving logic “1” bit defines the MSB of the
control byte. Until this first “start” bit arrives, any num-
ber of logic “0” bits can be clocked into DIN with no
effect. Table 2 shows the control-byte format.
The MAX186/MAX188 are fully compatible with
Microwire and SPI devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. Microwire and SPI
both transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit, the simplest
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Example: Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode, call
it TB1. TB1 should be of the format: 1XXXXX11
Binary, where the Xs denote the particular channel
and conversion-mode selected.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Table 2.Control-Byte Format
Use a general-purpose I/O line on the CPU to pullon the MAX186/MAX188 low.Transmit TB1 and simultaneously receive a byteand call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB2.Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB3.Pull CSon the MAX186/MAX188 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital OutputIn unipolar input mode, the output is straight binary
(see Figure 15). For bipolar inputs, the output is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
Table 3.Channel Selection in Single-Ended Mode (SGL/DIFF= 1)
Table 4.Channel Selection in Differential Mode (SGL/DIFF= 0)
MAX186/MAX188
Internal and External Clock ModesThe MAX186/MAX188 may use either an external serial
clock or the internal clock to perform the
successive-approximation conversion. In both clock
modes, the external clock shifts data in and out of the
MAX186/MAX188. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7 through 10 show the timing
characteristics common to both modes.
External ClockIn external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (see Figure 6).
SSTRB and DOUT go into a high-impedance state whengoes high; after the next CSfalling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
Low-Power, 8-Channel,
Serial 12-Bit ADCsFigure 6.24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7.Detailed Serial-Interface Timing
