MAX186BEWP+ ,Low-Power, 8-Channel, Serial 12-Bit ADCsapplications that call for a parallel interface, Pin Configurationsee the MAX180/MAX181 data sheet. ..
MAX186BEWP+T ,Low-Power, 8-Channel, Serial 12-Bit ADCsFeatures♦ 8-Channel Single-Ended or 4-Channel The MAX186/MAX188 are 12-bit data-acquisition sys-Dif ..
MAX186CCAP ,Low-Power, 8-Channel, Serial 12-Bit ADCsMAX186/MAX18819-0123; Rev. 4; 8/96Low-Power, 8-Channel,Serial 12-Bit ADCs _______________
MAX186CCAP+ ,Low-Power, 8-Channel, Serial 12-Bit ADCsELECTRICAL CHARACTERISTICS(V = 5V ±5%; V = 0V or -5V; f = 2.0MHz, external clock (50% duty cycle); ..
MAX186CCPP ,Low-Power, 8-Channel, Serial 12-Bit ADCsGeneral Description ________
MAX186CCPP+ ,Low-Power, 8-Channel, Serial 12-Bit ADCsElectrical Characteristics). When ordering, please specify grade.under 10µA at reduced sampling rat ..
MAX4794EUS+T ,200mA/250mA/300mA Current-Limit SwitchesMAX4789–MAX479419-2663; Rev 3; 10/08200mA/250mA/300mA Current-Limit Switches
MAX4798EUK ,450mA/500mA Current-Limit SwitchesApplicationsMAX4796EUK-T -40°C to +85°C 5 SOT23-5 AEDJSDIOMAX4796ETT* -40°C to +85°C 6 TDFN-EP** —P ..
MAX4798EUK+T ,450mA/500mA Current-Limit Switchesapplications.♦ Autoretry (MAX4796/MAX4798)When the switch is on and a load is connected to the♦ 80µ ..
MAX4798EUK+T ,450mA/500mA Current-Limit SwitchesFeaturesThe MAX4795–MAX4798 family of switches feature inter- ♦ Guaranteed Current Limit: 450mA and ..
MAX479CPD ,17レA Max, Dual/Quad, Single-Supply, Precision Op AmpsELECTRICAL CHARACTERISTICS: 5V(V = 5V, 0V, V = 0.1V, V = 1.4V, T = +25°C, unless otherwise noted.) ..
MAX479CSD ,17レA Max, Dual/Quad, Single-Supply, Precision Op AmpsGeneral Description _______
MAX186ACAP+-MAX186ACPP+-MAX186ACWP+-MAX186AEAP+-MAX186AEPP+-MAX186BCAP+-MAX186BCPP+-MAX186BCWP+-MAX186BEAP+-MAX186BEPP+-MAX186BEWP+-MAX186BEWP+T-MAX186CCAP+-MAX186CCPP+-MAX186CCWP+-MAX186CCWP+T-MAX186CEAP+-MAX186CEPP+-MAX186CEWP+-MAX186DCAP+T-MAX186DEAP+-MAX
Low-Power, 8-Channel, Serial 12-Bit ADCs
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs EVALUATION KIT AVAILABLE
General DescriptionThe MAX186/MAX188 are 12-bit data-acquisition sys-
tems that combine an 8-channel multiplexer, high-
bandwidth track/hold, and serial interface together with
high conversion speed and ultra-low power consump-
tion. The devices operate with a single +5V supply or
dual ±5V supplies. The analog inputs are software con-
figurable for unipolar/bipolar and single-ended/differen-
tial operation.
The 4-wire serial interface directly connects to SPI,
QSPI™ and MICROWIRE®devices without external
logic. A serial strobe output allows direct connection to
TMS320 family digital signal processors. The
MAX186/MAX188 use either the internal clock or an
external serial-interface clock to perform successive-
approximation A/D conversions. The serial interface can
operate beyond 4MHz when the internal clock is used.
The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts have
a reference-buffer amplifier that simplifies gain trim .
The MAX186/MAX188 provide a hard-wired SHDNpin
and two software-selectable power-down modes.
Accessing the serial interface automatically powers up
the devices, and the quick turn-on time allows the
MAX186/MAX188 to be shut down between every con-
version. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.
The MAX186/MAX188 are available in 20-pin PDIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin
PDIP. For applications that call for a parallel interface,
see the MAX180/MAX181 data sheet. For anti-aliasing
filters, consult the MAX274/MAX275 data sheet.
________________________ApplicationsPortable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments
____________________________Features8-Channel Single-Ended or 4-Channel
Differential InputsSingle +5V or ±5V OperationLow Power:1.5mA (Operating Mode)
2µA (Power-Down Mode)Internal Track/Hold, 133kHz Sampling RateInternal 4.096V Reference (MAX186)SPI-/QSPI-/MICROWIRE-/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin PDIP, SO, SSOP PackagesEvaluation Kit Available
Ordering InformationTOP VIEW
PDIP/SO/SSOPVDD
SCLK
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VREFSHDN
VSS
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX186
MAX188
____________________Pin ConfigurationQSPI is a trademark of Motorola.
MICROWIRE is a registered trademark of National
Ordering Information continued on last page.†Parts are offered in grades A, B, C and D (grades defined in
Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
*Dice are specified at +25°C, DC parameters only.
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART† TEMP RANGE PIN-PACKAGE
MAX186_CPP+ 0°C to +70°C 20 PDIP
MAX186_CWP+ 0°C to +70°C 20 SO
MAX186_CAP+ 0°C to +70°C 20 SSOP
MAX186DC/D 0°C to +70°C Dice*
MAX186_EPP+ -40°C to +85°C 20 PDIP
MAX186_EWP+ -40°C to +85°C 20 SO
MAX186_EAP+ -40°C to +85°C 20 SSOP
Relative Accuracy (Note 2)
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETERSYMBOLMINTYPMAXUNITS±1.0
LSB
±0.75
±1.0
±0.5
Differential NonlinearityDNL±1LSB
±2.0
±3.0
±3.0
Resolution12Bits
±0.5
Offset Error
±3.0
LSB
±3.0
±1.5
±2.0
±2.0
Gain Error (Note 3)
±3.0
LSB
Gain Temperature Coefficient±0.8ppm/°C
±0.1LSB
SINAD70dB
THD-80dB
Spurious-Free Dynamic RangeSFDR80dB
Channel-to-Channel Crosstalk-85dB
CONDITIONSMAX186D/MAX188D
MAX186D/MAX188D
MAX186 (all grades)
MAX188C
MAX186C
MAX186B/MAX188B
No missing codes over temperature
MAX186A/MAX188A
MAX186B/MAX188B
MAX186C/MAX188C
External reference
4.096V (MAX188)
External reference, 4.096V
MAX186A/MAX188A
65kHz, VIN= 4.096VP-P(Note 4)
VDDto AGND............................................................-0.3V to +6V
VSSto AGND............................................................+0.3V to -6V
VDDto VSS..............................................................-0.3V to +12V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND, DGND.............(VSS- 0.3V) to (VDD+ 0.3V)
CH0–CH7 Total Input Current...........................................±20mA
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA = +70°C)
PDIP (derate 11.11mW/°C above +70°C).....................889mW
SO (derate 10.00mW/°C above +70°C)........................800mW
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX186_C/MAX188_C........................................0°C to +70°C
MAX186_E/MAX188_E......................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
MAX188A
MAX188B
MAX188C
MAX188D
Channel-to-Channel
Offset Matching
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion
(up to the 5th harmonic)
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(10kHz sine wave input, 4.096VP-P, 133ksps, 2.0MHz external clock, bipolar input mode)
External Clock Frequency Range
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSmall-Signal Bandwidth-3dB rolloff4.5MHz
Full-Power Bandwidth800kHz
Internal clock5.510Conversion Time (Note 5)t CONVExternal clock, 2MHz, 12 clocks/conversion6µs
Track/Hold Acquisition TimetAZ1.5µs
Aperture Delay10ns
Aperture Jitter<50ps
Internal Clock Frequency1.7MHz
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
External compensation, 4.7µF0.12.0
Internal compensation (Note 6)0.10.4
Used for data transfer only10
MHz
Unipolar, VSS= 0VInput Voltage Range,
Single-Ended and Differential
(Note 9)Bipolar, VSS= -5V
Multiplexer Leakage CurrentOn/off leakage current, VIN= ±5V±0.01±1µA
Input Capacitance(Note 6)16pF
VREFOutput VoltageTA= +25°C4.0764.0964.116V
VREFShort-Circuit Current30mA
MAX186A, MAX186B,
MAX186C
±30±50
±30±60VREFTempco
MAX186D±30
Load Regulation (Note 7)0 to 0.5mA output load2.5
Internal compensation0Capacitive Bypass at VREFExternal compensation4.7µF
Internal compensation0.01Capacitive Bypass at REFADJExternal compensation0.01µF
MAX186_C
MAX186_E
REFADJAdjustment Range±1.5%
±VREF/2
0 to
VREF
Input Voltage RangeV
Input Current200350µA
Input Resistance1220kΩ
Shutdown VREFInput Current1.510µA
Buffer Disable Threshold REFADJVDD-
50mVV
VDD+ 2.5050mV
CONVERSION RATE
ANALOG INPUT
INTERNAL REFERENCE(MAX186 only, reference buffer enabled)
EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF= 4.096V)
ppm/°C
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXInternal compensation mode0µFCapacitive Bypass at VREFExternal compensation mode4.7
MAX1861.678V/VMAX1881.638
MAX186±50µAREFADJ Input CurrentMAX188±5
VINH2.4V
VINL0.8V
DIN, SCLK, CSInput HysteresisVHYST0.15V
DIN, SCLK, CSInput LeakageIINVIN= 0V or VDD±1µA
CIN(Note 6)15pF
SHDNInput High VoltageVINHVDD- 0.5V
SHDNInput Low VoltageVINL0.5V
SHDNInput Current, HighIINHVSHDN= VDD4.0µA
SHDNInput Current, LowIINLVSHDN= 0V-4.0µA
SHDNInput Mid VoltageVIMV
SHDNVoltage, OpenVFLTVSHDN= open2.75V
VSHDN= open-100100nA
ISINK= 5mA0.4Output Voltage LowVOLISINK= 16mA0.3V
Output Voltage HighVOHISOURCE= 1mA4V
Three-State Leakage CurrentILVCS= 5V±10µA
Three-State Output CapacitanceCOUTVCS= 5V (Note 6)15pF
Positive Supply VoltageVDD5 ±5%V
DIN, SCLK, CSInput Capacitance
SHDNMax Allowed Leakage,
Mid Input
Negative Supply VoltageVSS0 or
-5 ±5%V
Operating mode1.52.5
Fast power-down3070Positive Supply CurrentIDD
Full power-down210
Operating mode and fast power-down50Negative Supply CurrentISSFull power-down10µA
DIN, SCLK, CSInput Low Voltage
DIN, SCLK, CSInput High Voltage
1.5VDD-1.5
DIGITAL INPUTS (DIN, SCLK, CCSS, SSHHDDNN)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
UNITS
EXTERNAL REFERENCE AT REFADJReference-Buffer Gain
CLOAD= 100pF20150SCLK Fall to Output Data ValidtDOMAX18_ _C/E
Note 1:Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4:Ground on-channel; sine wave applied to all off channels.
Note 5:Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:Guaranteed by design. Not subject to production testing.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:Measured at VSUPPLY+5% and VSUPPLY-5% only.
Note 9:The common-mode range for the analog inputs is from VSSto VDD.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
PARAMETERSYMBOLCONDITIONSUNITSPositive Supply Rejection
(Note 8)PSR±0.06±0.5mV
Negative Supply Rejection
(Note 8)PSRVSS= -5V ±5%; external reference, 4.096V;
full-scale input±0.01±0.5mV
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V ±5%; VSS= 0V or -5V; fCLK= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—
4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; TA= TMINto TMAX, unless otherwise
noted.)
TIMING CHARACTERISTICS(VDD= 5V ±5%; VSS =0V or -5V, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSUNITSSCLK Pulse Width LowtCL200ns
SCLKFall to SSTRBtSSTRBCLOAD= 100pF200ns
tSDVExternal clock mode only, CLOAD= 100pF200ns
tSTRExternal clock mode only, CLOAD= 100pF200ns
tSCKInternal clock mode only0ns
Acquisition TimetAZ1.5µs
DIN to SCLK SetuptDS100ns
DIN to SCLK HoldtDH0nsFall to Output EnabletDVCLOAD= 100pF100nsRise to Output DisabletTRCLOAD= 100pF100nsto SCLKRise SetuptCSS100nsto SCLK Rise HoldtCSH0ns
SCLK Pulse Width HightCH200ns
SSTRB Rise to SCLKRise
(Note 6)Fall to SSTRB Output Enable
(Note 6)
VDD= 5V ±5%; external reference, 4.096V;
full-scale input
MINTYPMAX
MINTYPMAXRise to SSTRB Output Disable
(Note 6)
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
Low-Power, 8-Channel,
Serial 12-Bit ADCs
__________________________________________Typical Operating CharacteristicsPOWER-SUPPLY REJECTION
vs. TEMPERATURE
TEMPERATURE (°C)
PSR (LSBs)
-2004080120DD = +5V ±5%
VSS = 0V or -5V
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
VREFADJ (V)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET MATCHING (LSBs)100
-14066.5kHz
MAX186/MAX188 FFT PLOT – 133kHzft = 10kHz
fs = 133kHz
33.25kHz
AMPLITUDE (dB)
FREQUENCY
ft = 10kHz
fs = 133kHz
TA = +25°C
_____________________________________________________________Pin Description
PIN NAME FUNCTION 1–8 CH0–CH7 Sampling Analog Inputs
9 VSS Negative Supply Voltage. Connect to -5V ±5% or AGND SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10μA (max)
supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the
reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the
reference-buffer amplifier in external compensation mode.
11 VREF
Reference Voltage for analog-to-digital conversion. Also, output of the reference buffer amplifier
(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7μF capacitor to ground when
using external compensation mode. Also functions as an input when used with a precision external
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188+5V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a. High-Z to VOH and VOL to VOHb. High-Z to VOL and VOH to VOL
+5V
3kΩ
CLOAD
DGND
DOUT
CLOAD
DGND
3kΩ
DOUT
a VOH to High-Zb VOL to High-Z
Figure 1.Load Circuits for Enable Time
Figure 2.Load Circuits for Disabled Time
INPUT
SHIFTREGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+2.46V
REFERENCE(MAX186)
T/HANALOG
INPUTMUX
12-BITSAR
ADC
DOUT
SSTRB
VDD
DGND
VSS
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
AGND
REFADJ
VREF
OUT
REF
CLOCK
+4.096V
20kΩ≈ 1.65
MAX186
MAX188
SHDN
Figure 3.Block Diagram
________________________________________________Pin Description (continued)
PIN NAME FUNCTION 12 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
VDD.
13 AGND Analog Ground. Also IN- Input for single-ended conversions.
14 DGND Digital Ground
15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
16 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external mode).
17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
18 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20 VDD Positive Supply Voltage, +5V ±5%
_______________Detailed DescriptionThe MAX186/MAX188 use a successive-approximation
conversion technique and input track/hold (T/H) circuit-
ry to convert an analog signal to a 12-bit digital output.
A flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX186/MAX188.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0-CH7 and IN-is switched to AGND. In
differential mode, IN+ and IN-are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7.
Configure the channels with Table 3 and Table 4.
In differential mode, IN-and IN+ are internally switched
to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN-(the select-
ed analog input, respectively) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply AGND. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) -(VIN-)] from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for
single-ended inputs, IN-is connected to AGND, and
the converter samples the “+” input. If the converter is
set up for differential inputs, IN-connects to the “-”
input, and the difference of |IN+ -IN-|is sampled. At
the end of the conversion, the positive input connects
back to IN+, and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal-
culated by:
tAZ= 9 x (RS+ RIN) x 16pF,
where RIN= 5kΩ, RS= the source impedance of the
input signal, and tAZis never less than 1.5µs. Note that
source impedances below 5kΩdo not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
CSWITCH
TRACK
T/H
SWITCH
10kΩ
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND.
DIFFERENTIAL MODE: IN+ AND IN– SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN– CHANNEL.
INPUT
MUX
Figure 4.Equivalent Input Circuit
Full ScaleVREFADJx A*
Analog Input Range and Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand VSS, allow the channel input pins to
swing from VSS-0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV, or be
lower than VSSby 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on-channel.The full-scale input voltage depends on the voltage at
VREF. See Tables 1a and 1b.
Quick LookTo evaluate the analog performance of the
MAX186/MAX188 quickly, use the circuit of Figure 5.
The MAX186/MAX188 require a control byte to be writ-
ten to DIN before each conversion. Tying DIN to +5V
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
ReferenceZero
ScaleFull ScaleInternal Reference
(MAX186 only)0V+4.096V
at VREF0VVREF
External Reference
at REFADJ
ReferenceNegative
Full Scale
Zero
ScaleInternal Reference
(MAX186 only)-4.096V/20V
External Reference
at REFADJ
-1/2VREFADJ
x A*0V
at VREF-1/2 VREF0V
+4.096V/2
+1/2VREFADJ
x A*
+1/2 VREF
0.1µF
VDD
DGND
AGND
VSS
SCLK
DIN
DOUT
SSTRB
SHDN
+5V
N.C.
0.01µF
CH7
REFADJ
VREF
0.01µF
+2.5V
REFERENCE
4.7µF
1N4148
+5V
0V TO
4.096V
ANALOG
INPUT
+2.5V**
OSCILLOSCOPE
CH1CH2CH3CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**REQUIRED FOR MAX188 ONLY. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.
MAX186
MAX188
+5V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5.Quick-Look Circuit
* A = 1.678 for the MAX186, 1.638 for the MAX188
Table 1b.Bipolar Full Scale, Zero Scale, and
Negative Full Scale
Table 1a.Unipolar Full Scale and Zero Scale
single-ended unipolar conversions on CH7 in external
clock mode without powering down between conver-
sions. In external clock mode, the SSTRB output pulses
high for one clock period before the most significant bit
of the 12-bit conversion result comes out of DOUT.
Varying the analog input to CH7 should alter the
sequence of bits from DOUT. A total of 15 clock cycles
is required per conversion. All transitions of the SSTRB
and DOUT outputs occur on the falling edge of SCLK.
How to Start a ConversionA conversion is started on the MAX186/MAX188 by
clocking a control byte into DIN. Each rising edge on
SCLK, with CSlow, clocks a bit from DIN into the
MAX186/MAX188’s internal shift register. After CSfalls,
the first arriving logic “1” bit defines the MSB of the
control byte. Until this first “start” bit arrives, any num-
ber of logic “0” bits can be clocked into DIN with no
effect. Table 2 shows the control-byte format.
The MAX186/MAX188 are fully compatible with
Microwire and SPI devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. Microwire and SPI
both transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit, the simplest
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
Example: Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode, call
it TB1. TB1 should be of the format: 1XXXXX11
Binary, where the Xs denote the particular channel
and conversion-mode selected.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BitNameDescription7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the eight channels are used for the conversion.SEL1See Tables 3 and 4.SEL0UNI/BIP
1= unipolar, 0= bipolar. Selects unipolar or bipolar conversion mode. In unipolar
mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2. SGL/DIF
1= single ended, 0= differential. Selects single-ended or differential conversions. In
single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. See Tables 3 and 4. PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode
0Full power-down (IQ= 2µA)
1Fast power-down (IQ= 30µA)
0Internal clock mode
1External clock mode
Table 2.Control-Byte Format
Use a general-purpose I/O line on the CPU to pullon the MAX186/MAX188 low.Transmit TB1 and simultaneously receive a byteand call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB2.Transmit a byte of all zeros ($00 HEX) and simulta-
neously receive byte RB3.Pull CSon the MAX186/MAX188 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital OutputIn unipolar input mode, the output is straight binary
(see Figure 15). For bipolar inputs, the output is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7AGND0+–0+–1+–1+–0+–0+–1+–1+ –
Table 3.Channel Selection in Single-Ended Mode (SGL/DDIIFFFF
= 1)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH70+–1+–0+–1+–0–+1–+0–+1–+
Table 4.Channel Selection in Differential Mode (SGL/DDIIFFFF
= 0)
Internal and External Clock Modes
The MAX186/MAX188 may use either an external serial
clock or the internal clock to perform the
successive-approximation conversion. In both clock
modes, the external clock shifts data in and out of the
MAX186/MAX188. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7 through 10 show the timing
characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (see Figure 6).
SSTRB and DOUT go into a high-impedance state whengoes high; after the next CSfalling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
SSTRB
SCLK
DIN
DOUT812162024
STARTSEL2SEL1SEL0UNI/
BIP
SCL/
DIFFPD1PD0
B11
MSBB10B9B8B7B6B5B4B3B2B1B0
LSB
ACQUISITION
1.5μs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1
RB2RB3
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDOtTR
tCSH
Figure 6.24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7.Detailed Serial-Interface Timing
Internal Clock
In internal clock mode, the MAX186/MAX188 generate
their own conversion clock internally. This frees the
microprocessor from the burden of running the SAR con-
version clock, and allows the conversion results to be
read back at the processor’s convenience, at any clock
rate from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the con-
version is complete. SSTRB will be low for a maximum of
10µs, during which time SCLK should remain low for best
noise performance. An internal register stores data when
the conversion is in progress. SCLK clocks the data out
at this register at any time after the conversion is com-
plete. After SSTRB goes high, the next falling clock edge
will produce the MSB of the conversion at DOUT, fol-
lowed by the remaining bits in MSB-first format (see
Figure 9). CSdoes not need to be held low once a con-
version is started. Pulling CShigh prevents data from
being clocked into the MAX186/MAX188 and three-
states DOUT, but it does not adversely effect an internal
clock-mode conversion already in progress. When inter-
nal clock mode is selected, SSTRB does not go into a
high-impedance state when CSgoes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in and
out of the MAX186/MAX188 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time, tAZ,
is kept above 1.5µs.
Low-Power, 8-Channel,
Serial 12-Bit ADCs
MAX186/MAX188
• • •
• • •• • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
tSSTRB
• • •• • •• •
SSTRB
SCLK
DIN
DOUT812182024
STARTSEL2SEL1SEL0UNI/DIPSCL/DIFFPD1PD0
B11MSBB10B9B2B1B0LSB
ACQUISITION
1.5μs (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLECONVERSION
10μs MAXA/D STATE35679101119212223
tCONV
Figure 8.External Clock Mode SSTRBDetailed Timing
Figure 9.Internal Clock Mode Timing
