MAX1858EEG+T ,Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and PORApplicationsPin ConfigurationNetwork Power Supplies TOP VIEWTelecom Power SuppliesCOMP2 1 24 ENDSP, ..
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. 12-Blt Resolutlon and Accuracy
. Fast Conversion Tlmes:
MAX183 - 3ps
MAX184 - 5 ..
MAX185BCWG ,High-Speed 12-Bit A/D Converters With External Refernce inputApplications
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MAX185BCWG ,High-Speed 12-Bit A/D Converters With External Refernce input19-3127; Rena; 4191
[VI llXI/VI
High-Speed 12-Bit A/D Converters
With External Reference Inp ..
MAX185BCWG+ ,3µs, 12-Bit ADCELECTRICAL CHARACTERISTICS
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MAX477ESA ,300MHz High-Speed Op AmpApplicationsSOTPIN-Broadcast and High-Definition TV Systems PART TEMP. RANGE TOPPACKAGEMARKVideo Sw ..
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MAX477ESA+T ,300MHz High-Speed Op AmpApplications Ordering InformationBroadcast and High-Definition TV SystemsPIN- TOPPART TEMP. RANGEPA ..
MAX1858EEG+-MAX1858EEG+T
Dual 180° Out-of-Phase PWM Step-Down Controller with Power Sequencing and POR
General DescriptionThe MAX1858 dual, synchronized, step-down controller
generates two outputs from input supplies ranging from
4.75V to 23V. Each output is adjustable from sub-1V to
18V and supports loads of 10A or higher. Input voltage
ripple and total RMS input ripple current are reduced by
synchronized 180°out-of-phase operation.
The switching frequency is adjustable from 100kHz to
600kHz with an external resistor. Alternatively, the con-
troller can be synchronized to an external clock gener-
ated to another MAX1858 or a system clock. One
MAX1858 can be set to generate an in-phase, or 90°
out-of-phase, clock signal for synchronization with addi-
tional controllers. This allows two controllers to operate
either as an interleaved two- or four-phase system with
each output shifted by 90°. The device also features
“first-on/last-off” power sequencing for compatibility
with DSPs, ASICs, and FPGAs, as well as soft-start and
soft-stop to ensure reliable and repeatable power
sequencing.
The MAX1858 eliminates the need for current-sense
resistors by utilizing the low-side MOSFET’s on-resistance
as a current-sense element. This protects the DC-DC
components from damage during output-overload condi-
tions or when output short-circuit faults without requiring a
current-sense resistor. Adjustable foldback current limit
reduces power dissipation during short-circuit condition.
A power-on reset output signals the system when both
outputs reach regulation.
The MAX1858 is available in a 24-pin QSOP package.
An evaluation kit is available to speed designs.
ApplicationsNetwork Power Supplies
Telecom Power Supplies
DSP, ASIC, and FPGA Power Supplies
Set-Top Boxes
Broadband Routers
Servers
FeaturesTwo Independent Output Voltages180°Out-of-Phase Operation90°Out-of-Phase Operation
(Using Two MAX1858s)Foldback Current Limit4.75V to 23V Input Supply Range0 to 18V Output-Voltage Range (Up to 10A)>90% EfficiencyFixed-Frequency Pulse-Width Modulation (PWM)
OperationAdjustable 100kHz to 600kHz Switching
FrequencyExternal SYNC InputClock Output for Master/Slave SynchronizationPower-On/-Off Sequencing with Soft-Start and
Soft-StopRST
Output with 140ms Minimum DelayLossless Current Limit (No Sense Resistor)
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and PORLX2
DH2
BST2OSC
ILIM2
FB2
COMP2
TOP VIEW
DL2
PGND
DL1CKO
GND
REF
BST1
DH1
LX1
COMP1
FB1
ILIM1
SYNC
QSOPMAX1858
RST
Pin Configuration
Ordering Information19-2432; Rev 0; 7/02
EVALUATION KIT MANUALAVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX1858EEG-40°C to +85°C24 QSOP
Typical Operating Circuit appears at end of data sheet.
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +25V
PGND to GND.......................................................-0.3V to +0.3Vto GND..................-0.3V to the lower of +6V and (V+ + 0.3V)
BST1, BST2 to GND...............................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1..............................................-0.3V to (VBST1+ 0.3V)
DH2 to LX2..............................................-0.3V to (VBST2+ 0.3V)
DL1, DL2 to PGND........................................-0.3V to (VL+ 0.3V)
CKO, REF, OSC, ILIM1, ILIM2,
COMP1, COMP2 to GND..........................-0.3V to (VL+ 0.3V)
FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6Vto GND Short Circuit..............................................Continuous
REF to GND Short Circuit...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL= 0mA, PGND = GND, CREF= 0.22µF, CVL= 4.7µF (ceramic), ROSC= 60kΩ,
compensation components for COMP_ are from Figure 1, TA
= -40°C to +85°C (Note 1), unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITSGENERAL(Note 2) 4.75 23 V+ Operating Range VL = V+ (Note 2) 4.75 5.5 VV+ Operating Supply Current VL unloaded, no MOSFETs connected 3.5 6 mAV+ Standby Supply Current EN = LX_ = FB_ = 0V ROSC = 60kΩ 0.3 0.6 mAThermal Shutdown Rising temperature, typical hysteresis = 10°C 160 °CILIM_ = VL 75 100 125RILIM_ = 100kΩ 32 50 62 Current-Limit Threshold PGND - LX_RILIM_ = 600kΩ 225 300 375mV
VL REGULATOROutput Voltage 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 4.75 5 5.25 VVL Undervoltage Lockout
Trip Level 4.4 4.55 4.7 V
REFERENCEOutput Voltage IREF = 0µA 1.98 2.00 2.02 VReference Load Regulation 0µA < IREF < 50µA 0 4 10 mV
SOFT-STARTDigital Ramp Period Internal 6-bit DAC for one converter to ramp from 0V to
full scale (Note 3) 1024 DC-DC
ClocksSoft-Start Steps 64 Steps
FREQUENCY0°C to +85°C 84 100 115Low End of Range ROSC = 60kΩ -40°C to +85°C 80 100 120 kHz
High End of Range ROSC = 10kΩ 540 600 660 kHz
DH_ Minimum Off-Time ROSC = 10kΩ 250 303 ns
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
ELECTRICAL CHARACTERISTICS (continued)(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL= 0mA, PGND = GND, CREF= 0.22µF, CVL= 4.7µF (ceramic), ROSC= 60kΩ,
compensation components for COMP_ are from Figure 1, TA
= -40°C to +85°C (Note 1), unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITSSYNC Range Internal oscillator nominal frequency must be set to half
of SYNC frequency 200 1200 kHzHigh 100 SYNC Input Pulse Width (Note 3) Low 100 ns
SYNC Rise/Fall Time (Note 3) 100 ns
ERROR AMPLIFIERFB_ Input Bias Current 250 nA0°C to +85°C 0.985 1.00 1.015 FB_ Input Voltage Set Point -40°C to +85°C 0.98 1.00 1.02 V0°C to +85°C 1.25 1.8 2.70 FB_ to COMP_ Transconductance -40°C to +85°C 1.2 1.8 2.9 mS
DRIVERSD L_, D H_ Break-Before-Make TimeCLOAD = 5nF 30 nsLow 1.5 2.5 DH_ On-Resistance High 3 5 ΩLow 0.6 1.5 DL_ On-Resistance High 3 5Ω
LOGIC INPUTS (EN, SYNC)Input Low Level Typical 15% hysteresis, VL = 4.75V 0.8 VInput High Level VL = 5.5V 2.4 VInput High/Low Bias Current VEN = 0 or 5.5V -1 0.1 +1 µA
LOGIC OUTPUTS (CKO)Output Low Level VL = 5V, sinking 5mA 0.4 VOutput High Level VL = 5V, sourcing 5mA 4.0 V
COMP_Pulldown Resistance During
Shutdown and Current Limit 17 ΩRST OUTPUTOutput-Voltage Trip Level Both FBs must be over this to allow the reset timer to
start; there is no hysteresis 0.87 0.9 0.93 VVL = 5V, sinking 3.2mA 0.4 Output Low Level VL = 1V, sinking 0.4mA 0.3 VOutput Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V 1 µAReset Timeout Period VFB_=1V 140 315 560 msFB_ to Reset Delay FB_ overdrive from 1V to 0.85V 4 µs
Note 1:Specifications to -40°C are guaranteed by design and not production tested.
Note 2:Operating supply range is guaranteed by VLline regulation test. Connect V+ to VLfor 5V operation.
Note 3:Guaranteed by design and not production tested.
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Typical Operating Characteristics(Circuit of Figure 1, VIN= 12V, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOADMAX1858 toc01
LOAD (A)
EFFICIENCY (%)1
OUT2
OUT1
OUTPUT-VOLTAGE ACCURACY vs. LOADMAX1858 toc02
LOAD (A)
OUTPUT VOLTAGE ACCURACY (%)5
OUT2
OUT1
VL VOLTAGE ACCURACY
vs. LOAD CURRENTMAX1858 toc03
LOAD CURRENT (mA)
L VOLTAGE ACCURACY
SWITCHING FREQUENCY vs. ROSC
MAX1858 toc04
ROSC (kΩ)
SWITCHING FREQUENCY (kHz)40302010
LOAD TRANSIENT RESPONSE (OUTPUT 1)
MAX1858 toc05
10μs/div
IOUT1
10A
VOUT2
50mV/div
AC-COUPLED
VOUT1
50mV/div
AC-COUPLED
LOAD TRANSIENT RESPONSE (OUTPUT 2)MAX1858 toc06
10μs/div
IOUT2
10A
VOUT1
50mV/div
AC-COUPLED
VOUT2
50mV/div
AC-COUPLED
SOFT-START AND SOFT-STOP WAVEFORMMAX1858 toc07
1ms/div
1V/div
VOUT2
VOUT1
1V/div
VEN
RESET TIMEOUTMAX1858 toc08
100ms/div
VOUT1
VOUT2
5V/div
VRST
OUT-OF-PHASE WAVEFORMMAX1858 toc09
1μs/div
VOUT1
20mV/div
VOUT2
20mV/div
12V
VLX1
VLX2
12V
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
EXTERNALLY SYNCHRONIZED
SWITCHING WAVEFORMMAX1858 toc10
400ns/div
VOUT1
10mV/div
AC-COUPLED
VSYNC
VCK0
VLX1
10V
CKO OUTPUT WAVEFORMMAX1858 toc11
VOUT1
10mV/div
AC-COUPLED
VCK0
VLX1
10V
SYNC = GND
400ns/div
SHORT-CIRCUIT CURRENT
FOLDBACK AND RECOVERYMAX1858 toc13
IOUT1 = 10A (5A/div)
VOUT1 = 1.8V (1V/div)
VOUT2 = 2.5V (1V/div)
IOUT2 = 10A (5A/div)SHORT
VOUT2
CKO OUTPUT WAVEFORMMAX1858 toc12
400ns/div
VOUT1
10mV/div
VCK0
VLX1
10V
SYNC = VL
ypical Operating Characteristics (continued)(Circuit of Figure 1, VIN= 12V, TA = +25°C, unless otherwise noted.)
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Pin Description
PINNAMEFUNCTIONCOMP2
Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series
resistor (RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor
(CCOMP2B) as shown in Figure 1.FB2
Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive-divider between REG2’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB2 to a resistive voltage-divider from REF to REG2’s output. See the Setting the Output
Voltage section.ILIM2
Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to
100mV if ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the
REG2’s current-limit threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See
the Setting the Valley Current Limit section.OSC
Oscillator Frequency Set Input. The controller generates the clock signal by dividing down the
oscillator, so the switching frequency equals half the synchronization frequency (fSW = fOSC/2).
Connect a resistor from OSC to GND (ROSC) to set the switching frequency from 100kHz (ROSC =
60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is
connected to SYNC. When using SYNC, set ROSC for one half of the SYNC input.V+Input Supply Voltage. 4.75V to 23V.REF2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.GNDAnalog GroundCKOClock Output. Clock Output for external 2- or 4-phase synchronization (see the Clock Synchronization
(SYNC, CKO) section).SYNC
Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect
SYNC to a 200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase
operation as a master controller. Connect SYNC to VL for 4-phase operation as a master controller
(see the Clock Synchronization (SYNC, CKO) section).ILIM1
Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to
100mV if ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s
current-limit threshold (VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the
Setting the Valley Current Limit section.FB1
Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive-divider between REG1’s output
and GND to adjust the output voltage between 1V and 18V. To set the output voltage below 1V,
connect FB1 to a resistive voltage-divider from REF and REG1’s output. See the Setting the Output
Voltage section.COMP1
Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series
resistor (RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor
(CCOMP1B) as shown in Figure 1.RST
Open-Drain Reset Output. RST is low when either output voltage is more than 10% below its
regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output
voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high
impedance as long as both outputs maintain regulation. Connect a resistor between RST and the
logic supply for logic-level voltages.
Detailed Description
DC-DC PWM ControllerThe MAX1858 step-down converters use a PWM volt-
age-mode control scheme (Figure 2) for each out-of-
phase controller. The controller generates the clock
signal by dividing down the internal oscillator or SYNC
input when driven by an external clock, so each con-
troller’s switching frequency equals half the oscillator
frequency (fSW= fOSC/2). An internal transconductance
error amplifier produces an integrated error voltage at
the COMP pin, providing high DC accuracy. The volt-
age at COMP sets the duty cycle using a PWM com-
parator and a ramp generator. At each rising edge of
the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty
cycle or until the maximum duty cycle is reached.
REG2 operates out-of-phase, so the second high-side
MOSFET turns on at each falling edge of the clock.
During each high-side MOSFET’s on-time, the associat-
ed inductor current ramps up.
During the second-half of the switching cycle, the high-
side MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
tor current exceeds the selected valley current-limit
(see the Current-Limit Circuit (ILIM_) section), the high-
side MOSFET does not turn on at the appropriate clock
edge and the low-side MOSFET remains on to let the
inductor current ramp down.
Synchronized Out-of-Phase OperationThe two independent regulators in the MAX1858 oper-
ate 180°out-of-phase to reduce input filtering require-
ments, reduce electromagnetic interference (EMI), and
improve efficiency. This effectively lowers component
cost and saves board space, making the MAX1858
ideal for cost-sensitive applications.
Dual-switching regulators typically operate both con-
trollers in-phase, and turn on both high-side MOSFETs
at the same time. The input capacitor must then sup-
port the instantaneous current requirements of both
controllers simultaneously, resulting in increased ripple
voltage and current when compared to a single switch-
ing regulator. The higher RMS ripple current lowers effi-
ciency due to power loss associated with the input
capacitor’s effective series resistance (ESR). This typi-
cally requires more low-ESR input capacitors in parallel
to minimize input voltage ripple and ESR-related loss-
es, or to meet the necessary ripple-current rating.
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
Pin Description (continued)
PINNAMEFUNCTIONDH1High-Side Gate Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1.LX1External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the
inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver.BST1Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic
capacitor and diode according to Figure 1.DL1Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL.PGNDPower GroundVLInternal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers
and external boost circuitry for the high-side gate drivers.DL2Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL.BST2Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic
capacitor and diode according to Figure 1.LX2External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the
inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver.DH2High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2.ENActive-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on
operation.
MAX1858With dual synchronized out-of-phase operation, the
MAX1858’s high-side MOSFETs turn on 180°out-of-
phase. The instantaneous input current peaks of both
regulators no longer overlap, resulting in reduced RMS
ripple current and input voltage ripple. This reduces the
required input capacitor ripple-current rating, allowing
fewer or less expensive capacitors, and reduces shield-
ing requirements for EMI. The Out-of-Phase Waveforms
in the Typical Operating Characteristicsdemonstrate
synchronized 180°out-of-phase operation.
Internal 5V Linear Regulator (VL)All MAX1858 functions are internally powered from an
on-chip, low-dropout 5V regulator. The maximum regu-
lator input voltage (V+) is 23V. Bypass the regulator’s
output (VL) with a 4.7µF ceramic capacitor to PGND.
The VLdropout voltage is typically 500mV, so when V+
is greater than 5.5V, VLis typically 5V. The MAX1858
also employs an undervoltage lockout circuit that dis-
ables both regulators when VLfalls below 4.5V. VL
should also be bypassed to GND with 0.1µF.
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and PORBST1
DH1
LX1
DL1
BST2
DH2
LX2
DL2
FB1
COMP1
*IRF7811W
**OPTIONAL
FB2
COMP2
PGND
REF
GND
OSC
SYNC
CKO
ILIM1
ILIM2EN
OFF
RESET OUTPUT
CLOCK OUTPUT
RST
MAX1858
CV+
0.22μF
CIN1
2 × 10μF
COUT1
4 × 220μF
NH1*
NL1*
1μH
VIN
6V - 23V
CBST1
0.1μF
R1A
8.06kΩ
R1B
10kΩ
CCOMP1B
100pF
CREF
0.22μF
CCOMP2B
100pF
R2B
10kΩ
118kΩ
140kΩ
R2A
15kΩ
4.7Ω4.7Ω
RV+
4.7Ω
NL2*****
NH2*L2
1.2μH
COUT2
4 × 220μF
CIN2
2 × 10μF
OUTPUT2
VOUT = 2.5V
CBST2
0.1μF
CVL
4.7μF
0.1μF
CCOMP2A
6.8nF
RCOMP2
8.2kΩ
96.5kΩ
CMSSH-3
OUTPUT1
VOUT = 1.8V
RCOMP1
5.9kΩ
CCOMP1A
10nF
84.5kΩ
CMSSH-3
Figure 1. Standard Application Circuit
The internal VLlinear regulator can source over 50mA
to supply the IC, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving large FETs, little or no regulator cur-
rent may be available for external loads. For example,
when switched at 600kHz, a single large FET with 18nC
total gate charge requires 18nC x 600kHz = 11mA. To
drive larger MOSFETs, or deliver larger loads, connectto an external power supply from 4.75V to 5.5V.
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and PORCONVERTER 1
ILIM1
DL1
PGND
LX1
DH1
BST1
FB1
COMP1
SOFT-START
DAC
SEQUENCING
OSCILLATOR
OSC
SYNC
CK05V LINEAR
REGULATORGND
REF
DL2
LX2
DH2
BST2
ILIM2FB2
COMP2
CONVERTER 2
RESET
UVLO
AND
SHUTDOWN
VREF
MAX1858
RST
VREF
VL - 0.5V
5μA
Figure 2. Functional Diagram
MAX1858
High-Side Gate-Drive Supply (BST_)Gate-drive voltages for the high-side N-channel switch-
es are generated by the flying-capacitor boost circuits
(Figure 3). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
On startup, the synchronous rectifier (low-side
MOSFET) forces LX_ to ground and charges the boost
capacitor to 5V. On the second half-cycle, after the low-
side MOSFET turns off, the high-side MOSFET is turned
on by closing an internal switch between BST_ and
DH_. This provides the necessary gate-to-source volt-
age to turn on the high-side switch, an action that
boosts the 5V gate-drive signal above VIN. The current
required to drive the high-side MOSFET gates
(fSWITCH ✕QG) is ultimately drawn from VL.
MOSFET Gate Drivers (DH_, DL_)The DH and DL drivers are optimized for driving moder-
ate-size N-channel high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor seen
with large VIN- VOUTdifferential. The DL_ low-side drive
waveform is always the complement of the DH_ high-side
drive waveform (with controlled dead time to prevent
cross-conduction or “shoot-through”). An adaptive dead-
time circuit monitors the DL_ output and prevents the
high-side FET from turning on until DL_ is fully off. There
must be a low-resistance, low-inductance path from the
DL_ driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1858 interprets the MOSFET gate as
“off” while there is actually charge still left on the gate.
Use very short, wide traces (50mils to 100mils wide if the
MOSFET is 1in from the device). The dead time at the
DH-off edge is determined by a fixed 30ns internal delay.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1858 uses the synchronous rectifi-
er to ensure proper startup of the boost gate-driver cir-
cuit and to provide the current-limit signal.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω(typ) on-resistance. This low on-
resistance helps prevent DL_ from being pulled up dur-
ing the fast rise-time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5Ω) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 3).
Current-Limit Circuit (ILIM_)The current-limit circuit employs a “valley” current-
sensing algorithm that uses the on-resistance of the
low-side MOSFET as a current-sensing element. If the
current-sense signal is above the current-limit thresh-
old, the MAX1858 does not initiate a new cycle (Figure
4). Since valley current sensing is employed, the actual
peak current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and
maximum load capability are a function of the low-side
MOSFET’s on-resistance, current-limit threshold, induc-
tor value, and input voltage. The reward for this uncer-
tainty is robust, lossless overcurrent sensing that does
not require costly sense resistors.
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Proceduresection). The current-limit thresh-
old is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, cor-
responding to resistor values of 100kΩto 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
to 100mV when ILIM is tied to VL. The logic threshold
for switchover to this 100mV default value is approxi-
mately VL- 0.5V. Adjustable foldback current limit
reduces power dissipation during short-circuit condi-
tions (see the Design Proceduresection).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
Undervoltage Lockout and StartupIf VLdrops below 4.5V, the MAX1858 assumes that the
supply and reference voltages are too low to make
valid decisions and activates the undervoltage lockout
(UVLO) circuitry which forces DL and DH low to inhibit
switching. RSTis also forced low during UVLO. After VL
rises above 4.5V, the controller powers up the outputs.
Enable (EN), Soft-Start, and Soft-StopPull EN high to enable or low to shutdown both regula-
tors. During shutdown the supply current drops to 1mA
(max), LX enters a high-impedance state (DH_ con-
nected to LX_, and DL_ connected to PGND), and
COMP_ is discharged to GND through a 17Ωresistor.and REF remain active in shutdown. For “always-on”
operation, connect EN to VL.
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and POR
On the rising edge of EN both controllers enter soft-
start. Soft-start gradually ramps up to the reference
voltage seen by the error amplifier in order to control
the outputs’ rate of rise and reduce input surge cur-
rents during startup. The soft-start period is 1024 clock
cycles (1024/fSW), and the internal soft-start DAC
ramps up the voltage in 64 steps. The output reaches
regulation when soft-start is completed. On the falling
edge of EN both controllers simultaneously enter soft-
stop, which reverses the soft-start ramp. The part
enters shutdown after soft-stop is complete.
Output-Voltage SequencingAfter the startup circuitry enables the controller, the
MAX1858 begins the startup sequence. Regulator 1
(OUT1) powers up with soft-start enabled. Once the first
converter’s soft-start sequence ends, Regulator 2 (OUT2)
powers up with soft-start enabled. Finally, when both con-
verters complete soft-start and both output voltages
exceed 90% of their nominal values, the reset output
(RST) goes high (see the Reset Output section). Soft-stop
is initiated by pulling EN low. Soft-stop occurs in reverse
order of soft-start, allowing last-on/first-off operation.
Reset OutputRSTis an open-drain output. RSTpulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regula-
tion voltages and both soft-start cycles are completed,
RSTgoes high impedance. To obtain a logic-voltage out-
put, connect a pullup resistor from RSTto the logic sup-
ply voltage. A 100kΩresistor works well for most appli-
cations. If unused, leave RSTgrounded or unconnected.
Clock Synchronization (SYNC, CKO)SYNC serves two functions: SYNC selects the clock out-
put (CKO) type used to synchronize slave controllers, or
it serves as a clock input so the MAX1858 can be syn-
chronized with an external clock signal. This allows the
MAX1858 to function as either a master or slave. CKO
provides a clock signal synchronized to the MAX1858’s
switching frequency, allowing either in-phase (SYNC =
GND) or 90°out-of-phase (SYNC = VL) synchronization
of additional DC-DC controllers (Figure 5). The
MAX1858 supports the following three operating modes:
SYNC = GND:The CKO output frequency equals
REG1’s switching frequency (fCKO= fDH1) and the
CKO signal is in phase with REG1’s switching fre-
quency. This provides 2-phase operation when syn-
chronized with a second slave controller.
SYNC = VL:The CKO output frequency equals two
times REG1’s switching frequency (fCKO= 2fDH1)
and the CKO signal is phase shifted by 90°with
respect to REG1’s switching frequency. This pro-
vides 4-phase operation when synchronized with a
second MAX1858 (slave controller).
SYNC Driven by External Oscillator:The controller
generates the clock signal by dividing down the
SYNC input signal, so the switching frequency equals
half the synchronization frequency (fSW= fSYNC/2).
REG1’s conversion cycles initiate on the rising edge
of the internal clock signal. The CKO output frequen-
cy and phase match REG1’s switching frequency
(fCKO= fDH1) and the CKO signal is in phase. Note
that the MAX1858 still requires ROSCwhen SYNC is
externally clocked and the internal oscillator frequen-
cy should be set to 50% of the synchronization fre-
quency (fOSC= 0.5fSYNC).
Thermal Overload ProtectionThermal overload protection limits total power dissipation
in the MAX1858. When the device’s die-junction tempera-
ture exceeds TJ= +160°C, an on-chip thermal sensor
shuts down the device, forcing DL_ and DH_ low, allow-
ing the IC to cool. The thermal sensor turns the part on
again after the junction temperature cools by 10°C.
During thermal shutdown, the regulators shut down, RST
goes low, and soft-start is reset. If the VLlinear-regulator
output is short-circuited, thermal-overload protection is
triggered.
MAX1858
Dual 180°Out-of-Phase PWM Step-Down
Controller with Power Sequencing and PORBST_
DH_
LX_
INPUT
(VIN)
MAX1858
Figure 3. Reducing the Switching-Node Rise Time
