MAX1858A-MAX1876A Fast Delivery |IC PHOENIX CO.,LIMITED

MAX1876A ,Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and PORFeaturesThe MAX1858A/MAX1875A/MAX1876A dual, synchro-♦ 4.5V to 23V Input Supply Rangenized, step-do ..
MAX1876AEEG ,Dual 180 Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and PORFeaturesThe MAX1858A/MAX1875A/MAX1876A dual, synchro- 4.5V to 23V Input Supply Rangenized, step-do ..
MAX1876AEEG ,Dual 180 Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and PORELECTRICAL CHARACTERISTICS(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C = 0.22µF, ..
MAX1876AEEG+ ,Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and PORELECTRICAL CHARACTERISTICS(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C = 0.22µF, ..
MAX1876AEEG+T ,Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and PORApplicationsMAX1858AREF 6 19 VLNetwork Power Supplies MAX1875AGND 7 18 PGNDMAX1876ATelecom Power Su ..
MAX1876EEG ,Dual 180 Out-of-Phase PWM Step- Down Controllers with PORELECTRICAL CHARACTERISTICS(V+ = 12V, EN = ILIM_ = V , SYNC = GND, I = 0mA, PGND = GND, C = 0.22µF, ..
MAX481EEPA ,【15kV ESD-Protected, Slew-Rate-Limited, Low-Power, RS-485/RS-422 TransceiversApplicationsIndustrial-Control Local Area Networks__Selection TableRECEIVER/ QUIESCENT NUMBER OFPAR ..
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MAX1858A-MAX1876A
Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and POR
General Description
The MAX1858A/MAX1875A/MAX1876A dual, synchro-
nized, step-down controllers generate two outputs from
input supplies ranging from 4.5V to 23V. Each output is
adjustable from sub-1V to 18V and supports loads of 10A
or higher. Input voltage ripple and total RMS input ripple
current are reduced by synchronized 180°out-of-phase
operation.
The switching frequency is adjustable from 100kHz to
600kHz with an external resistor. Alternatively, the con-
troller can be synchronized to an external clock gener-
ated by another MAX1858A/MAX1875A/MAX1876Aor a
system clock. One MAX1858A/MAX1875A/MAX1876A
can be set to generate an in-phase, or 90°out-of-
phase, clock signal for synchronization with additional
controllers. This allows two controllers to operate either
as an interleaved two- or four-phase system with each
output shifted by 90°. The MAX1858A/MAX1875A/
MAX1876A feature soft-start. The MAX1858A also fea-
tures first-on/last-off power sequencing and soft-stop.
The MAX1858A/MAX1875A/MAX1876A eliminate the
need for current-sense resistors by utilizing the low-side
MOSFET’s on-resistance as a current-sense element.
This protects the DC-DC components from damage dur-
ing output-overload conditions or output short-circuit
faults without requiring a current-sense resistor.
Adjustable foldback current limit reduces power dissipa-
tion during short-circuit conditions. The MAX1858A/
MAX1876A include a power-on reset (POR) output to sig-
nal the system when both outputs reach regulation.
The MAX1858A/MAX1875A/MAX1876A ensure that the
output voltage does not swing negative when the input
power is removed or when EN is driven low. The
MAX1875A/MAX1876A also allow prebias startup with-
out discharging the output.
The MAX1858A/MAX1875A/MAX1876A are available in a
24-pin QSOP package. Use the MAX1875 evaluation kit
or the MAX1858 evaluation kit to evaluate the
MAX1858A/MAX1875A/MAX1876A.
Applications
Network Power Supplies
Telecom Power Supplies
DSP, ASIC, and FPGA Power Supplies
Set-Top Boxes
Broadband Routers
Servers
Desknote Computers
Features4.5V to 23V Input Supply Range0 to 18V Output Voltage Range (Up to 10A)Adjustable Lossless Foldback Current LimitAdjustable 100kHz to 600kHz Switching
FrequencyOptional SynchronizationClock Output for Master/Slave Synchronization4 x 90°Out-of-Phase Step-Down Converters
(Using Two Controllers, Figure 7)Prebias Startup (MAX1875A/MAX1876A)Power Sequencing (MAX1858A)RSTOutput with 140ms Minimum Delay
(MAX1858A/MAX1876A)Fixed-Frequency Pulse-Width Modulation (PWM)
Operation
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
LX2
DH2
BST2OSC
ILIM2
FB2
COMP2
TOP VIEW
DL2
PGND
DL1CKO
GND
REF
BST1
DH1
LX1
COMP1
FB1
ILIM1
SYNC
QSOP
MAX1858A
MAX1875A
MAX1876A
RST (N.C.)
() ARE FOR THE MAX1875A ONLY
Pin Configuration
Ordering Information
19-2966; Rev 0; 10/03
PARTTEMP RANGEPIN-PACKAGE
MAX1858AEEG-40°C to +85°C24 QSOP
MAX1875AEEG-40°C to +85°C24 QSOP
MAX1876AEEG-40°C to +85°C24 QSOP
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +25V
PGND to GND.......................................................-0.3V to +0.3Vto GND..................-0.3V to the lower of +6V and (V+ + 0.3V)
BST1, BST2 to GND...............................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1..............................................-0.3V to (VBST1+ 0.3V)
DH2 to LX2..............................................-0.3V to (VBST2+ 0.3V)
DL1, DL2 to PGND........................................-0.3V to (VL+ 0.3V)
CKO, REF, OSC, ILIM1, ILIM2,
COMP1, COMP2 to GND..........................-0.3V to (VL+ 0.3V)
FB1, FB2, RST, SYNC, EN to GND...........................-0.3V to +6V
VL to GND Short Circuit.............................................Continuous
REF to GND Short Circuit...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.4mW/°C above +70°C)...........762mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL= 0mA, PGND = GND, CREF= 0.22µF, CVL= 4.7µF (ceramic), ROSC= 60kΩ,
compensation components for COMP_ are from Figure 1, TA= -40°C to +85°C (Note 1), unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITSGENERAL(Note 2) 4.5 23.0 V+ Operating Range VL = V+ (Note 2) 4.5 5.5 VV+ Operating Supply Current VL unloaded, no MOSFETs connected 3.5 6 mAV+ Standby Supply Current EN = LX_ = FB_ = 0V 0.3 0.6 mAThermal Shutdown Rising temperature, typical hysteresis = 10°C +160 °CILIM_ = VL 75 100 125RILIM_ = 100kΩ 32 50 62 Current-Limit Threshold PGND - LX_RILIM_ = 600kΩ 225 300 375mVVL REGULATOROutput Voltage 5.5V < V+ < 23V, 1mA < ILOAD < 50mA 4.75 5 5.25 VVL Undervoltage Lockout Rising
Trip Level 4.1 4.2 4.3 VVL Undervoltage Lockout
Hysteresis (Note 3) 100 mVREFERENCEOutput Voltage IREF = 0µA 1.98 2.00 2.02 VReference Load Regulation 0µA < IREF < 50µA 0 4 10 mVSOFT-STARTDigital Ramp Period Internal 6-bit DAC for one converter to ramp from 0V to
full scale (Note 4) 1024 DC-DC
clocksSoft-Start Steps 64 StepsFREQUENCY0°C to +85°C 84 100 115Low End of Range ROSC = 60kΩ -40°C to +85°C 80 100 120 kHz
High End of Range ROSC = 10kΩ 540 600 660 kHz
DH_ Minimum Off-Time ROSC = 10kΩ 250 303 ns
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 12V, EN = ILIM_ = VL, SYNC = GND, IVL= 0mA, PGND = GND, CREF= 0.22µF, CVL= 4.7µF (ceramic), ROSC= 60kΩ,
compensation components for COMP_ are from Figure 1, TA= -40°C to +85°C (Note 1), unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC Range Switching frequency must be set to half of the SYNC
frequency 200 1200 kHzHigh 100 SYNC Input Pulse Width (Note 4) Low 100 ns
SYNC Rise/Fall Time (Note 4) 100 nsERROR AMPLIFIERFB_ Input Bias Current 250 nA0°C to +85°C 0.985 1.00 1.015 FB_ Input Voltage Set Point -40°C to +85°C 0.98 1.00 1.02 V0°C to +85°C 1.25 1.8 2.70 FB_ to COMP_ Transconductance -40°C to +85°C 1.2 1.8 2.9 mSDRIVERSDL_, DH_ Break-Before-Make TimeCLOAD = 5nF 30 nsLow 1.5 2.5 DH_ On-Resistance High 3 5 ΩLow 0.6 1.5 DL_ On-Resistance High 3 5ΩLOGIC INPUTS (EN, SYNC)Input Low Level Typical 15% hysteresis, VL = 4.5V 0.8 VInput High Level VL = 5.5V 2.4 VInput High/Low Bias Current VEN = 0 or 5.5V -1 +0.1 +1 µALOGIC OUTPUTS (CKO)Output Low Level VL = 5V, sinking 5mA 0.4 VOutput High Level VL = 5V, sourcing 5mA 4.0 VCOMP_Pulldown Resistance During
Shutdown and Current Limit 17 ΩRST OUTPUT (MAX1858A/MAX1876A ONLY)Output-Voltage Trip Level Both FBs must be over this to allow the reset timer to
start; there is no hysteresis 0.87 0.9 0.93 VVL = 5V, sinking 3.2mA 0.4 Output Low Level VL = 1V, sinking 0.4mA 0.3 VOutput Leakage V+ = VL = 5V, V RST = 5.5V, VFB = 1V 1 µAReset Timeout Period VFB_ = 1V 140 315 560 msFB_ to Reset Delay FB_ overdrive from 1V to 0.85V 4 µs
Note 1:Specifications to -40°C are guaranteed by design and not production tested.
Note 2:Operating supply range is guaranteed by VLline regulation test. Connect V+ to VLfor 5V operation.
Note 3:When VLfalls and UVLO is tripped, the device is latched and VLmust be discharged below 2.5V before normal operation
can resume.
Note 4:Guaranteed by design and not production tested.
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Typical Operating Characteristics
(Circuit of Figure 1, VIN= 12V, TA = +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD
MAX1858A/75A/76A toc01
LOAD (A)
EFFICIENCY (%)1
OUT2
OUT1
OUTPUT VOLTAGE ACCURACY vs. LOAD
MAX1858A/75A/76A toc02
LOAD (A)
OUTPUT VOLTAGE ACCURACY (%)5
OUT2
OUT1
VL VOLTAGE ACCURACY
vs. LOAD CURRENT
MAX1858A/75A/76A toc03
LOAD CURRENT (mA)
VOLTAGE ACCURACY
SWITCHING FREQUENCY vs. ROSC
MAX1858A/75A/76A toc04
ROSC (kΩ)
SWITCHING FREQUENCY (kHz)40302010
LOAD TRANSIENT RESPONSE (OUTPUT 1)
MAX1858A/75A/76A toc05
10µs/div
IOUT1
10A
VOUT1
50mV/div
AC-COUPLED
VOUT2
50mV/div
AC-COUPLED
LOAD TRANSIENT RESPONSE (OUTPUT 2)
MAX1858A/75A/76A toc06
10µs/div
IOUT2
10A
VOUT1
50mV/div
AC-COUPLED
VOUT2
50mV/div
AC-COUPLED
SOFT-START AND SOFT-STOP WAVEFORM
(MAX1858A ONLY)
MAX1858A/75A/76A toc07
2ms/div
VOUT1
1V/div
IOUT1 = 300mA
VOUT2
1V/div
IOUT2 = 300mA
10V
SOFT-START AND SOFT-STOP WAVEFORM
(MAX1858A ONLY)
MAX1858A/75A/76A toc08
2ms/div
VOUT1
1V/div
IOUT1 = 300mA
VOUT2
1V/div
IOUT2 = 300mA
EN PULLED HIGH BEFORE VOUT1 REACHES 0V.
START AND STOP WAVEFORM
(MAX1875A/MAX1876A ONLY)
MAX1858A/75A/76A toc09
2ms/div
10V
VOUT1
1V/div
IOUT1 = 300mA
VOUT2
1V/div
IOUT2 = 300mA
PREBIAS STARTUP
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
INPUT POWER REMOVAL
MAX1858A/75A/76A toc10
5ms/div
VIN
10V/div
VOUT1
1V/div
IOUT1 = 300mA
VOUT2
1V/div
IOUT2 = 300mA
CKO OUTPUT WAVEFORM
MAX1858A/75A/76A toc14
400ns/div
VOUT1
10mV/div
AC-COUPLED
VCK0
VLX1
10V
SYNC = GND
CKO OUTPUT WAVEFORM
MAX1858A/75A/76A toc15
400ns/div
VOUT1
10mV/div
VCK0
VLX1
10V
SYNC = VL
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, TA = +25°C, unless otherwise noted.)
SHORT-CIRCUIT CURRENT FOLDBACK
AND RECOVERY
MAX1858A/75A/76A toc16
4ms/div
IOUT1 = 10A (5A/div)
VOUT1 = 1.8V (1V/div)
VOUT2 = 2.5V (1V/div)
IOUT2 = 10A (5A/div)VOUT2
SHORT
RESET TIMEOUT
(MAX1858A/MAX1876A ONLY)
MAX1858A/75A/76A toc11
100ms/div, 5V/div
VOUT1
VOUT2
VRST
OUT-OF-PHASE WAVEFORM
MAX1858A/75A/76A toc12
1µs/div
VOUT1
20mV/div
VOUT2
20mV/div
12V
VLX1
VLX2
12V
EXTERNALLY SYNCHRONIZED
SWITCHING WAVEFORM
MAX1858A/75A/76A toc13
400ns/div
VOUT1
10mV/div
AC-COUPLED
VSYNC
VCK0
VLX1
10V
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Pin Description
PINNAMEFUNCTIONCOMP2
Compensation Pin for Regulator 2 (REG2). Compensate REG2’s control loop by connecting a series resistor
(RCOMP2) and capacitor (CCOMP2A) to GND in parallel with a second compensation capacitor (CCOMP2B) as
shown in Figure 1.FB2
Feedback Input for Regulator 2 (REG2). Connect FB2 to a resistive divider between REG2’s output and GND to
adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB2 to a resistive
voltage-divider from REF to REG2’s output. See the Setting the Output Voltage section.ILIM2
Current-Limit Adjustment for Regulator 2 (REG2). The PGND–LX2 current-limit threshold defaults to 100mV if
ILIM2 is connected to VL. Connect a resistor (RILIM2) from ILIM2 to GND to adjust the REG2’s current-limit
threshold (VITH2) from 50mV (RILIM2 = 100kΩ) to 300mV (RILIM2 = 600kΩ). See the Setting the Valley Current
Limit section.OSC
Oscillator Frequency Set Input. Connect a resistor from OSC to GND (ROSC) to set the switching frequency from
100kHz (ROSC = 60kΩ) to 600kHz (ROSC = 10kΩ). The controller still requires ROSC when an external clock is
connected to SYNC. When using an external clock, select ROSC as described above, and set the external clock
frequency to twice the desired switching frequency.V+Input Supply Voltage. 4.5V to 23V.REF2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor.GNDAnalog GroundCKOClock Output. Clock output for external 2- or 4-phase synchronization (see the Clock Synchronization (SYNC,
CKO) section).SYNC
Synchronization Input or Clock Output Selection Input. SYNC has three operating modes. Connect SYNC to a
200kHz to 1200kHz clock for external synchronization. Connect SYNC to GND for 2-phase operation as a master
controller. Connect SYNC to VL for 4-phase operation as a master controller (see the Clock Synchronization
(SYNC, CKO) section).ILIM1
Current-Limit Adjustment for Regulator 1 (REG1). The PGND–LX1 current-limit threshold defaults to 100mV if
ILIM1 is connected to VL. Connect a resistor (RILIM1) from ILIM1 to GND to adjust REG1’s current-limit threshold
(VITH1) from 50mV (RILIM1 = 100kΩ) to 300mV (RILIM1 = 600kΩ). See the Setting the Valley Current Limit section.FB1
Feedback Input for Regulator 1 (REG1). Connect FB1 to a resistive divider between REG1’s output and GND to
adjust the output voltage between 1V and 18V. To set the output voltage below 1V, connect FB1 to a resistive
voltage-divider from REF and REG1’s output. See the Setting the Output Voltage section.COMP1
Compensation Pin for Regulator 1 (REG1). Compensate REG1’s control loop by connecting a series resistor
(RCOMP1) and capacitor (CCOMP1A) to GND in parallel with a second compensation capacitor (CCOMP1B) as
shown in Figure 1.
RST
Open-Drain Reset Output (MAX1858A/MAX1876A Only). RST is low when either output voltage is more than 10%
below its regulation point. After soft-start is completed and both outputs exceed 90% of their nominal output
voltage (VFB_ > 0.9V), RST becomes high impedance after a 140ms delay and remains high impedance as long
as both outputs maintain regulation. Connect a resistor between RST and the logic supply for logic-level
voltages.
N.C.Connect to GND or leave unconnected for the MAX1875A.
Detailed Description
DC-DC PWM Controller
The MAX1858A/MAX1875A/MAX1876A step-down con-
verters use a PWM voltage-mode control scheme (Figure
2) for each out-of-phase controller. The controller gener-
ates the clock signal by dividing down the internal oscil-
lator or SYNC input when driven by an external clock, so
each controller’s switching frequency equals half the
oscillator frequency (fSW= fOSC/2). An internal transcon-
ductance error amplifier produces an integrated error
voltage at the COMP pin, providing high DC accuracy.
The voltage at COMP sets the duty cycle using a PWM
comparator and a ramp generator. At each rising edge
of the clock, REG1’s high-side N-channel MOSFET turns
on and remains on until either the appropriate duty cycle
or until the maximum duty cycle is reached. REG2 oper-
ates out-of-phase, so the second high-side MOSFET
turns on at each falling edge of the clock. During each
high-side MOSFET’s on-time, the associated inductor
current ramps up.
During the second-half of the switching cycle, the high-
side MOSFET turns off and the low-side N-channel
MOSFET turns on. Now the inductor releases the stored
energy as its current ramps down, providing current to
the output. Under overload conditions, when the induc-
tor current exceeds the selected valley current limit (see
the Current-Limit Circuit (ILIM_) section), the high-side
MOSFET does not turn on at the appropriate clock edge
and the low-side MOSFET remains on to let the inductor
current ramp down.
Synchronized Out-of-Phase Operation
The two independent regulators in the MAX1858A/
MAX1875A/MAX1876A operate 180°out-of-phase to
reduce input filtering requirements, reduce electromag-
netic interference (EMI), and improve efficiency. This
effectively lowers component cost and saves board
space, making the MAX1858A/MAX1875A/MAX1876A
ideal for cost-sensitive applications.
Dual-switching regulators typically operate both
controllers in-phase, and turn on both high-side
MOSFETs at the same time. The input capacitor must
then support the instantaneous current requirements of
both controllers simultaneously, resulting in increased
ripple voltage and current when compared to a single
switching regulator. The higher RMS ripple current
lowers efficiency due to power loss associated with the
input capacitor’s effective series resistance (ESR). This
typically requires more low-ESR input capacitors in
parallel to minimize input voltage ripple and ESR-related
losses, or to meet the necessary ripple-current rating.
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
Pin Description (continued)
PINNAMEFUNCTIONDH1High-Side Gate-Driver Output for Regulator 1 (REG1). DH1 swings from LX1 to BST1. DH1 is low during UVLO.LX1External Inductor Connection for Regulator 1 (REG1). Connect LX1 to the switched side of the inductor. LX1
serves as the lower supply rail for the DH1 high-side gate driver.BST1Boost Flying-Capacitor Connection for Regulator 1 (REG1). Connect BST1 to an external ceramic capacitor and
diode according to Figure 1.DL1Low-Side Gate-Driver Output for Regulator 1 (REG1). DL1 swings from PGND to VL. DL1 is low during UVLO.PGNDPower GroundVLInternal 5V Linear-Regulator Output. Supplies the regulators and powers the low-side gate drivers and external
boost circuitry for the high-side gate drivers.DL2Low-Side Gate-Driver Output for Regulator 2 (REG2). DL2 swings from PGND to VL. DL2 is low during UVLO.BST2Boost Flying-Capacitor Connection for Regulator 2 (REG2). Connect BST2 to an external ceramic capacitor and
diode according to Figure 1.LX2External Inductor Connection for Regulator 2 (REG2). Connect LX2 to the switched side of the inductor. LX2
serves as the lower supply rail for the DH2 high-side gate driver.DH2High-Side Gate-Driver Output for Regulator 2 (REG2). DH2 swings from LX2 to BST2. DH2 is low during UVLO.ENActive-High Enable Input. A logic low shuts down both controllers. Connect to VL for always-on operation.
MAX1858A/MAX1875A/MAX1876A
With dual, synchronized, out-of-phase operation, the
MAX1858A/MAX1875A/MAX1876As’ high-side MOSFETs
turn on 180°out-of-phase. The instantaneous input cur-
rent peaks of both regulators no longer overlap, resulting
in reduced RMS ripple current and input voltage ripple.
This reduces the required input capacitor ripple-current
rating, allowing fewer or less expensive capacitors, and
reduces shielding requirements for EMI. The Out-of-
Phase Waveforms in the Typical Operating Charac-
teristicsdemonstrate synchronized 180°out-of-phase
operation.
Internal 5V Linear Regulator (VL)
All MAX1858A/MAX1875A/MAX1876A functions are
internally powered from an on-chip, low-dropout 5V
regulator. The maximum regulator input voltage (V+) is
23V. Bypass the regulator’s output (VL) with a 4.7µF
ceramic capacitor to PGND. The VLdropout voltage is
typically 500mV, so when V+ is greater than 5.5V, VLis
typically 5V. The MAX1858A/MAX1875A/MAX1876A
also employs an undervoltage lockout circuit that dis-
ables both regulators when VLfalls below 4.2V. VL
should also be bypassed to GND with a 0.1µF capaci-
tor. When VLfalls and UVLO is tripped, the device is
latched and VLmust be discharged below 2.5V before
normal operation can resume.
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
BST1
DH1
LX1
DL1
BST2
DH2
LX2
DL2
FB1
COMP1
*IRF7811W
**OPTIONAL
FB2
COMP2
PGND
REF
GND
OSC
SYNC
CKO
ILIM1
ILIM2EN
OFF
RESET OUTPUT
CLOCK OUTPUT
RST (MAX1858A/
MAX1876A ONLY)
MAX1858A
MAX1875A
MAX1876A
CV+
0.22µF
CIN1
2 × 10µF
COUT1
4 × 220µF
NH1*
NL1*
1.1µH
OUTPUT1
VOUT = 1.8V
VIN
6V - 23V
CBST1
0.1µF
R1A
8.06kΩ
R1B
10kΩ
10kΩ
RCOMP1
5.9kΩ
CCOMP1A
0.01µF
CCOMP1B
100pF
CREF
0.22µF
CCOMP2A
6800pF
CCOMP2B
100pF
RCOMP2
8.2kΩR2B
10kΩ
96.5kΩ
140kΩ
R2A
15kΩ
4.7Ω4.7Ω
RV+
4.7Ω
NL2*****
NH2*L2
1.1µH
CMPSH-3A
COUT2
4 × 220µF
CIN2
2 × 10µF
OUTPUT2
VOUT = 2.5V
CBST2
0.1µF
CVL
4.7µF
0.1µF
118kΩ
CMSSH-3
84.5kΩ
CMSSH-3
Figure 1. Standard 600kHz Application Circuit
The internal VLlinear regulator can source over 50mA to
supply the IC, power the low-side gate driver, charge the
external boost capacitor, and supply small external
loads. When driving large FETs, little or no regulator cur-
rent may be available for external loads.
For example, when switched at 600kHz, a single large
FET with 18nC total gate charge requires 18nC ✕600kHz
= 11mA. To drive larger MOSFETs, or deliver larger
loads, connect VLto an external power supply from 4.5V
to 5.5V.
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
CONVERTER 1
ILIM1
DL1
PGND
LX1
DH1
BST1
VL - 0.5V
FB1
COMP1
SOFT-START DAC
(SEQUENCING—
MAX1858A ONLY)
OSCILLATOR
OSC
1VP-P
SYNC
CK05V LINEAR
REGULATORGND
REF
DL2
LX2
DH2
BST2
ILIM2FB2
COMP2
CONVERTER 2
RESET
UVLO
AND
SHUTDOWN
VREF
2.0V
MAX1858A
MAX1875A
MAX1876A
RST
(MAX1858A/
MAX1876A ONLY)
VREF
5µA
Figure 2. Functional Diagram
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and PORNM
DH_
DL_
MAX1875A/MAX1876A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOLDEFINITION
SS_
VOUT_
UVLOABCDEFGHIJKL
Undervoltage lockout trip level is provided in the Electrical Characteristics table.
Internal 5V Linear-Regulator Output
Active-High Enable Input
Output Voltage
Internal Soft-Start Input Signal into Error Amplifier
High-Side Gate-Driver Output
Low-Side Gate-Driver Output
VL rising while below the UVLO threshold. EN is low.
VL is greater than the UVLO threshold. EN is low.
EN is pulled high.
Normal operation
VL enters UVLO.
VL exits UVLO.
Resumes normal operation
EN is pulled low.
EN is pulled high.
Resumes normal operation
VL drops below UVLO threshold while EN is high.
Resumes normal operation
UVLO is activated and DL_ is latched low.
Exiting UVLO: DL_ remains latched low until the first fall of DH_ is detected.
DL_ is low after EN is pulled low.
UVLO
VOUT_
SS_
DH_
DL_
Figure 3. MAX1875A/MAX1876A Detailed Power-On-Off Sequencing
MAX1858A/MAX1875A/MAX1876A
Dual 180°Out-of-Phase Buck Controllers with
Sequencing/Prebias Startup and POR
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
UVLOABCDEFGHIJKMLON
MAX1858A POWER-ON-OFF SEQUENCING DEFINITIONS
SYMBOLDEFINITION
VOUT1
SS1
VOUT2
SS2
DH1
DL1
DH2
DL2
Internal 5V Linear-Regulator Output
Active-High Enable Input
Regulator 1 Output Voltage
Regulator 1: Internal Soft-Start Input Signal into Error Amplifier
Regulator 2 Output Voltage
Regulator 2: Internal Soft-Start Input Signal into Error Amplifier
Regulator 1: High-Side Gate-Driver Output
Regulator 1: Low-Side Gate-Driver Output
Regulator 2: High-Side Gate-Driver Output
Regulator 2: Low-Side Gate-Driver Output
VL rising while below the UVLO threshold. EN is low.
VL is greater than the UVLO threshold. EN is low.
SYMBOLDEFINITION
Normal operation
VL enters UVLO.
VL exits UVLO.
UVLOUndervoltage threshold value is provided in the
Electrical Characteristics table.
EN is pulled high. DH1 and DL1 start switching. DH2 and
DL2 are off.C
Resumes normal operation. DH1 and DL1 start switching.
DH2 and DL2 are off.
EN is pulled low and then high.H
VOUT1 must reach 0V before restarting due to the cycling
of the enable in region H (above).
VOUT1 recovers.
VOUT2 recovers.
VL enters UVLO before VOUT2 fully recovers.
VL exits UVLO.
UVLO latches DL_ low.
Exiting UVLO: DL_ remains latched low until the first fall
of DH_ is detected.
DL_ is high after EN is pulled low and soft-stop is complete.
Figure 4. MAX1858A Detailed Power-On-Off Sequencing

Partno	Mfg	Dc	Qty	Available	Descript
MAX1858A	MAX	N/a	20	avai	Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and POR
MAX1876A	MAX	N/a	30	avai	Dual 180° Out-of-Phase Buck Controllers with Sequencing/Prebias Startup and POR