MAX1813EEI-T ,Dynamically-Adjustable, Synchronous Step-Down Controller with Integrated Voltage PositioningApplicationsTON 10 19 ZMODENotebook Computers REF 11 18 SUS(Intel IMVP–II™/Coppermine™) ILIM 12 17 ..
MAX1817EUB ,Compact / High-Efficiency / Dual-Output Step-Up DC-DC ConverterELECTRICAL CHARACTERISTICS(V = V =V = +3.3V, FB = GND, T = 0°C to +85°C, unless otherwise noted. Ty ..
MAX1817EUB ,Compact / High-Efficiency / Dual-Output Step-Up DC-DC ConverterFeaturesThe MAX1817 is a compact, high-efficiency, dual-out- Dual Step-Up Converter in a Tiny 10-P ..
MAX1817EUB ,Compact / High-Efficiency / Dual-Output Step-Up DC-DC ConverterApplications Ordering InformationOrganizers/Translators PART TEMP. RANGE PIN-PACKAGE MAX1817EUB -40 ..
MAX1817EUB ,Compact / High-Efficiency / Dual-Output Step-Up DC-DC ConverterELECTRICAL CHARACTERISTICS (continued)(V = V = V = +3.3V, FB = GND, T = 0°C to +85°C, unless otherw ..
MAX1817EUB+ ,Compact, High-Efficiency, Dual-Output, Step-Up DC-DC ConverterApplications Ordering InformationOrganizers/Translators PART TEMP. RANGE PIN-PACKAGE MAX1817EUB -40 ..
MAX4684EBC ,0.5 /0.8 Low-Voltage / Dual SPDT Analog Switches in UCSPfeatures a 0.8Ω max on-♦ R Match Between ChannelsONresistance for both NO and NC switches at a +2.7 ..
MAX4684EBC+T ,0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSPELECTRICAL CHARACTERISTICS—+3V SUPPLY(V+ = +2.7V to +3.3V, V = +1.4V, V = +0.5V, T = T to T , unles ..
MAX4684EBC-T ,0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSPfeatures a 0.5Ω (max) R for its NCON♦ NO Switch RONswitch and a 0.8Ω (max) R for its NO switch at a ..
MAX4684EBC-T ,0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSPELECTRICAL CHARACTERISTICS—+3V SUPPLY(V+ = +2.7V to +3.3V, V = +1.4V, V = +0.5V, T = T to T , unles ..
MAX4684EBC-T ,0.5Ω/0.8Ω Low-Voltage, Dual SPDT Analog Switches in UCSPApplications Ordering InformationSpeaker Headset Switching PIN/B U M P- TOPPART TEMP RANGEMARKMP3 ..
MAX4684ETB ,0.5 /0.8 Low-Voltage / Dual SPDT Analog Switches in UCSPApplicationsSpeaker Headset Switching PIN/BUMP-TOPPART TEMP RANGEMARKPACKAGEMP3 PlayersMAX4684EBC - ..
MAX1813EEI-T
Dynamically-Adjustable, Synchronous Step-Down Controller with Integrated Voltage Positioning
General DescriptionThe MAX1813 step-down controller is intended for core
CPU DC-DC converters in notebook computers. The
controller features a dynamically adjustable output (5-
bit DAC), ultra-fast transient response, high DC accura-
cy, and high efficiency necessary for leading-edge
CPU core power supplies. Maxim’s proprietary Quick-
PWM™ quick-response, constant-on-time PWM control
scheme handles wide input/output voltage ratios with
ease and provides 100ns “instant-on” response to load
transients while maintaining a relatively constant switch-
ing frequency.
The MAX1813 is designed specifically for CPU core
applications requiring a voltage-positioned supply. The
voltage-positioning input (VPCS), combined with a
high-DC-accuracy control loop, is used to implement a
power supply that modifies its output set point in
response to the load current. This arrangement
decreases full-load power dissipation and reduces the
required number of output capacitors.
The output voltage can be dynamically adjusted
through the 5-bit digital-to-analog converter (DAC)
inputs over a 0.600V to 2V range. The MAX1813
includes an internal multiplexer that selects between
three different DAC code settings. The first two inputs
are controlled by five digital input pins (D0–D4). The
third input is used for the suspend mode and controlled
by two 4-level input pins (S0, S1). Output voltage transi-
tions are accomplished with a proprietary precision
slew-rate control that minimizes surge currents to and
from the battery while guaranteeing “just-in-time” arrival
at the new DAC setting.
The MAX1813’s 28V input range enables single-stage
buck conversion from high-voltage batteries for the
maximum possible efficiency. Alternatively, the con-
troller’s high-frequency capability combined with two-
stage conversion (stepping down the +5V system
supply instead of the battery) allows the smallest possi-
ble physical size.
The MAX1813 is available in a 28-pin QSOP package.
ApplicationsNotebook Computers
(Intel IMVP–II™/Coppermine™)
Docking Stations
CPU Core Supply
Single-Stage (BATT to VCORE) Converters
Two-Stage (+5V to VCORE) Converters
FeaturesHigh-Efficiency Voltage PositioningQuick-PWM Architecture±1% VOUTAccuracy Over LineAdjustable Output Slew Rate0.600V to 2V Adjustable Output Range (5-Bit DAC)2V to 28V Battery Input Range200/300/600/1000kHz Switching FrequencyOutput Undervoltage and Overvoltage ProtectionDrives Large Synchronous-Rectifier MOSFETs±20% Accurate Current-Limit10µA Shutdown Supply Current2V ±1% Reference OutputPower-Good (PGOOD) IndicatorSmall 28-Pin QSOPPackage
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Ordering Information19-2010; Rev 0; 4/01
PARTTEMP. RANGEPIN-PACKAGEMAX1813EEI-40°C to +85°C28 QSOP
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Coppermine and IMVP-ΙΙare trademarks of Intel Corp.
Typical Operating Circuit appears at end of data sheet.BST
PGND
CODE
ZMODE
SUS
VDD
GND
PGOOD
ILIM
REF
TON
VCC
TIME
SKP/SDN
VPCS
QSOPTOP VIEW
MAX1813
Pin Configuration
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1:SKP/SDNmay be forced to 12V, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto-
type breadboards, using the no-fault test mode.
V+ to GND..............................................................-0.3V to +30V
VCC, VDDto GND.....................................................-0.3V to +6V
PGND to GND.....................................................................±0.3V
D0–D4, CODE, ZMODE, SUS, PGOOD to GND......-0.3V to +6V
SKP/SDNto GND (Note 1).....................................-0.3V to +16V
ILIM, FB, CC, REF,
TON, TIME, S0, S1 to GND......................-0.3V to (VCC+ 0.3V)
VPCS to GND............................................................-2V to +30V
DL to PGND................................................-0.3V to (VDD+ 0.3V)
BST to PGND..........................................................-0.3V to +36V
DH to LX....................................................-0.3V to (VBST+ 0.3V)
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND...........................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin QSOP (derate 10.8mW/°C above +70°C)..........860mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLERBattery voltage, V+228Input Voltage RangeVCC, VDD4.55.5V
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.925V to 2.0V-1+1
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.700V to 0.900V-1.5+1.5DC Output Voltage Accuracy
(Notes 2, 3)
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.600V to 0.675V-1.83+1.83
VPCS Input Bias CurrentIVPSVVPCS = 0 or 28V-1+1μA
VPCS TransconductanceGmVVPCS = 0 to -100mV182022μS
VPCS Linear Input Range±100mV
FB Input ResistanceRFB115180265kΩ
38kHz nominal, RTIME = 470kΩ-12+12
150kHz nominal, RTIME = 120kΩ-8+8TIME Frequency Accuracy
380kHz nominal, RTIME = 47kΩ-12+12
ILIM Input Leakage CurrentIILIMVILIM = 0 or 5.0V0.01100nA
V+ = 5.0V, VFB = 1.2VTON = GND250270290
TON = REF165190215
TON = open320355390On-Time (Note 4)tONV+ = 12V, VFB = 1.2V
TON = VCC465515563
TON = REF, open, or VCC400500Minimum Off-Time (Note 4)tOFF(MIN)TON = GND300375ns
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point1.42.5mA
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSQuiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation point<15μA
Quiescent Supply Current (V+)I+Measured at V+2540μA
Shutdown Supply Current (VCC)SKP/SDN = GND25μA
Shutdown Supply Current (VDD)SKP/ SDN = GND<15μA
Shutdown Supply Current (V+)SKP/SDN = GND, VCC = VDD = 0 or 5V<15μA
Reference VoltageVREFVCC = 4.5V to 5.5V, -40μA ≤ IREF ≤ +40μA1.9822.02V
REF Fault Lockout VoltageFalling edge, 1% hysteresis1.51.61.7V
FAULT PROTECTIONCODE = GND2.202.252.30Output Overvoltage Fault Preset
ThresholdVOVPMeasured at FBCODE = VCC1.952.002.05V
Output Overvoltage Fault
Propagation DelaytOVPFB forced to 2% above trip threshold1.5μs
Output Undervoltage Fault
ThresholdWith respect to unloaded output voltage607080%
Output Undervoltage Fault
Propagation DelayFB forced to 2% below trip threshold10μs
Output Undervoltage Fault-
Blanking Time
From SKP/SDN signal going high, clock
speed set by RTIME256clks
Current-Limit Threshold (Positive,
Default)VITHVGND - VVPCS, ILIM = VCC405060mV
VILIM = 0.5V405060Current-Limit Threshold
(Positive, Adjustable)VITHVGND - VVPCSVILIM = 2V (REF)143200265mV
Negative Current-Limit ThresholdVGND - VVPCS, with respect to VITH, ILIM =
VCC-72-56-40mV
Zero-Crossing Current-Limit
ThresholdVGND - VVPCS5mV
Thermal Shutdown ThresholdRising temperature, hysteresis = 15°C160°C
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, switching
disabled below this level4.054.45V
PGOOD Lower Trip ThresholdMeasured at FB with respect to unloaded
output voltage, falling edge-15-12.5-10.5%
PGOOD Upper Trip ThresholdMeasured at FB with respect to unloaded
output voltage, rising edge81012%
PGOOD Propagation DelayFalling edge, FB forced 2% below or
above PGOOD trip threshold1.5μs
PGOOD Output Low VoltageISINK = 1mA0.4V
PGOOD Leakage CurrentHigh state, forced to 5.5V1μA
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GATE DRIVERSDH Gate Driver On-ResistanceRON (D H ) VBST - VLX forced to 5V1.23.5Ω
High state (pull up)1.33.5DL Gate Driver On-ResistanceRON(DL)Low state (pull down)0.41.0Ω
DH Gate Driver Source/Sink
CurrentIDHDH forced to 2.5V, VBST - VLX forced to 5V2.0A
DL Gate Driver Sink CurrentIDLDL forced to 5V4.0A
DL Gate Driver Source CurrentIDLDL forced to 2.5V1.3A
DL rising35Dead TimeDH rising26ns
LOGIC AND I/OLogic Input High VoltageVIHD0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V2.4V
Logic Input Low VoltageVILD0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V0.8V
DAC Z-Mode Programming
Resistor, Low
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
1.05kΩ
DAC Z-Mode Programming
Resistor, High
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCCkΩ
Pull up40D0−D4, CODE Pull Up/DownEntering impedance
modePull down8kΩ
D0−D4, CODE = VCC-1+1Logic Input CurrentSUS, ZMODE = GND or VCC-1+1μA
4-Level Logic Input High (VCC)TON (200kHz operation), S0, S1VCC -
0.4V
4-Level Logic Input Upper-
Middle (Float)TON (300kHz operation), S0, S12.83.85V
4-Level Logic Input Lower-
Middle (REF)TON (600kHz operation), S0, S11.652.35V
4-Level Logic Low (GND)TON (1000kHz operation), S0, S10.5V
SKP/SDN High Input Level
(Skip Mode)2.86.0V
SKP/SDN Float Input Level
(Forced-PWM Mode)1.42.2V
SKP/SDN Low Input Level
(Shutdown Mode)0.5V
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSKP/SDN NO FAULT Input Level1215V
SKP/SDN, 4-Level Logic Input
CurrentSKP/SDN, TON, S0, S1 = GND or VCC-33μA
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
PWM CONTROLLERBattery voltage, V+228Input Voltage RangeVCC, VDD4.55.5V
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.925V to 2.0V-1+1
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.700V to 0.900V-1.5+1.5DC Output Voltage Accuracy
(Notes 2, 3)
V+ = 4.5V to 28V, VPCS = GND, DAC
codes from 0.600V to 0.675V-1.83+1.83
VPCS Input Bias CurrentIVPSVVPCS = 0 or 28V-1+1μA
VVPS = 0 to -40mV1822VPCS TransconductanceGmVVPS = 0 to -100mV16.522μS
FB Input ResistanceRFB115265kΩ
380kHz nominal, RTIME = 47kΩ-12+12
150kHz nominal, RTIME = 120kΩ-8+8TIME Frequency Accuracy
38kHz nominal, RTIME = 470kΩ-12+12
ILIM Input Leakage CurrentIILIMVILIM = 0 or 5.0V100nA
V+ = 5.0V, VFB = 1.2VTON = GND250290
TON = REF165215
TON = open320390On-Time (Note 4)tONV+ = 12V, VFB = 1.2V
TON = VCC465563
TON = REF, open, or VCC500Minimum Off-Time (Note 4)tOFF(M IN) TON = GND375ns
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point2.5mA
Quiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation point5μA
Quiescent Supply Current (V+)I+Measured at V+40μA
Shutdown Supply Current (VCC)SKP/SDN = GND5μA
Shutdown Supply Current (VDD)SKP/SDN = GND5μA
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINMAXUNITSShutdown Supply Current (V+)SKP/SDN = GND, VCC = VDD = 0 or 5V5μA
Reference VoltageVREFVCC = 4.5V to 5.5V, -40μA ≤ IREF ≤ +40μA1.982.02V
REF Fault Lockout VoltageFalling edge, 1% hysteresis1.51.7V
FAULT PROTECTIONCODE = GND2.202.30Output Overvoltage Fault Preset
ThresholdVOVPMeasured at FBCODE = VCC1.952.05V
Output Undervoltage Fault
ThreshholdWith respect to unloaded output voltage6080%
Current-Limit Threshold
(Positive, Default)VITHVGND - VVPCS, ILIM = VCC4060mV
VILIM = 0.5V4060Current-Limit Threshold
(Positive, Adjustable)VITHVGND - VVPCSVILIM = 2V (REF)143265mV
Negative Current-Limit ThresholdVGND - VVPCS, with respect to VITH,
ILIM = VCC-75-35mV
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV, switching
disabled below this level4.054.45V
PGOOD Lower Trip ThresholdMeasured at FB with respect to unloaded
output voltage, falling edge-15-10.5%
PGOOD Upper Trip ThresholdMeasured at FB with respect to unloaded
output voltage, rising edge812%
PGOOD Output Low VoltageISINK = 1mA0.4V
PGOOD Leakage CurrentHigh state, forced to 5.5V1μA
GATE DRIVERSDH Gate Driver On-ResistanceRON ( D H ) VBST - VLX forced to 5V3.5Ω
High state (pull up)3.5DL Gate Driver On-ResistanceRON(DL)Low state (pull down)1.0Ω
LOGIC AND I/OLogic Input High VoltageVIHD0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V2.4V
Logic Input Low VoltageVILD0−D4, CODE, SUS, ZMODE; VCC = 4.5V
to 5.5V0.8V
DAC Z-Mode Programming
Resistor, Low
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCC
1.05kΩ
DAC Z-Mode Programming
Resistor, High
D0−D4, 0 to 0.4V or 2.6V to 5.5V applied to
the resistor, ZMODE = CODE = GND or
ZMODE = CODE = VCCkΩ
D0−D4, CODE = VCC-1+1Logic Input CurrentSUS, ZMODE = GND or VCC-1+1μA
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Note 2:Output voltage accuracy specifications apply to DAC voltages from 0.6V to 2.0V.
Note 3:When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-com-
parator threshold by 50% of the ripple. In discontinuous conduction (SKP/SDN= VCC, light load), the output voltage will
have a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 4:On-time and off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be differ-
ent due to MOSFET switching speeds.
Note 5:Specifications to -40°C are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = +15V, VCC= VDD= 5V, VPCS = ZMODE = GND = PGND, SKP/SDN= CODE = VCC, VOUTset to 1.5V,
= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS4-Level Logic Input High (VCC)TON (200kHz operation), S0, S1VCC -
0.4V
4-Level Logic Input Upper-
Middle (Float)TON (300kHz operation), S0, S12.83.85V
4-Level Logic Input Lower-
Middle (REF)TON (600kHz operation), S0, S11.652.35V
4-Level Logic Low (GND)TON (1000kHz operation), S0, S10.5V
SKP/SDN High Input Level
(Skip Mode)2.86.0V
SKP/SDN Float Input Level
(Forced-PWM Mode)1.42.2V
SKP/SDN Low Input Level
(Shutdown Mode)0.5V
SKP/SDN NO FAULT Input Level1215V
SKP/SDN, 4-Level Logic Input
CurrentSKP/SDN, TON, S0, S1 = GND or VCC-3+3μA
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Typical Operating Characteristics(Circuit from Figure 1, components from Table 2, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.4V)
MAX1813 toc01
LOAD CURRENT (A)
EFFICIENCY (%)70A1B1C1
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.1V)
MAX1813 toc02
LOAD CURRENT (A)
EFFICIENCY (%)70A1B1C1
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.4V)
MAX1813 toc03
LOAD CURRENT (A)
EFFECTIVE EFFICIENCY (%)A1B1C1C2
EFFECTIVE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.1V)
MAX1813 toc04
LOAD CURRENT (A)
EFFECTIVE EFFICIENCY (%)B1C1C2
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.4V)
MAX1813 toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)VBATT = 24V
VBATT = 7V
PWM MODE
SKIP MODE
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.1V)
MAX1813 toc06
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
VBATT = 24V
VBATT = 7V
PWM MODE
SKIP MODE
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX1813 toc07
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)
PWM MODE
SKIP MODE
VOUT = 1.4V
VBATT = 7V
SWITCHING FREQUENCY
vs. BATTERY INPUT VOLTAGE
MAX1813 toc08
BATTERY INPUT VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
IOUT = 10A
VOUT = 1.4V
VOUT = 1.1V
EFFICIENCY CURVE LEGEND
SKIP MODE (SKIP = GND)A1:V+ = 4.5V
B1:V+ = 7V
C1:V+ = 15V
D1:V+ = 24V
PWM MODE (SKIP = VCC)A2:V+ = 4.5V
B2:V+ = 7V
C2:V+ = 15V
D2:V+ = 24V
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage PositioningSWITCHING FREQUENCY
vs. TEMPERATURE
MAX1813 toc09
TEMPERATURE (°C)
SWITCHING FREQUENCY (kHz)
IOUT = 20A
IOUT = 10A
IOUT = 5A
IOUT = 1A
ON TIME
vs. TEMPERATURE
MAX1813 toc10
TEMPERATURE (°C)
ON TIME (ns)
IOUT = 1A
IOUT = 5A
IOUT = 20A
IOUT = 10A
CURRENT-LIMIT DEVIATION
vs. TEMPERATURE
MAX1813 toc11
TEMPERATURE (°C)
VPCS
DEVIATION (mV)
VILIM = 0.5V
VILIM = 2V
NO-LOAD SUPPLY CURRENT
vs. BATTERY INPUT VOLTAGE (SKIP MODE)
MAX1813 toc12
BATTERY INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
ICC + IDD
VOUT = 1.4V
SKP/SDN = VCC
CODE = ZMODE = GND
IBATT412162024
NO-LOAD SUPPLY CURRENT
vs. BATTERY INPUT VOLTAGE (PWM MODE)MAX1813 toc13
BATTERY INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)
ICC + IDD
IBATT
VOUT = 1.4V
SKP/SDN = FLOAT
CODE = ZMODE = GND
TRANSITION FREQUENCY vs. RTIME
MAX1813 toc14
RTIME (kΩ)
fSLEW
(kHz)100
TA = -40°C, 25°C, 85°C
Typical Operating Characteristics (continued)(Circuit from Figure 1, components from Table 2, TA= +25°C, unless otherwise noted.)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning40μs/div
OUTPUT OVERLOAD WAVEFORM40A
MAX1813 toc18
-100mV
20A
100mV
A. IOUT = 0 TO 40A, (0 to 35mΩ), 20A/div
B. VOUT = 1.4V, 1V/div
C. VPCS, 200mV/div
ILIM = VCC
1.4V
40μs/div
DYNAMIC TRANSITION
(ZMODE TRANSITION)MAX1813 toc19
-10A
1.2V
1.3V
A. VZMODE = 0 TO 5V, 5V/div
B. PGOOD, 5V/div
C. INDUCTOR CURRENT, 10A/div
D. VOUT = 1.3V TO 1.15V, IOUT = 1A, 100mV/div
CODE = VCC
10A
1.1V
40μs/div
DYNAMIC TRANSITION
(SUS TRANSITION)MAX1813 toc20
-5A
1.3V
-15A
A. VSUS = 0 TO 5V, 5V/div
B. PGOOD, 5V/div
C. INDUCTOR CURRENT, 10A/div
D. VOUT = 1.3V TO 0.85V, IOUT = 1A, 500mV/div
CODE = VCC
15A
0.85V
Typical Operating Characteristics (continued)(Circuit from Figure 1, components from Table 2, TA= +25°C, unless otherwise noted.)
20μs/div
LOAD TRANSIENT
(PWM MODE)20A
MAX1813 toc15
1.41V
1.31V
10A
1.36V
A. IOUT = 0.3A TO 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = FLOAT
20μs/div
LOAD TRANSIENT
(SKIP MODE)20A
MAX1813 toc16
1.41V
1.31V
10A
1.36V
A. IOUT = 0.3A TO 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = VCC
20μs/div
LOAD TRANSIENT
(VOLTAGE POSITIONING DISABLED)20A
MAX1813 toc17
1.46V
1.36V
10A
1.41V
A. IOUT = 0.3A to 22A, 10A/div
B. VOUT = 1.4V, 50mV/div
SKP/SDN = FLOAT
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning200μs/div
STARTUP WAVEFORM
(HEAVY LOAD)1.6V
MAX1813 toc21
20A
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, ROUT = 63mΩ, 1V/div
D. INDUCTOR CURRENT, 20A/div
1.4V
200μs/div
STARTUP WAVEFORM
(NO LOAD, PWM MODE)1.6V
MAX1813 toc22
10A
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, NO LOAD, 1V/div
D. INDUCTOR CURRENT, 10A/div
1.4V
200μs/div
STARTUP WAVEFORM
(NO LOAD, SKIP MODE)MAX1813 toc23
10A
A. VSKP/SDN = 0 TO 5V
B. PGOOD, 5V/div
C. VOUT = 1.4V, NO LOAD, 1V/div
D. INDUCTOR CURRENT, 10A/div
1.4VC
40μs/div
SHUTDOWN WAVEFORM1.6V
MAX1813 toc24
1.4V
20A
A. VSKP/SDN = 0 TO 1.6V, 2V/div
B. PGOOD, 5V/div
C. VOUT = 1.4V, ROUT = 63mΩ, 1V/div
D. INDUCTOR CURRENT, 20A/div
Typical Operating Characteristics (continued)(Circuit from Figure 1, components from Table 2, TA= +25°C, unless otherwise noted.)
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Pin Description
PINNAMEFUNCTION1V+Battery Voltage Sense Connection. Connect V+ to the input power source. V+ is used only for PWM
one-shot timing. DH on-time is inversely proportional to the input voltage over a 2V to 28V range.VPCS
Current-Sense Input. Connect a current-sense resistor (RSENSE) between VPCS and PGND. The
voltage on VPCS controls both the voltage-positioning and current-limit circuits. The slope of the
voltage-positioned output is controlled with the current-sense resistor and the gain resistor connected
between CC and REF. See Setting Voltage Positioning. The current-limit threshold is set by ILIM. If the
current-sense signal (inductor current × RSENSE) exceeds the current-limit threshold, the MAX1813
will not initiate a new cycle. VPCS can also be connected to LX to reduce component count, but CC
must be connected to REF to disable the voltage positioning.SKP/SDN
Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown, leave SKP/SDN
open for low-noise forced-PWM mode, or drive to VCC for normal pulse-skipping operation:
Shutdown mode: SKP/SDN = GND
Low-noise forced-PWM mode: SKP/SDN = open
Normal pulse-skipping operation: SKP/SDN = VCCLow-noise forced PWM mode causes inductor current recirculation at light loads and suppresses
pulse-skipping operation. Forcing SKP/SDN with 12V to 15V clears the fault latch and disables
undervoltage protection, overvoltage protection, and thermal shutdown with otherwise normal pulse-
skipping operation. Exiting shutdown clears the fault latch.
Do not connect SKP/SDN to voltages over 15V.TIME
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
470kΩ to 47kΩ resistor sets the clock from 38kHz to 380kHz, respectively:
fSLEW = 150kHz x 120kΩ / RTIME.FBFeed b ack Inp ut. C onnect FB to the j uncti on of the exter nal i nd uctor and outp ut cap aci tor ( Fi g ur e 1) .
6CC
Compensation Capacitor and Voltage-Positioning Gain Adjustment. Connect a 47pF to 1000pF (47pF
typ) capacitor from CC to GND to adjust the loop’s response time. Connect a resistor (RAVPS) from
CC to REF to set the gain of the voltage positioning amplifier.
where the voltage-positioning amplifer’s transconductance (Gm) is typically 20μS.
7, 8S0, S1
Suspend-Mode Voltage Select Inputs. S0 and S1 are 4-level logic inputs that select the suspend-
mode VID code for for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID
code is delivered to the DAC. See Suspend-Mode Internal Mux.
9VCC
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V)
through a series 20Ω resistor. Bypass to GND with a 0.22μF or greater capacitor as close to the
MAX1813 as possible.TON
On-Time Selection-Control Input. This is a 4-level input used to determine DH on-time. Connect to
GND, REF, or VCC, or leave TON unconnected to set the following switching frequencies: GND =
1000kHz, REF = 600kHz, floating = 300kHz, and VCC = 200kHz.GRVOUTOUTPROGmAVPSVPCS
REF() 1
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Pin Description (continued)
PINNAMEFUNCTIONREF
+2.0V Reference Voltage Output. Bypass to GND with a 0.22μF or greater capacitor. The reference
can sink and source ±40μA (min) for external loads. Loading REF degrades FB accuracy according to
the REF load regulation error.ILIM
Current-Limit Adjustment. The PGND - VPCS current-limit threshold defaults to 50mV if ILIM is tied to
VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a
500mV to 2.0V range. The logic threshold for switchover to the 50mV default value is approximately
VCC - 1V. Connect ILIM to REF for a fixed 200mV threshold.PGOOD
Open-Drain Power-Good Output. PGOOD is normally high when the output is in regulation. If VFB is not
within a +10%/-12.5% window of the DAC setting, PGOOD is asserted low. During DAC code
transitions, PGOOD is forced high until 1 clock period after the slew-rate controller finishes the
transition. PGOOD is low in shutdown, undervoltage lockout, and during soft-start. Any fault condition
forces PGOOD low, and it remains low until the fault is cleared.GNDAnalog GroundPGNDPower Ground. PGND is one of the inputs to the current-limit comparator.DLLow-Side Gate-Driver Output. DL swings from GND to VDD. DL is forced high when a fault occurs, and
at the end of the shutdown sequence.VDDSupply Input for the DL Gate Drive. Connect to the system supply voltage (4.5V to 5.5V). Bypass to
PGND with a 1μF or greater capacitor.SUS
Suspend-Mode Control Input. When SUS is high, the suspend-mode VID code, as programmed by S0
and S1, is delivered to the DAC. SUS overrides ZMODE. Connect SUS to GND if the suspend-mode
multiplexer is not used. See Table 6.ZMODE
Performance-Mode Mux Contol Input. If SUS is low, ZMODE selects between two different VID codes.
If ZMODE = GND with CODE = VCC, or ZMODE = VCC with CODE = GND, the VID code is set by the
logic-level voltages on D0−D4. When initially entering impedance mode, the VID code is determined
by the impedance at D0−D4. See Tables 5 and 7.CODE
Code Select Input. CODE acts like another VID code input to select between the Intel Mobile Voltage
Position II (IMVP-II™) or Coppermine™ VID codes. CODE also determines the polarity of the ZMODE
input. See Tables 5 and 7.
21−25D4−D0
VID Code Inputs. D0 is the LSB and D4 is the MSB of the internal 5-bit DAC (see Tables 5 and 7). If
ZMODE = GND with CODE = VCC, or ZMODE = VCC with CODE = GND, D0−D4 are high-impedance
digital inputs, and the VID code is set by the logic-level voltages on D0−D4. When initially entering
impedance mode, the VID code is determined by the impedance at D0−D4 as follows:
Logic Low = source impedance is ≤1kΩ ±5%
Logic High = source impedance is ≥100kΩ ±5%.BST
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the
standard high-power application circuit (Figure 1). An optional resistor in series with BST allows DH
pullup current to be adjusted.LXExternal Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower
supply rail for the DH high-side gate driver. LX does not connect to the current-limit comparator.DHHigh-Side Gate Driver Output. DH swings from LX to BST.
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning
Detailed DescriptionThe MAX1813 buck controller is targeted for low-volt-
age, high-current CPU core power supplies for note-
book computers, which typically exhibit 0 to 22A (or
greater) load steps. The proprietary Quick-PWM pulse-
width modulator in the converter is specifically
designed for handling fast load steps while maintaining
a relatively constant operating frequency and inductor
operating point over a wide range of input voltages.
The Quick-PWM architecture circumvents the poor
load-transient timing problems of fixed-frequency cur-
rent-mode PWMs while also avoiding the problems
caused by widely varying switching frequencies in con-
ventional constant on-time and constant off-time PFM
schemes.
+5V Bias Supply (VCCand VDD)The MAX1813 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply
is the notebook’s 95% efficient +5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
+5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the +5V supply can be generated
with an external linear regulator.
The +5V bias supply powers VCC(PWM controller) and
VDD(gate-drive power). The maximum current is:
IBIAS= ICC+ ƒSW(QG1+ QG2) = 15mA to 45mA (typ)
where ICCis 1.4mA (typ), ƒSWis the switching frequen-
cy, and QG1and QG2are the MOSFETtotal gate-
charge specification limits at VGS= 5V.
The battery input (V+) and +5V bias inputs (VCCand
VDD) can be connected together if the input source is a
fixed 4.5V to 5.5V supply. If the +5V bias supply is
powered up prior to the battery supply, the enable sig-
nal (SKP/SDN) must be delayed until the battery volt-
age is present in order to ensure startup.
Free-Running, Constant-On-Time PWM
Controller with Input Feed-ForwardThe Quick-PWM control architecture is a constant-on-
time, current-mode type with voltage feed-forward
VCC
COUT
0.68μH1.4V OUTPUT
UP TO 22A
PGOOD
ILIM
1μF
CBST
0.1μF
1μFR1
20Ω
CIN
BATTERY (VBATT)
7V TO 24V
TIME
+5V INPUT
BIAS SUPPLY
POWER-GOOD
INDICATOR
BST
VPCS
PGND
GND
ZMODE
TON
VDD
MAX1813
REF
SUS
CODE
TO VCC
OPEN
SUSPEND
MODE
OPEN
RGATE
100kΩ
RTIME
120kΩ
RAVPS
150kΩ
CREF
0.22μF
CCOMP
47pF
OPEN (FORCED-PWM)
OPEN (300kHz)
RSENSE
RVPCS
100Ω
RFB
100Ω
CVPCS
1nF
CFB
1nF
SKP/SDN
NOTE: SEE TABLE 1 FOR COMPLETE LIST OF COMPONENT VALUES
Figure 1. Standard High-Power Application Circuit
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioning(Figure 2). This architecture relies on the output ripple
voltage to provide the PWM ramp signal. Thus, the out-
put filter capacitor’s equivalent series resistance (ESR)
acts as a feedback resistor. The control algorithm is
simple: the high-side switch on-time is determined sole-
ly by a one-shot whose period is inversely proportional
to input voltage and directly proportional to output volt-
age (see On-Time One-Shot). Another one-shot sets a
minimum off-time (400ns typ). The on-time one-shot is
triggered if the error comparator is low, the low-side
switch current is below the current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to the input and output voltages. The high-
side switch on-time is inversely proportional to V+ and
directly proportional to the output voltage as set by the
DAC code. This algorithm results in a nearly constant
switching frequency despite the lack of a fixed-frequen-
cy clock generator. The benefits of a constant switch-
ing frequency are twofold: first, the frequency can be
selected to avoid noise-sensitive regions such as the
455kHz IF band; second, the inductor ripple-current
operating point remains relatively constant, resulting in
COMPONENTCIRCUIT 1
(FIGURE 1)Output Voltage0.6V to 1.75V
Input Voltage Range7V to 24V
Maximum Load Current22A
Inductor
0.68μH
Sumida CDEP134H-0R6 or
Panasonic ETQP6F0R6BFA
Frequency300kHz (TON = float)
High-Side MOSFETInternational Rectifier
(2) IRF7811A
Low-Side MOSFET
Fairchild (3) FDS7764A or
International Rectifier
(3) IRF7822A
Input Capacitor
(6) 10μF, 25V
Taiyo Yuden TMK432BJ106 or
TDK C4532X5R1E106M
Output Capacitor
(6) 220μF
Panasonic
EEFUE0E221R
Current-Sense Resistor1.5mΩ Dale WSL 2512, plus
0.5mΩ copper PC board trace
ILIM LevelVCC (Default)
Voltage-Positioning Gain
Resistor150kΩ
A NUF ACT URER
PH ONEC OUN TRY
CO DE]
WEBSITE
MOSFETsFairchild
Semiconductor
[1] 888-
522-5372www.fairchildsemi.com
International
Rectifier
[1] 310-
322-3331www.irf.com
Siliconix[1] 203-
268-6261www.vishay.com
CapacitorsKemet[1] 408-
986-0424www.kemet.com
Panasonic[1] 847-
468-5624www.panasonic.com
Sanyo65] 281-
3226S i ng ap or e) 1] 408-
749- 9714
www.secc.co.jp
Taiyo Yuden
[03] 3667-
(Japan)
[1] 408-
www.t-yuden.com
InductorsCoilcraft[1] 800-
322-2645www.coilcraft.com
Coiltronics[1] 561-
752-5000www.coiltronics.com
Sumida[1] 408-
982-9660www.sumida.com
Table 1. Component Selection for
Standard Applications
Table 2. Component Suppliers
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage PositioningTOFF
ONE-SHOT
TON
GND
VCC
REF
PGOOD
VPCS
CHIP
SUPPLY
FROM
DAC
TRIGQSET
CLRR
TON
ONE-SHOT
REF
REF
+10%
5-BIT
R-2R
DAC
REF
-12%
TRIGQSET
CLRR
VPCS
BST
VBATT
5V TO 24V
5V BIAS
SUPPLY
ILIMV+
REF
PGND
VDDCODEZMODED1D2D3D4
SUS
TIME
SOFT-START
ZERO
CROSSING
REF
SKP/SDN
TON
COMPUTE
OVP/UVP
DETECT
OSC
DECODER
(SEE FIGURE 6)
AND
SLEW-RATE CONTROLLER
MAX1813
BIAS
VOUT
Figure 2. Functional Diagram
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioningeasy design methodology and predictable output volt-
age ripple.
where K is set by the TON pin-strap connection, and
75mV is an approximation to accommodate for the
expected drop across the low-side MOSFET switch and
current-sense resistor (Table 3).
The on-time one-shot has good accuracy at the operat-
ing points specified in the Electrical Characteristics
table. On-times at operating points far removed from
the conditions specified can vary over a wide range.
For example, the 1000kHz setting will typically run
about 10% slower with inputs much greater than +5V,
due to the very short on-times required.
Although the on-time is set by TON, the input voltage,
and the output voltage, other factors also contribute to
the overall switching frequency. The on-time guaran-
teed in the Electrical Characteristicstable is influenced
by switching delays in the external high-side MOSFET.
Resistive losses—including the inductor, both
MOSFETs, output capacitor ESR, and PC board copper
losses in the output and ground—tend to raise the
switching frequency at higher output currents. Switch
dead-time can increase the effective on-time, reducing
the switching frequency. This effect occurs only in
PWM mode (SKP/SDN= float) when the inductor cur-
rent reverses at light or negative load currents. With
reversed inductor current, the inductor’s EMF causes
LX to go high earlier than normal, extending the on-time
by a period equal to the DH-rising dead-time (26ns
typ).
When the controller operates in continuous
mode, the dead-time is no longer a factor, and the
actual switching frequency is:
where VDROP1is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
tances; and tONis the on-time calculated by the
MAX1813.
Automatic Pulse-Skipping SwitchoverIn skip mode (SKP/SDN= high, Table 4), an inherent
automatic switchover to PFM takes place at light
loads (Figure 3). This switchover is controlled by a
comparator that truncates the low-side switch on-time
at the inductor current’s zero crossing. This mechanism
causes the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation. For a 7V to 24V input volt-
age range, this threshold is relatively constant, with+SWOUTDROP1INDROP1DROP2V)
t(VVV)K(V75mV)ONOUT=+
TON SETTING
(kHz)
K-FACTOR
(μs)
APPROXIMATE
K-FACTOR ERROR
(%)
MINIMUM RECOMMENDED VBATT
AT VOUT = 1.4V (V)2004.9±91.8
3003.3±102.0
6001.8±132.9
10001.05±133.5
Table 3. Approximate K-Factor ErrorsINDUCTOR CURRENT
ILOAD = IPEAK/2
ON-TIME0TIME
IPEAKL
VBATT - VOUTΔi=
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioningonly a minor dependence on the input voltage:
where K is the on-time scale factor (Table 3). The load-
current level at which PFM/PWM crossover occurs
(ILOAD(SKIP)) is equal to 1/2 the peak-to-peak ripple
current, which is a function of the inductor value (Figure
3). For example, in the standard application circuit with
K = 3.3µs (300kHz), VIN= 12V, VOUT= 1.4V, and L =
0.68µH, switchover to pulse-skipping operation occurs
at ILOAD= 3.0A or about 1/4 full load. The crossover
point occurs at an even lower value if a swinging (soft-
saturation) inductor is used.
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation; this is a normal operating condition that
improves light-load efficiency. Trade-offs in PFM noise
vs. light-load efficiency are made by varying the induc-
tor value. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input voltage levels).
Forced-PWM ModeThe low-noise, forced-PWM mode (SKP/SDNleft float-
ing, Table 4) disables the zero-crossing comparator
that controls the low-side switch on-time. The resulting
low-side gate-drive waveform is forced to be the com-
plement of the high-side gate-drive waveform. This, in
turn, causes the inductor current to reverse at light
loads because the PWM loop strives to maintain a duty
ratio of VOUT/VIN. The benefit of forced-PWM mode is
to keep the switching frequency nearly constant, but it
results in higher no-load supply current that can be
15mA to 45mA, depending on the external MOSFETs
and switching frequency.
The MAX1813 uses forced-PWM mode during all transi-
tions, while the slew-rate controller is active. During
downward output voltage transitions, forced-PWM
allows the MAX1813 to sink current, thereby rapidly
pulling down the output voltage. When a transition uses
high negative inductor current, due to voltage position-
ing, the output voltage may not settle to its intended
final value until after the slew-rate controller terminates.
For this reason, most applications should use PWM
mode exclusively, although skip mode is beneficial in
the low-power suspend state (see Shutdown and Mode
Control).
Shutdown and Mode Control (SKP/SDN)When SKP/SDNis driven low, the MAX1813 enters the
low-current shutdown mode (Table 4). Shutdown forces
PGOOD low immediately and ramps down the output
voltage in 25mV increments at the clock rate set by
RTIME. Once the output voltage ramps down, the
MAX1813 pulls DH low, forces DL high, and shuts
down the reference, so the total supply current (ICC+
IDD+ I+) drops to 4µA (typ).
When SKP/SDNis left floating or driven high, the
MAX1813 begins the startup sequence. First, the refer-
ence powers up. After the reference exceeds its 1.6V
undervoltage lockout threshold, the DAC determines
the target output voltage and starts ramping up the out-
put voltage. The slew-rate controller increases the out-
IK VLOAD(SKIP)OUTINOUT≈−
SKP/SDNDLMODECOMMENTSGNDHighShutdownMicropower shutdown state (ICC = 2μA typ).
VCCSwitchingNormal
Operation
Automatic switchover from PWM mode to pulse-skipping PFM mode at
light loads. Prevents inductor current from recirculating into the input.
FloatSwitchingForced PWMLow-noise forced-PWM mode causes inductor current to reverse at
light loads and suppresses pulse-skipping operation.
12VSwitchingNO-FAULT Test
Mode
Test mode with overvoltage, undervoltage, and thermal shutdown
faults disabled. Otherwise, the converter operates as if SKP/SDN =
VCC.
VCC or FloatHighFAULT
The fault latch set by the overvoltage protection, output undervoltage
protection, or thermal shutdown. The MAX1813 will remain in FAULT
mode until VCC power is cycled or SKP/SDN is forced low.
Table 4. Operating Mode Truth Table
MAX1813
Dynamically-Adjustable, Synchronous Step-Down
Controller with Integrated Voltage Positioningput voltage in 25mV increments at the clock rate set by
RTIMEuntil the MAX1813 reaches the selected output
voltage. The MAX1813 does not feature traditional vari-
able current-limit soft-start, so full output current is
immediately available. Once the slew-rate controller ter-
minates, output undervoltage fault blanking period
ends, and the output voltage is in regulation, PGOOD
goes high.
Leave SKP/SDNfloating for forced-PWM operation, or
connect SKP/SDNto VCCfor normal operation. During
all transitions, the MAX1813 uses PWM mode while the
slew-rate controller is active. Exiting shutdown clears
the fault latch.
Current-Limit Circuit (ILIM)The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm. If the current-sense signal is
above the current-limit threshold, the MAX1813 will not
initiate a new cycle (Figure 4). The actual peak current
is greater than the current-limit threshold by an amount
equal to the inductor ripple current. Therefore the exact
current-limit characteristic and maximum load capabili-
ty are a function of the current-limit threshold, inductor
value, and input voltage. The reward for this uncertainty
is robust, loss-less over-current sensing. When com-
bined with the undervoltage protection circuit, this cur-
rent-limit method is effective in almost every
circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when VOUTis sink-
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
therefore tracks the positive current limit when ILIM is
adjusted.
The MAX1813 measures the current by sensing the
voltage between VPCS and PGND. Connect an external
sense resistor between the source of the low-side N-
channel MOSFET and PGND. The signal provided by
this current-sense resistor is also used for voltage posi-
tioning (see Setting Voltage Positioning). Reducing the
sense voltage increases the relative measurement
error. However, the configuration eliminates the uncer-
tainty of using the low-side MOSFET on-resistance to
measure the current, so the resulting current-limit toler-
ance is tighter when sensing with a 1% sense resistor.
The voltage at ILIM sets the current-limit threshold. For
voltages from 500mV to 2V, the current-limit threshold
voltage is precisely 0.1 x VILIM. Set this voltage with a
resistive divider between REF and GND. The current-
limit threshold defaults to 50mV when ILIM is tied to
VCC. The logic threshold for switchover to this 50mV
default value is approximately VCC- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur-
rent-sense signals seen by VPCS and GND. The IC
must be mounted close to the current-sense resistor
with short, direct traces making a Kelvin sense connec-
tion (see PC Board Layout Guidelines).
MOSFET Gate Drivers (DH and DL)The DH and DL drivers are optimized for driving mod-
erate-sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN- VOUTdifferential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate for the adaptive dead-time
circuit to work properly. Otherwise, the sense circuitry
in the MAX1813 will interpret the MOSFET gate as “off”
while there is actually charge still left on the gate. Use
very short, wide traces (50 to 100 mils wide if the MOS-
FET is 1 inch from the device). The dead time at the
other edge (DH turning off) is determined by a fixed
35ns internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω(typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time
of the LX node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor
INDUCTOR CURRENT
ILIMIT
ILOADTIME
IPEAK
Figure 4. “Valley” Current-Limit Threshold Point
