MAX17036GTL+ ,1/2/3-Phase Quick-PWM IMVP-6.5 VID ControllersMAX17030/MAX1703619-4577; Rev 1; 8/091/2/3-Phase Quick-PWMIMVP-6.5 VID Controllers
MAX17036GTL+T ,1/2/3-Phase Quick-PWM IMVP-6.5 VID ControllersFeatures♦ Triple/Dual-Phase Quick-PWM ControllersThe MAX17030/MAX17036 are 3/2-phase interleavedQui ..
MAX17039GTN+ ,Dual-Output, 3-Phase + 1-Phase Quick-PWM Controller for VR12/IMVP7FeaturesThe MAX17039 is a dual-output, step-down, constant- S Supports all Required IMVP-7 Function ..
MAX17039GTN+T ,Dual-Output, 3-Phase + 1-Phase Quick-PWM Controller for VR12/IMVP7features detect a fault, the controller shuts down both channels.S Accurate Droop and Current Limit ..
MAX1703ESE ,1-Cell to 3-Cell / High-Power 1.5A / Low-Noise / Step-Up DC-DC ConverterApplicationsMAX848/MAX849.Digital Cordless Phones Personal CommunicatorsThe MAX1703 evaluation kit ..
MAX1703ESE ,1-Cell to 3-Cell / High-Power 1.5A / Low-Noise / Step-Up DC-DC ConverterELECTRICAL CHARACTERISTICS (continued)(CLK/SEL = AIN = ON = POKIN = FB = PGND = GND, OUT = POUT, LX ..
MAX4522CPE ,Quad / Low-Voltage / SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4522CSE ,Quad / Low-Voltage / SPST Analog SwitchesFeaturesThe MAX4521/MAX4522/MAX4523 are quad, low-volt-' +2V to +12V Single Supplyage, single-pole/ ..
MAX4522CSE ,Quad / Low-Voltage / SPST Analog SwitchesApplications______________Ordering InformationBattery-Operated EquipmentPART TEMP. RANGE PIN-PACKAG ..
MAX4522CUE ,Quad, Low-Voltage SPST Analog SwitchesApplicationsMAX4521CPE 0°C to +70°C 16 Plastic DIPBattery-Operated EquipmentMAX4521CSE 0°C to +70°C ..
MAX4522CUE+ ,Quad, Low-Voltage SPST Analog SwitchesApplicationsMAX4521CPE 0°C to +70°C 16 Plastic DIPBattery-Operated EquipmentMAX4521CSE 0°C to +70°C ..
MAX4522EEE ,Quad / Low-Voltage / SPST Analog SwitchesGeneral Description ________
MAX17030GTL+-MAX17030GTL+T-MAX17036GTL+-MAX17036GTL+T
1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
General DescriptionThe MAX17030/MAX17036 are 3/2-phase interleaved
Quick-PWM™ step-down VID power-supply controllers
for IMVP-6.5 notebook CPUs. Two integrated drivers and
the option to drive a third phase using an external driver
such as the MAX8791 allow for a flexible 3/2-phase con-
figuration depending on the CPU being supported.
True out-of-phase operation reduces input ripple-current
requirements and output-voltage ripple while easing
component selection and layout difficulties. The Quick-
PWM control provides instantaneous response to fast
load-current steps. Active voltage positioning reduces
power dissipation and bulk output capacitance require-
ments and allows ideal positioning compensation for tan-
talum, polymer, or ceramic bulk output capacitors.
The MAX17030/MAX17036 are intended for bucking
down the battery directly to create the core voltage.
The single-stage conversion method allows this device
to directly step down high-voltage batteries for the
highest possible efficiency.
A slew-rate controller allows controlled transitions
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. An
output current monitor provides an analog current out-
put proportional to the sum of the inductor currents,
which in steady state is the same as the current con-
sumed by the CPU.
ApplicationsIMVP-6.5 SV and XE Core Power Supplies
High-Current Voltage-Positioned Step-Down
Converters
3 to 4 Li+ Cells Battery to CPU Core Supply
Converters
Notebooks/Desktops/Servers
FeaturesTriple/Dual-Phase Quick-PWM Controllers2 Internal Drivers + 1 External Driver±0.5% VOUTAccuracy Over Line, Load, and
Temperature7-Bit IMVP-6.5 DACDynamic Phase Selection Optimizes Active/Sleep
EfficiencyTransient Phase Overlap Reduces Output
CapacitanceTransient Suppression Feature (MAX17036 Only)Integrated Boost SwitchesActive Voltage Positioning with Adjustable GainAccurate Lossless Current Balance and
Current LimitRemote Output and Ground SenseAdjustable Output Slew-Rate ControlPower-Good (IMVPOK), Clock Enable (CLKEN),
and Thermal-Fault (VRHOT) OutputsIMVP-6.5 Power Sequencing and Timing
CompliantOutput Current Monitor (IMON)Drives Large Synchronous Rectifier FETs7V to 26V Battery Input RangeAdjustable Switching Frequency (600kHz max)Undervoltage, Overvoltage, and Thermal-Fault
Protection
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID ControllersBST1LX1DL1V
DH2LX2BST2VRHOTDL2DH1
THRM
IMON
ILIM
TIMEFB
FBAC
GNDS
CSP3
CSN3
SHDN
TON
DRSKP
PWM3
DPRSLPVR
PSI
CSP2
CSN2
CSP1
PGD_IN
CSN1
PWRGD
MAX17030
MAX17036
THIN QFN
5mm x 5mmTOP VIEW45672829302624232210
CLKEN
Pin Configuration
Ordering Information19-4577; Rev 1; 8/09
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGE
MAX17030GTL+ -40°C to +105°C 40 TQFN-EP*
MAX17036GTL+ -40°C to +105°C 40 TQFN-EP*
+Denotes a lead-free(Pb)/RoHS-compliant package.
*EP = Exposed pad.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ABSOLUTE MAXIMUM RATINGS
(Note 1)
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VDDto GND.....................................................-0.3V to +6V
D0–D6, PGD_IN, PSI, DPRSLPVR to GND...............-0.3V to +6V
CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V
PWRGD, CLKEN, VR_HOTto GND..........................-0.3V to +6V
FB, FBAC, IMON, TIME to GND.................-0.3V to (VCC+ 0.3V)
SHDNto GND (Note 2)...........................................-0.3V to +30V
TON to GND...........................................................-0.3V to +30V
GNDS to GND.......................................................-0.3V to +0.3V
DL1, DL2, PWM3, DRSKPto GND.............-0.3V to (VDD+ 0.3V)
BST1, BST2 to GND...............................................-0.3V to +36V
BST1, BST2 to VDD.................................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1..............................................-0.3V to (VBST1+ 0.3V)
DH2 to LX2..............................................-0.3V to (VBST2+ 0.3V)
Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN)
Up to +70°C..............................................................1778mW
Derating above +70°C..........................................22.2mW/°C
Operating Temperature Range.........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +165°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLER VCC, VDD 4.5 5.5 Input Voltage Range
VIN 7 26
DAC codes from
0.8125V to 1.5000V -0.5 +0.5 %
DAC codes from
0.3750V to 0.8000V -7 +7 FB Output Voltage Accuracy VFB
Measured at FB
with respect to
GNDS;
includes load-
regulation error
(Note 3) DAC codes from
0 to 0.3625V -20 +20
mV
Boot Voltage VBOOT 1.094 1.100 1.106 V
Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.1 %
FB Input Bias Current TA = +25°C -0.1 +0.1 μA
GNDS Input Range -200 +200 mV
GNDS Gain AGNDS VOUT/VGNDS 0.97 1.00 1.03 V/V
GNDS Input Bias Current IGNDS TA = +25°C -0.5 +0.5 μA
TIME Regulation Voltage VTIME RTIME = 147k 1.985 2.000 2.015 V
RTIME = 147k (6.08mV/μs nominal) -10 +10
RTIME = 35.7k (25mV/μs nominal) to
178k (5mV/μs nominal) -15 +15
TIME Slew-Rate Accuracy
Soft-start and soft-shutdown:
RTIME = 35.7k (6.25mV/μs nominal) to
178k (1.25mV/μs nominal)
-20 +20
Note 1:Absolute Maximum Ratings valid using 20MHz bandwidth limit.
Note 2:SHDNmight be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal
BST switches are disabled as well. Use external BST diodes when SHDNis forced to 12V.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RTON = 96.75k (600kHz
per phase), 167ns nominal -15 +15
RTON = 200k (300kHz
per phase), 333ns nominal -10 +10 On-Time AccuracytON
VIN = 10V,
VFB = 1.0V,
measured at
DH1, DH2,
and PWM3
(Note 4) RTON = 303.25k (200kHz
per phase), 500ns nominal -15 +15
Minimum Off-Time tOFF(MIN) Measured at DH1, DH2, and PWM3 (Note 4) 300 375 ns
TON Shutdown Input Current ITON,SDN SHDN = GND, VIN = 26V, VCC = VDD = 0
or 5V, TA = +25°C 0.01 0.1 μA
BIAS CURRENTSQuiescent Supply Current (VCC) ICC Measured at VCC, VDPRSLPVR = 5V, FB
forced above the regulation point 3.5 7 mA
Quiescent Supply Current (VDD) IDD Measured at VDD, VDPRSLPVR = 0, FB forced
above the regulation point, TA = +25°C 0.02 1 μA
Shutdown Supply Current (VCC) ICC,SDN Measured at VCC,SHDN = GND, TA = +25°C 0.01 1 μA
Shutdown Supply Current (VDD) IDD,SDN Measured at VDD,SHDN = GND, TA = +25°C 0.01 1 μA
FAULT PROTECTIONSkip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250 300 350 mV
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45 1.50 1.55
Output Overvoltage-Protection
Threshold VOVP
Minimum OVP threshold; measured at FB 0.8
Output Overvoltage-
Propagation Delay tOVP FB forced 25mV above trip threshold 10 μs
Output Undervoltage-
Protection Threshold VUVP Measured at FB with respect to the voltage
target set by the VID code (see Table 4) -450 -400 -350 mV
Output Undervoltage-
Propagation Delay tUVP FB forced 25mV below trip threshold 10 μs
CLKEN Startup Delay and
Boot Time Period tBOOTMeasured from the time when FB reaches
the boot target voltage (Note 3) 20 60 100 μs
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWRGD Startup Delay Measured at startup from the time when
CLKEN goes low 3 6.5 10 ms
Lower threshold,
falling edge
(undervoltage)
-350 -300 -250
CLKEN and PWRGD Threshold
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4), 20mV
hysteresis (typ)
Upper threshold,
rising edge
(overvoltage)
+150 +200 +250
mV
CLKEN and PWRGD Delay FB forced 25mV outside the PWRGD trip
thresholds 10 μs
CLKEN and PWRGD Transition
Blanking Time (VID Transitions) tBLANK Measured from the time when FB reaches
the target voltage (Note 3) 20 μs
CLKEN, PWRGD Output
Low Voltage Low state, ISINK = 3mA 0.4 V
CLKEN, PWRGD Leakage
Current High-Z state, pin forced to 5V, TA = +25°C 1 μA
CSN1 Pulldown Resistance in
UVLO and Shutdown
SHDN = GND, measured after soft-
shutdown completed (DL = low) 8
VCC Undervoltage-Lockout
Threshold VUVLO(VCC) Rising edge, 65mV typical hysteresis,
controller disabled below this level 4.05 4.27 4.48 V
THERMAL PROTECTIONVRHOT Trip Threshold Measured at THRM with respect to VCC;
falling edge, typical hysteresis = 75mV 29 30 31 %
VRHOT Delay tVRHOTTHRM forced 25mV below the VRHOT trip
threshold, falling edge 10 μs
VRHOT Output On-Resistance RON(VRHOT)Low state 2 8
VRHOT Leakage Current High-Z state, VRHOT forced to 5V, TA = +25°C 1 μA
THRM Input Leakage ITHRM VTHRM = 0 to 5V, TA = +25°C -0.1 +0.1 μA
Thermal-Shutdown Threshold TSHDN Typical hysteresis = 15°C +160 °C
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITORVTIME - VILIM = 100mV 7 10 13
VTIME - VILIM = 500mV 45 50 55 Current-Limit Threshold Voltage
(Positive) VLIMITVCSP_ - VCSN_
ILIM = VCC 20 22.5 25
mV
Current-Limit Threshold Voltage
(Negative) Accuracy VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT-4 +4 mV
Current-Limit Threshold Voltage
(Zero Crossing) VZX VGND - VLX_, VDPRSLPVR = 5V 0 mV
CSP_, CSN_ Common-Mode
Input Range 0 2 V
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 3 VCC -
VCC -
0.4 V
CSP_, CSN_ Input Current ICSP, ICSN TA = +25°C -0.2 +0.2 μA
ILIM Input Current IILIMTA = +25°C -0.1 +0.1 μA
TA = +25°C -0.5 +0.5
Droop Amplifier Offset
(1/N) x (VCSP_ -
VCSN_) at IFBAC = 0;
indicates
summation over all
power-up enabled
phases from 1 to N,
N = 3
TA = 0°C to +85°C -0.75 +0.75
mV/
phase
Droop Amplifier
Transconductance Gm(FBAC)
IFBAC/[(VCSP_ - VCSN_)];
indicates summation over all power-up
enabled phases from 1 to N, N = 3,
VFBAC = VCSN_ = 0.45V to 1.5V
393 400 406 μS
Current-Monitor Offset
(1/N) x (VCSP_ - VCSN_) at IIMON = 0,
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1.1 +1 mV/
phase
Current-Monitor
Transconductance Gm(IMON)
IIMON/[(VCSP_ - VCSN_)];
indicates summation over all power-up
enabled phases from 1 to N, N = 3,
VCSN_ = 0.45V to 1.5V
1.552 1.6 1.648 mS
GATE DRIVERSHigh state (pullup) 0.9 2.5 DH_ Gate-Driver On-Resistance RON(DH) BST_ - LX_ forced
to 5V Low state (pulldown) 0.7 2
High state (pullup) 0.7 2 DL_ Gate-Driver On-Resistance RON(DL) Low state (pulldown) 0.25 0.7
DH_ Gate-Driver Source Current IDH(SOURCE) DH_ forced to 2.5V,
BST_ - LX_ forced to 5V 2.2 A
DH_ Gate-Driver Sink Current IDH(SINK) DH_ forced to 2.5V,
BST_ - LX_ forced to 5V 2.7 A
DL_ Gate-Driver Source Current IDL(SOURCE) DL_ forced to 2.5V 2.7 A
DL_ Gate-Driver Sink Current IDL(SINK) DL_ forced to 2.5V 8 A
DL_ falling, CDL_ = 3nF 20 DL_ Transition Time
DL rising, CDL_ = 3nF 20
ns
DH_ falling, CDH_ = 3nF 20 DH_ Transition Time DH_ rising, CDH_ = 3nF 20 ns
Internal BST_ Switch
On-Resistance RON(BST) IBST_ = 10mA 10 20
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM3, DRSKP OUTPUTSPWM3, DRSKP Output
High Voltages ISOURCE = 3mA VDD -
0.4V V
PWM3, DRSKP Output
Low Voltages ISINK = 3mA 0.4 V
LOGIC AND I/OLogic-Input High Voltage VIHSHDN, PGD_IN 2.3 V
Logic-Input Low Voltage VIL SHDN, PGD_IN 1.0 V
Low-Voltage Logic-Input
High Voltage VIHLV PSI, D0–D6, DPRSLPVR 0.67 V
Low-Voltage Logic-Input
Low Voltage VILLV PSI, D0–D6, DPRSLPVR 0.33 V
Logic Input Current TA = +25°C;SHDN, DPRSLPVR, PGD_IN,
PSI, D0–D6 = 0 or 5V -1 +1 μA
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= -40oC to +105°C, unless otherwise noted.)(Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLER VCC, VDD 4.5 5.5 Input Voltage Range VIN 7 26 V
DAC codes from
0.8125V to 1.5000V -0.75 +0.75 %
DAC codes from
0.3750V to 0.8000V -10 +10 FB Output-Voltage Accuracy VFB
Measured at
FB with
respect to
GNDS,
includes load-
regulation
error (Note 3)
DAC codes from
0 to 0.3625V -25 +25
mV
Boot Voltage VBOOT 1.085 1.115 V
GNDS Input Range -200 +200 mV
GNDS Gain AGNDS VOUT/VGNDS 0.95 1.05 V/V
TIME Regulation Voltage VTIME RTIME = 147k 1.985 2.015 V
RTIME = 147k (6.08mV/μs nominal) -10 +10
RTIME = 35.7k (25mV/μs nominal) to
178k (5mV/μs nominal) -15 +15
TIME Slew-Rate Accuracy
Soft-start and soft-shutdown:
RTIME = 35.7k (6.25mV/μs nominal) to
178k (1.25mV/μs nominal)
-20 +20
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= -40oC to +105°C, unless otherwise noted.)(Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRTON = 96.75k (600kHz
per phase), 167ns nominal -15 +15
RTON = 200k (300kHz
per phase), 333ns nominal -10 +10 On-Time Accuracy tON
VIN = 10V,
VFB = 1.0V,
measured at
DH1, DH2,
and PWM3
(Note 4) RTON = 303.25k (200kHz
per phase), 500ns nominal -15 +15
Minimum Off-Time tOFF(MIN) Measured at DH1, DH2, and PWM3 (Note 4) 400 ns
BIAS CURRENTSQuiescent Supply Current (VCC) ICC Measured at VCC, DPRSLPVR = 5V, FB
forced above the regulation point 7 mA
FAULT PROTECTIONSkip mode after output reaches the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
250 350 mV
Output Overvoltage-Protection
Threshold VOVP
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
1.45 1.55 V
Output Undervoltage-Protection
Threshold VUVP Measured at FB with respect to the voltage
target set by the VID code (see Table 4) -450 -350 mV
CLKEN Startup Delay and Boot
Time Period tBOOTMeasured from the time when FB reaches
the boot target voltage (Note 3) 20 100 μs
PWRGD Startup Delay Measured at startup from the time when
CLKEN goes low 3 10 ms
Lower threshold,
falling edge
(undervoltage)
-350 -250
CLKEN and PWRGD Threshold
Measured at FB
with respect to the
voltage target set
by the VID code
(see Table 4),
20mV hysteresis
(typ)
Upper threshold,
rising edge
(overvoltage)
+150 +250
mV
CLKEN, PWRGD Output
Low Voltage Low state, ISINK = 3mA 0.4 V
VCC Undervoltage-Lockout
Threshold VUVLO(VCC) Rising edge, 65mV typical hysteresis,
controller disabled below this level 4.05 4.5 V
THERMAL PROTECTIONVRHOT Trip Threshold Measured at THRM with respect to VCC,
falling edge, typical hysteresis = 75mV 29 31 %
VRHOT Output On-Resistance RON(VRHOT)Low state 8
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITORVTIME - VILIM = 100mV 7 13
VTIME - VILIM = 500mV 45 55 Current-Limit Threshold Voltage
(Positive) VLIMITVCSP_ - VCSN_
ILIM = VCC 20 25
mV
Current-Limit Threshold Voltage
(Negative) Accuracy VLIMIT(NEG) VCSP_ - VCSN_, nominally -125% of VLIMIT-4 +4 mV
CSP_, CSN_ Common-Mode
Input Range 0 2 V
Phases 2, 3 Disable Threshold Measured at CSP2, CSP3 3 VCC -
0.4 V
Droop Amplifier Offset
(1/N) x (VCSP_ - VCSN_) at IFBAC = 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1 +1 mV/
phase
Droop Amplifier
Transconductance Gm(FBAC)
IFBAC/[(VCSP_ - VCSN_)]; indicates
summation over all power-up enabled
phases from 1 to N, N = 3,
VFBAC = VCSN_ = 0.45V to 1.5V
390 407 μS
Current-Monitor Offset
(1/N) x (VCSP_ - VCSN_) at IFBAC = 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1.5 +1.5 mV/
phase
Current-Monitor
Transconductance Gm(IMON)
IIMON/[(VCSP_ - VCSN_)]; indicates
summation over all power-up enabled phases
from 1 to N, N = 3, VCSN_ = 0.45V to 1.5V
1.536 1.664 mS
GATE DRIVERSHigh state (pullup) 2.5 DH_ Gate-Driver On-Resistance RON(DH) BST_ – LX_
forced to 5V Low state (pulldown) 2
High state (pullup) 2 DL_ Gate-Driver On-Resistance RON(DL)
Low state (pulldown) 0.7
Internal BST_ Switch
On-Resistance RON(BST) IBST- = 10mA 20
PWM3, DRSKP OUTPUTSPWM3, DRSKP Output
High Voltages ISOURCE = 3mA VDD -
0.4V V
PWM3, DRSKP Output
Low Voltages ISINK = 3mA 0.4 V
LOGIC AND I/OLogic-Input High Voltage VIHSHDN, PGD_IN 2.3 V
Logic-Input Low Voltage VIL SHDN, PGD_IN 1.0 V
Low-Voltage Logic-Input
High Voltage VIHLV PSI, D0–D6, DPRSLPVR 0.67 V
Low-Voltage Logic-Input
Low Voltage VILLV PSI, D0–D6, DPRSLPVR 0.33 V
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, VIN= 10V, VCC= VDD= VSHDN= VPGD_IN= VPSI= VILIM= 5V, VDPRSLPVR= VGNDS= 0, VCSP_= VCSN_=
1.0000V, FB = FBAC, RFBAC= 3.57kΩfrom FBAC to CSN_, [D6–D0] = [0101000]; TA
= -40oC to +105°C, unless otherwise noted.)(Note 5)
Note 3:The equation for the target voltage VTARGETis:
VTARGET= The slew-rate-controlled version of VDAC, where VDAC= 0 for shutdown
VDAC= VBOOTduring IMVP-6.5 startup
VDAC= VVIDotherwise (the VVIDvoltages for all possible VID codes are given in Table 4).
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4:On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times
might be different due to MOSFET switching speeds.
Note 5:Specifications to -40°C and +105°C are guaranteed by design, not production tested.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
EFFICIENCY vs. LOAD CURRENT
(VOUT(HFM) = 0.95V)MAX17030 toc01
LOAD CURRENT (A)
EFFICIENCY (%)1
12V
20V
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(HFM) = 0.95V)MAX17030 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)60203040
EFFICIENCY vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)
MAX17030 toc03
LOAD CURRENT (A)
EFFICIENCY (%)1
12V
20V
SKIP MODE
PWM MODE
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT(LFM) = 0.875V)MAX17030 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)510
2-PHASE PWM MODE
1-PHASE SKIP MODE
SWITCHING FREQUENCY
vs. LOAD CURRENTMAX17030 toc05
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)1020
VOUT(HFM) = 0.95V
VOUT(LFM) = 0.875V
DPRSLPVR = VCC
DPRSLPVR = GND
VOUT(HFM) = 0.95V NO-LOAD
SUPPLY CURRENT vs. INPUT VOLTAGEMAX17030 toc06
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)912
IIN
IIN
ICC + IDD
ICC + IDD
DPRSLPVR = VCC
DPRSLPVR = GND
Typical Operating Characteristics(Circuit of Figure 1. VIN= 12V, VCC= VDD= 5V, SHDN= VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
ELECTRICAL CHARACTERISTICS (continued)
MAX17030/MAX17036
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
Typical Operating Characteristics (continued)(Circuit of Figure 1. VIN= 12V, VCC= VDD= 5V, SHDN= VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
CURRENT BALANCE
vs. LOAD CURRENTMAX17030 toc07
LOAD CURRENT (A)
SENSE VOLTAGE (mV)
SENSE VOLTAGE DIFFERENCE (mV)401020
VOUT = 0.95V
VCSP1 - VCSN1
VCSP2 - VCSN2
VCS3 - VCS1
VCS2 - VCS1
VCSP3 -
VCSN3
IIMON
vs. LOAD CURRENTMAX17030 toc08
∑VCSP - CSN (mV)
IMON (1020
VOUT = 0.95V
DPRSLPVR = GND
0.8125V OUTPUT
VOLTAGE DISTRIBUTIONMAX17030 toc09
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
+85°C
+25°C
SAMPLE SIZE = 100
Gm(FB) TRANSCONDUCTANCE
DISTRIBUTIONMAX17030 toc10
TRANCONDUCTANCE (μs)
SAMPLE PERCENTAGE (%)
+85°C
+25°C
SAMPLE SIZE = 100
Gm(IMON) TRANSCONDUCTANCE
DISTRIBUTIONMAX17030 toc11
TRANCONDUCTANCE (μs)
SAMPLE PERCENTAGE (%)
+85°C
+25°C
SAMPLE SIZE = 100
MAX17030/MAX17036
1/2/3-Phase-Quick-PWM
IMVP-6.5 VID Controllers
SOFT-START WAVEFORM
(UP TO CLKEN)MAX17030 toc12
200µs/div
A. SHDN, 5V/div
B. CLKEN, 10V/div
C. VOUT, 500mV/div
3.3V
0.95V
3.3V
D. ILX1, 10A/div
E. ILX2, 10A/div
F. ILX3, 10A/div
IOUT, 15A
SOFT-START WAVEFORM
(UP TO PWRGD)MAX17030 toc13
1ms/div
A. SHDN, 5V/div
B. CLKEN, 6.6V/div
C. PWRGD, 10V/div
D. VOUT, 1V/div
3.3V
0.95V
3.3V
3.3V
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
IOUT, 15A
SHUTDOWN WAVEFORMMAX17030 toc14
200µs/div
A. SHDN, 5V/div
B. PWRGD, 10V/div
C. CLKEN, 10V/div
D. VOUT, 500mV/div
3.3V
0.95V
3.3V
3.3V
E. DL1, 10V/div
F. DL2, 10V/div
G. DL3, 10V/div
LOAD-TRANSIENT RESPONSE
(HFM MODE)MAX17030 toc15
20μs/div
A. IOUT = 7A - 59A
B. VOUT, 50mV/div59A
0.84V
0.935V
C. ILX1, 20A/div
D. ILX2, 20A/div
E. ILX3, 20A/div
Typical Operating Characteristics (continued)(Circuit of Figure 1. VIN= 12V, VCC= VDD= 5V, SHDN= VCC, D0–D6 set for 0.95V, TA= +25°C, unless otherwise specified.)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description
PINNAMEFUNCTIONCSN3
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing. CSP3
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
To disable phase 3, connect CSP3 to VCC and CSN3 to GND.
3 THRM
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC
and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of
VCC) at the desired high temperature.
4 IMON
Current Monitor Output Pin. The output current at this pin is:
IIMON = GM(IMON) x V(CSP_,CSN_)
where GM(IMON) = 1.6mS typical and denotes summation over all enabled phases.
An external resistor RIMON between IMON and GNDS sets the current-monitor output voltage:
VIMON = ILOAD x RSENSE x GM(IMON) x RIMON
where RSENSE is the value of the effective current-sense resistance.
Choose RIMON such that VIMON does not exceed 900mV at the maximum expected load current IMAX.
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
5 ILIM
Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are
precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
current-limit thresholds. Connect ILIM to VCC to get the default current-limit threshold setting of
22.5mV typ.
6 TIME
Slew-Rate Adjustment Pin. The total resistance RTIME from TIME to GND sets the internal slew rate:
Slew rate = (12.5mV/μs) x (71.5k/RTIME)
where RTIME is between 35.7k and 178k.
This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
7 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1μF minimum.
8 FB
Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
of the inductor currents is essential for cycle-by-cycle stability.
The external connections and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PINNAMEFUNCTION9 FBAC
Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor RFBAC between
FBAC and the positive side of the feedback remote sense to set the transient (AC) droop based on
the stability, load-transient response, and voltage-positioning gain requirements:
RFBAC = RDROOP,AC/[RSENSE x Gm(FBAC)]
where RDROOP,AC is the transient (AC) voltage-positioning slope that provides an acceptable
tradeoff between stability and load-transient response, Gm(FBAC) = 400μS typ, and RSENSE is the
effective current-sense resistance that is used to provide the (CSP_, CSN_) current-sense voltages.
A minimum RDROOP,AC value is required for stability, but if there are no ceramic output capacitors
used, then the minimum requirement applies to RESR + RDROOP,AC, where RESR is the effective
ESR of the output capacitors.
If lossless sensing (inductor DCR sensing) is used, usea thermistor-resistor network to minimize
the temperature dependence of the voltage-positioning slope.
FBAC is high impedance in shutdown.
10 GNDS
Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load.
GNDS internally connects to a transconductance amplifier that fine tunes the output voltage
compensating for voltage drops from the regulator ground to the load ground.
11 CSN2
Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
12 CSP2
Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
inductor is utilized for current sensing.
To disable phase 2, connect CSP2 to VCC and CSN2 to GND. SHDN
Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the IC into
the 1μA (max at TA = +25°C) shutdown state. During startup, the output voltage is ramped up at 1/4
the slew rate set by the TIME resistor to the boot voltage or to the target voltage.
During the transition from normal operation to shutdown, the output voltage is ramped down at 1/4
the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V to enter no-fault test mode clears
the fault latches, disables transient phase overlap, and turns off the internal BST_-to-VDD switches.
However, internal diodes still exist between BST_ and VDD in this state.
Deeper Sleep VR Control Input. This low-voltage logic input indicates power usage and sets the
operating mode together with PSI as shown in the truth table below. When DPRSLPVR is forced high, the
controller is immediately set to 1-phase automatic pulse-skipping mode. The controller returns to forced-
PWM mode when DPRSLPVR is forced low and the output is in regulation. The PWRGD upper threshold
is blanked during any downward output-voltage transition that happens when the controller is in skip
mode, and stays blanked until the slew-rate-controlled internal-transition-related PWRGD blanking period
is complete and the output reaches regulation. During this blanking period, the overvoltage fault
threshold is changed from a tracking [VID + 300mV] threshold to a fixed 1.5V threshold.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase
forced-PWM mode during the transition from boot mode to VID mode, during soft-shutdown,
irrespective of the DPRSLPVR and PSI logic levels. However, if phases 2 and 3 are disabled by
connecting CSP2, CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVRPSI
MODE14 DPRSLPVR
Very low current (1-phase skip)
Intermediate power potential (N-1-phase PWM)
Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)PIN NAME FUNCTIONThis low-voltage logic input indicates power usage and sets the operating mode togetherwith DPRSLPVR as shown in the truth table below. While DPRSLPVR is low, if P SI is forced low, the
controller is immediately set to (N-1)-phase forced-PWM mode. The controller returns to N-phase
forced-PWM mode when P SI is forced high.
The controller is in N-phase skip mode during startup including boot mode, but is in N-phase forced-
PWM mode during the transition from boot mode to VID mode, during soft-shutdown, irrespective of
the DPRSLPVR and P SI logic levels. However, if phases 2 and 3 are disabled by connecting CSP2,
CSP3 to VCC, then only phase 1 is active in the above modes.
DPRSLPVR PSI
MODE15 PSI1 0 0X 0 1Very low current (1-phase skip) Intermediate power potential (N-1-phase PWM) Max power potential (full-phase PWM: N-phase or 1 phase as set by user
at CSP2, CSP3)16TON
Switching Frequency Setting Input. An external resistor between the input power source and this pin
sets the switching frequency according to the following equation:
fSW = 1/(CTON x (RTON + 6.5kΩ))
where CTON = 16.26pF.
The external resistor must also satisfy the requirement [VIN(MIN)/RTON] ≥ 10μA where VIN(MIN) is the
minimum VIN value expected in the application.
TON is high impedance in shutdown.17 CLKENC l ock E nab l e Op en- D r ai n Log i c O utp ut P ow er ed b y V 3 P 3 . Thi s i nver ted l og i c outp ut i nd i cates w hen the
outp ut vol tag e sensed at FB i s i n r eg ul ati on. C LKEN i s for ced hi g h i n shutd ow n and d ur i ng soft- star t and
soft- stop tr ansi ti ons. C LKEN i s for ced l ow d ur i ng d ynam i c V ID tr ansi ti ons and for an ad d i ti onal 20μs after
the tr ansi ti on i s com p l eted . C LKEN i s the i nver se of P WRGD , excep t for the 5m s P WRG D star tup d el ayer i od after C LKEN i s p ul l ed l ow . S ee the star tup ti m i ng d i ag r am ( Fi g ur e 9) . The C LKEN up p er thr eshol d s b l anked d ur i ng any d ow nw ar d outp ut- vol tag e tr ansi ti on that hap p ens w hen the contr ol l er i s i n ski p od e, and stays b l anked unti l the sl ew - r ate- contr ol l ed i nter nal - tr ansi ti on- r el ated P W RG D b l anki ng p er i od s com p l ete and the outp ut r eaches r eg ul ati on.18 PWRGDOpen-Drain Power-Good Output. After output-voltage transitions, except during power-up and power-
down, if FB is in regulation, then PWRGD is high impedance.
PWRGD is low during startup, continues to be low while the output is at the boot voltage, and stays
low until 5ms (typ) after CLKEN goes low, after which it starts monitoring the FB voltage and goes
high if FB is within the PWRGD threshold window.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance
whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced
high impedance for an additional 20μs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that happens
when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-
related PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.19 DRSKPDriver Skip Control Output. Push/pull logic output that controls the operating mode of the skip-mode
driver IC. DRSKP swings from VDD to GND. When DRSKP is high, the driver ICs operate in forced-
PWM mode. When DRSKP is low, the driver ICs enable their zero-crossing comparators and operate
in pulse-skipping mode. DRSKP goes low at the end of the soft-shutdown sequence, instructing the
external drivers to shut down.
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PINNAMEFUNCTION20 PWM3 PWM Signal Output for Phase 3. Swings from GND to VDD. Three-state whenever phase 3 is disabled
(in shutdown, when CSP3 is connected to VCC, and when operating with fewer than all phases). BST2
Phase 2 Boost Flying Capacitor Connection. BST2 is the internal upper supply rail for the DH2 high-
side gate driver. An internal switch between VDD and BST2 charges the BST2-LX2 flying capacitor
while the low-side MOSFET is on (DL2 pulled high). LX2 Phase 2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
Also used as an input to phase 2’s zero-crossing comparator. DH2 Phase 2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown. DL2
Phase 2 Low-Side Gate-Driver Output. DL2 swings from GND to VDD. DL2 is forced low in shutdown.
DL2 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL2 is forced low in skip mode after detecting an inductor
current zero crossing. VRHOTOpen-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes
below 1.5V (30% of VCC). VRHOT is high impedance in shutdown. VDD
Supply Voltage Input for the DL_ Drivers. VDD is also the supply voltage used to internally recharge
the BST_-LX_ flying capacitor during the times the respective DL_s are high. Connect VDD to the
4.5V to 5.5V system supply voltage. Bypass VDD to GND with a 1μF or greater ceramic capacitor. DL1
Phase 1 Low-Side Gate-Driver Output. DL1 swings from GND to VDD. DL1 is forced low in shutdown.
DL1 is forced high when an output overvoltage fault is detected, overriding any negative current-
limit condition that might be present. DL1 is forced low in skip mode after detecting an inductor
current zero crossing. DH1 Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown. LX1 Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
Also used as an input to phase 1’s zero-crossing comparator. BST1
Phase 1 Boost Flying Capacitor Connection. BST1 is the internal upper supply rail for the DH1 high-
side gate driver. An internal switch between VDD and BST1 charges the BST1-LX1 flying capacitor
while the low-side MOSFET is on (DL1 pulled high). PGD_IN
Power-Good Logic Input Pin that Indicates the Power Status of Other System Rails and Used for Supply
Sequencing. During startup, after soft-starting to the boot voltage, the output voltage remains at VBOOT,
and the CLKEN and PWRGD outputs remain high and low, respectively, as long as the PGD_IN input
stays low. When PGD_IN later goes high, the output is allowed to transition to the voltage set by the VID
code, and CLKEN is allowed to go low. During normal operation, if PGD_IN goes low, the controller
immediately forces CLKEN high and PWRGD low, and slews the output to the boot voltage while in skip
mode at 1/4 the normal slew rate set by the TIME resistor. The output then stays at the boot voltage until
the controller is turned off or power cycled, or until PGD_IN goes high again.
32–38 D0–D6
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups. These
1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID
code indicated by the logic-level voltages on D0–D6 (see Table 4).
The 1111111 code corresponds to a shutdown mode. When this code is detected, The
MAX17030/MAX17036 initiate a soft-shutdown transition identical to the shutdown transition for a
SHDN falling edge. After slewing the output to 0V, it forces DH_, DL_, and DRSKP low, and three-states
PWM3. The IC remains active and its VCC quiescent current consumption stays the same as in normal
operation. If D6–D0 is changed from 1111111 to a different code, the MAX17030/MAX17036 initiate a
startup sequence identical to the startup sequence for a SHDN rising edge. CSP1
Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Pin Description (continued)
PINNAMEFUNCTIONCSN1
Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing. A 10 discharge FET is turned on in UVLO event
or thermal shutdown, or at the end of soft-shutdown.PAD (GND) Exposed Backplate (Pad) of Package. Internally connected to both analog ground and power
(driver) grounds. Connect to the ground plane through a thermally enhanced via.
MAX8791
CBST2ΩRNTC1
RILIM1RILIM2
RTON200kΩ
TON
BST1CIN
SHDN
DPRSLPVR
PGDIN
PSI
DPRSLPVR
PGDIN
PSI
VDD5V BIAS
VCC16
8V TO 20V
PWR INPUT
OUTPUT
(IMVP-6.5 CORE)
ON OFF (VRON)
PWRGD
VCC
VCCP
VSS_SENSE
VID INPUTS
DH1
LX1DL1
RCATCHGND
10Ω
CSN1
CCS1
CSP1
COUT
ILIM
TIME
RTHRM
13kΩ
THRM
RPWRGD
1.9kΩ
RCLKEN
1.9kΩRVRHOT
56Ω
VRHOT
CLKEN
RFBRFBS
10ΩRCATCHCORE
10Ω
RGNDS
10Ω
IMONIMON
NTC
100kΩβ = 4250
PAD
RIMON
FBAC
GNDS
CFBS
1000pF
CGNDS
4700pF
CPU REMOTE
SENSE
3.3V
RVCC
20Ω
CVDD
2.2μF
CVCC
1.0μF
CBSTRNTC2
BST2CIN
8V TO 20V
PWR INPUT
DH2
LX2DL2
CSN2
CCS2
CSP2
COUT
CBSTRNTC3
BSTCIN
8V TO 20V
PWR INPUT5V BIASDL
CSN3
CCS3
CSP3
COUT
GND
VCC
CVCC1
1.0μF
PWM3
DRSKP
PWM
SKIP
MAX17030
MAX17036
VSS_SENSE
VCC_SENSE
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
DESIGN PARAMETERSIMVP-6.5 XE CORE
3-PHASE
IMVP-6.5 SV CORE
3-PHASE
IMVP-6.5 SV CORE
2-PHASE Circuit Figure 1 Figure 1 Figure 2
Input Voltage Range 8V to 20V 8V to 20V 8V to 20V
Maximum Load Current 65A (48A TDC) 52A (38A TDC) 52A (38A TDC)
Transient Load Current 49A
(100A/μs)
39A
(100A/μs)
39A
(100A/μs)
Load Line -1.9mV/A -1.9mV/A -1.9mV/A
POC Setting 110 101 101
TON Resistance (RTON) 200k (fSW = 300kHz) 200k (fSW = 300kHz) 200k (fSW = 300kHz)
Inductance (L)
0.36μH, 36A, 0.82m
(10mm x 10mm)
Panasonic ETQP4LR36ZFC
0.42μH, 20A, 1.55m
(7mm x 7mm)
NEC/TOKIN MPC0740LR42C
0.36μH, 36A, 0.82m
(10mm x 10mm)
Panasonic ETQP4LR36ZFC
High-Side MOSFET (NH)
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max)
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max
Fairchildsemi
1x FDS6298
9.4m/12m (typ/max)
Toshiba
1x TPCA8030-H
9.6m/13.4m (typ/max)
Low-Side MOSFET (NL)
Fairchildsemi
2x FDS8670
4.2m/5m (typ/max)
Toshiba
2x TPCA8019-H
Fairchildsemi
1x FDS8670
4.2m/5m (typ/max)
Toshiba
1x TPCA8019-H
Fairchildsemi
2x FDS8670
4.2m/5m (typ/max)
Toshiba
2x TPCA8019-H
Output Capacitors (COUT)
(MAX17030 Only)
Contact Maxim for MAX17036
reference design4x 330μF, 2V, 4.5m
Panasonic EEFSXOD331E4 or
NEC/Tokin PSGVOE337M4.5
27x 22μF, 6.3V X5R
ceramic capacitor (0805)
3x 330μF, 2V, 4.5m
Panasonic EEFSXOD331E4 or
NEC/Tokin PSGVOE337M4.5
27x 22μF, 6.3V X5R
ceramic capacitor (0805)
4x 330μF, 6m, 2.5V
Panasonic EEFSX0D0D331XR
28x 10μF, 6V ceramic (0805)
Input Capacitors (CIN) 6x 10μF 25V ceramic (1210) 4x 10μF 25V ceramic (1210) 4x 10μF 25V ceramic (1210)
TIME-ILIM Resistance (RILIM2) 14k 14k 16.9k
ILIM-GND Resistance (RILIM1) 137k 137k 133k
FB Resistance (RFB) 6.04k 453k 6.04k
IMON Resistance (RIMON) 12.1k 10.2k 14k
LX-CSP Resistance 2.21k (R1, R4, R7) 1.4k (R1, R4, R7) 2.21k (R1, R7)
CSP-CSN Resistance 3.24k (R2, R5, R8)
40.2k (R3, R6, R9)
2k (R2, R5, R8)
40.2k (R3, R6, R9)
3.24k (R2, R8)
40.2k (R3, R9)
DCR Sense NTC (RNTC)10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
DCR Sense Capacitance
(CSENSE)0.22μF, 6V ceramic (0805) 0.22μF, 6V ceramic (0805) 0.22μF, 6V ceramic (0805)
Table 1. Component Selection for Standard Applications
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
MANUFACTURERWEBSITEAVX Corp. www.avxcorp.com
Fairchild Semiconductor www.fairchildsemi.com
NEC/TOKIN America, Inc. www.nec-tokinamerica.com
Panasonic Corp. www.panasonic.com
SANYO Electric Co., Ltd. www.sanyodevice.com
MANUFACTURERWEBSITESiliconix (Vishay) www.vishay.com
Taiyo Yuden www.t-yuden.com
TDK Corp. www.component.tdk.com
TOKO America, Inc. www.tokoam.com
Toshiba America Electronic
Components, Inc. www.toshiba.com/taec
Table 2. Component SuppliersMAX17030
MAX17036
CBSTRNTC1
RILIM1RILIM2
RTON
200kΩ
TON
BST1CIN
SHDN
DPRSLPVR
PGDIN
PSI
DPRSLPVR
PGDIN
PSI
VDD5V BIAS
VCC
8V TO 20V
PWR INPUT
OUTPUT
(IMVP-6.5 CORE)
ON OFF (VRON)
PWRGD
VCC
VCCP
VID INPUTSDH1
LX1DL1
RCATCHGND
10Ω
CSN1
CCS1
CSP1
COUT
ILIM
TIME
RTHRM
13kΩ
THRM
RPWRGD
1.9kΩ
RCLKEN
1.9kΩRVRHOT
56Ω
VRHOT
CLKEN
RFB
RFBS
10Ω
RCATCHCORE
10Ω
RGNDS
10Ω
IMONIMON
VSS_SENSE
NTC
100kΩ
β = 4250
PAD
RIMON
FBAC
GNDS
CFBS
1000pFCPU REMOTE
SENSE
3.3V
RVCC
20Ω
CVDD
2.2µF
CVCC
1.0µFCBSTRNTC3
BST2CIN
8V TO 20V
PWR INPUT
5V BIAS
DH2
LX2DL2
CSN2
CCS2
CSP2
COUT
CSN3
CSP3
PWM3
DRSKP
VCC_SENSE
VSS_SENSE
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID ControllersTHRM
0.3 x VCC
VRHOT
CSN3
CSP3
10x
CSN2
CSP2
10x
CSN1
ILIM
TIME
VCC
CSP1
10x
REF
(2.0V)
GND
D0–D6DACR-TO-I
CONVERTER
FAULT
SHDN
PGDIN
TARGET
SEL
PHASE
GNDS
FBAC
CSN
CSP
Gm(FB)MAX17030
MAX17036
PWM3
DRSKP
ONE-SHOT
PHASE 3
ON-TIMETRIG3
TON
CC13
CCI2
TRIG
PHASE 3 DRIVER
CONTROL
CSP1
CSN1Gm(CCI3)
CSN3
CSP3Gm(CCI)
CSP1
CSN1Gm(CCI)
CSN2
CSP2Gm(CCI)
BST2
DH2
LX2
DL2
GND
ONE-SHOT
PHASE 2
ON-TIMETRIG
PHASE 2 DRIVERS
SLEW
MINIMUM
OFF-TIME
ONE SHOTTRIG TRIG 3
PGND1
PHASE 1
ON-TIME
ONE-SHOT
LX1
0mVTRIG
SKIP
DL1
PWRGD
GND
VDD
BST1
TON
MAIN PHASE
DRIVERS
DH1
LX1
SKIP
BLANK
TARGET
+ 200mV
TARGET
- 300mV
PGDINDPRSLPVRPSI
CLKEN
IMON
60μs
MODE/PHASE/SLEW-
RATE CONTROL
5ms
STARTUP
DELAY
CSP
CSNGm(IMON)
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
Detailed Description
Free-Running, Constant-On-Time PWM
Controller with Input Feed-ForwardThe Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator with
voltage feed-forward (Figure 3). This architecture relies on
the output filter capacitor’s ESR to act as the current-
sense resistor, so the output ripple voltage provides the
PWM ramp signal. The control algorithm is simple: the
high-side switch on-time is determined solely by a one-
shot whose period is inversely proportional to input volt-
age, and directly proportional to output voltage or the
difference between the main and secondary inductor cur-
rents (see the On-Time One-Shot section). Another one-
shot sets a minimum off-time. The on-time one-shot
triggers when the error comparator goes low, the inductor
current of the selected phase is below the valley current-
limit threshold, and the minimum off-time one-shot times
out. The controller maintains 120°out-of-phase operation
by alternately triggering the three phases after the error
comparator drops below the output-voltage set point.
Triple 120°Out-of-Phase OperationThe three phases in the MAX17030/MAX17036 operate
120°out-of-phase to minimize input and output filtering
requirements, reduce electromagnetic interference (EMI),
and improve efficiency. This effectively lowers component
count—reducing cost, board space, and component
power requirements—making the MAX17030/MAX17036
ideal for high-power, cost-sensitive applications.
The MAX17030/MAX17036 share the current between
three phases that operate 120°out-of-phase, so the
high-side MOSFETs never turn on simultaneously dur-
ing normal operation. The instantaneous input current
of each phase is effectively reduced, resulting in
reduced input voltage ripple, ESR power loss, and RMS
ripple current (see the Input Capacitor Selectionsec-
tion). Therefore, the same performance can be
achieved with fewer or less-expensive input capacitors.
+5V Bias Supply (VCCand VDD)The Quick-PWM controller requires an external +5V
bias supply in addition to the battery. Typically, this
+5V bias supply is the notebook’s 95% efficient +5V
system supply. The +5V bias supply must provide VCC
(PWM controller) and VDD(gate-drive power), so the
maximum current drawn is:
where ICCis provided in the Electrical Characteristics
table, fSWis the switching frequency, and QG(LOW)and
QG(HIGH)are the MOSFET data sheet’s total gate-
VINand VDDcan be connected together if the input
power source is a fixed +4.5V to +5.5V supply. If the
+5V bias supply is powered up prior to the battery sup-
ply, the enable signal (SHDNgoing from low to high)
must be delayed until the battery voltage is present to
ensure startup.
Switching Frequency (TON)Connect a resistor (RTON) between TON and VINto set
the switching period TSW= 1/fSW, per phase:
TSW= 16.26pF x (RTON+ 6.5kΩ)
A 96.75kΩto 303.25kΩcorresponds to switching peri-
ods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the appli-
cation for the smallest component size, trading off effi-
ciency due to higher switching losses. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
TON Open-Circuit ProtectionThe TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an over-
voltage condition on the output. The MAX17030/
MAX17036 detect an open-circuit fault if the TON current
drops below 10μA for any reason—the TON resistor
(RTON) is unpopulated, a high resistance value is used,
the input voltage is low, etc. Under these conditions, the
MAX17030/MAX17036 stop switching (DH and DL pulled
low) and immediately set the fault latch. Toggle SHDNor
cycle the VCCpower supply below 0.5V to clear the fault
latch and reactivate the controller.
On-Time One-ShotThe MAX17030/MAX17036 contain a fast, low-jitter,
adjustable one-shot that sets the high-side MOSFETs
on-time. It is shared among the three phases. The one-
shot for the main phase varies the on-time in response
to the input and feedback voltages. The main high-side
switch on-time is inversely proportional to the input volt-
age as measured by the V+ input, and proportional to
the feedback voltage (VFB):
The one-shot for the second phase and third phase
varies the on-time in response to the input voltage and
the difference between the main and the other inductor
currents. Two identical transconductance amplifiers
integrate the difference between the master and each
slave’s current-sense signals. The summed output is
connected to an internal integrator for each master-
slave pair, which serves as the input to the respectiveTVVONSWFB=+()0075.fQQBIASCCSWGLOWGHIGH=++()()()
