MAX17009GTL+ ,AMD Mobile Serial VID Dual-Phase Fixed-Frequency ControllerApplications ♦ Power Sequencing and TimingMobile AMD SVI Core Supply♦ Soft-Startup and Soft-Shutdow ..
MAX17009GTL+T ,AMD Mobile Serial VID Dual-Phase Fixed-Frequency ControllerFeaturesThe MAX17009 is a 2-phase, step-down interleaved, ♦ Dual-Output, Fixed-Frequency, Core Supp ..
MAX1700EEE ,1-Cell to 3-Cell / High-Power 1A / Low-Noise / Step-Up DC-DC ConvertersMAX1700/MAX170119-4759; Rev 1; 1/991-Cell to 3-Cell, High-Power (1A), Low-Noise, Step-Up DC-DC Conv ..
MAX1700EEE ,1-Cell to 3-Cell / High-Power 1A / Low-Noise / Step-Up DC-DC Convertersapplications. They use a synchro-nous-rectified pulse-width-modulation (PWM) boost' 0.7V to 5.5V In ..
MAX1700EEE+ ,1 Cell to 3 Cell, High-Power 1A, Low-Noise, Step-Up DC-DC ConvertersELECTRICAL CHARACTERISTICS(CLK/SEL = ONA = ONB = FB = PGND = GND, OUT = POUT, V = 3.6V (Note 6); MA ..
MAX17010AETL+ ,Internal-Switch Boost Regulator with Integrated High-Voltage Level Shifter and Op AmpApplicationsNotebook Computer DisplaysPGNDLCD Monitor PanelsCOMP SUPOrdering InformationAGNDPOSVLPA ..
MAX4514ESA+ ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesMAX4514/MAX451519-1069; Rev 1; 5/05Low-Voltage, Low-On-Resistance,SPST, CMOS Analog Switches_______ ..
MAX4514ESA+T ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesELECTRICAL CHARACTERISTICS—+5V Supply(V+ = +4.5V to +5.5V, V = 2.4V, V = 0.8V, T = T to T , unless ..
MAX4514EUK+T ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesELECTRICAL CHARACTERISTICS—+5V Supply(V+ = +4.5V to +5.5V, V = 2.4V, V = 0.8V, T = T to T , unless ..
MAX4514EUK-T ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesFeaturesThe MAX4514/MAX4515 are single-pole/single-throw ♦ Available in SOT23-5 Package(SPST), CMOS ..
MAX4514EUK-T ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesMAX4514/MAX451519-1069; Rev 1; 5/05Low-Voltage, Low-On-Resistance,SPST, CMOS Analog Switches_______ ..
MAX4515CPA ,Low-Voltage, Low-On-Resistance, SPST, CMOS Analog SwitchesELECTRICAL CHARACTERISTICS—+5V Supply(V+ = +4.5V to +5.5V, V = 2.4V, V = 0.8V, T = T to T , unless ..
MAX17009GTL+-MAX17009GTL+T
AMD Mobile Serial VID Dual-Phase Fixed-Frequency Controller
General DescriptionThe MAX17009 is a 2-phase, step-down interleaved,
fixed-frequency controller for AMD’s®serial VID inter-
face (SVI) CPU core supplies. Power-on detection of
the CPU configures the MAX17009 as two independent
single-phase regulators for a dual CPU core applica-
tion, or one high-current, dual-phase, combined-output
regulator for a unified core application. A reference
buffer output (NBV_BUF) sets the voltage-regulation
level for a North Bridge (NB) regulator, completing the
total CPU cores and NB power requirements.
The MAX17009 is fully AMD SVI compliant. Output volt-
ages are dynamically changed through a 2-wire serial
interface, allowing the switching regulator and the refe-
rence buffer to be individually programmed to different
voltages. A programmable slew-rate controller enables
controlled transitions between VID codes, soft-start limits
the inrush current, and soft-shutdown brings the output
voltage back down to zero without any negative ring.
Transient phase repeat improves the response of the
fixed-frequency architecture. Independently program-
mable AC and DC droop and selectable offset improve
stability and reduce the total output-capacitance
requirement. A thermistor-based temperature sensor
allows for a programmable thermal-fault output
(VRHOT). The MAX17009 includes thermal-fault protec-
tion, undervoltage protection (UVP), and selectable out-
put overvoltage protection (OVP). When any of these
protection features detect a fault, the controller shuts
down. True differential current sensing improves cur-
rent limit, load-line accuracy, and current balance when
operating in combined mode. The MAX17009 has an
adjustable switching frequency, allowing 100kHz to
1.2MHz per-phase operation.
ApplicationsMobile AMD SVI Core Supply
Multiphase CPU Core Supply
Voltage-Positioned, Step-Down Converters
Notebook/Desktop Computers
FeaturesDual-Output, Fixed-Frequency, Core Supply
ControllerSeparate or Combinable Outputs Detected at
Power-UpReference Buffer Output for NB Controller±0.4% VOUTAccuracy Over Line, Load, and
TemperatureAMD SVI-Compliant Serial Interface7-Bit On-Board DAC: 0 to +1.550V Output Adjust
RangeDynamic Phase Selection Optimizes Active/Sleep
EfficiencyTransient Phase Repeat Reduces Output
CapacitanceTrue Out-of-Phase Operation Reduces Input
CapacitanceIntegrated Boost SwitchesProgrammable AC and DC DroopProgrammable 100kHz to 1.2MHz Switching
FrequencyAccurate Current Balance and Current LimitAdjustable Slew-Rate ControlPower-Good (PWRGD) and Thermal-Fault
(VRHOT) OutputsSystem Power-OK (PGD_IN) InputDrives Large Synchronous-Rectifier MOSFETs4V to 26V Battery Input-Voltage RangeOvervoltage, Undervoltage, and Thermal-Fault
ProtectionPower Sequencing and TimingSoft-Startup and Soft-Shutdown< 1µA Typical Shutdown Current
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Ordering Information19-0814; Rev 0; 5/07
+Denotes a lead-free package.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX17009GTL+-40°C to +105°C40 TQFN-EP*,
5mm x 5mmT4055-1
Pin Configuration appears at end of data sheet.AMD is a registered trademark of Advanced Micro Devices, Inc.
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD1,VDD2,VCC, VDDIOto GND_............................-0.3V to +6V
PWRGD to GND_......................................................-0.3V to +6V
FBDC_, FBAC_, PROto GND_...................-0.3V to (VCC + 0.3V)
GNDS2, THRM, VRHOTto GND_.............................-0.3V to +6V
CSP_, CSN_, ILIM to GND_......................................-0.3V to +6V
SVC, SVD, PGD_IN to GND_....................................-0.3V to +6V
NBV_BUF, NBSKPto GND_.......................-0.3V to (VCC + 0.3V)
REF, OSC, TIME, OPTION to GND_ ..........-0.3V to (VCC + 0.3V)
BST1, BST2 to GND_..............................................-0.3V to +36V
BST1 to VDD1..........................................................-0.3V to +30V
BST2 to VDD2..........................................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 .............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 .............................................-0.3V to (VBST2 + 0.3V)
DL1 to GND_.............................................-0.3V to (VDD1 + 0.3V)
DL2 to GND_.............................................-0.3V to (VDD2 + 0.3V)
GNDS1, GNDS_NB to GND_.................................-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
Multilayer PCB(derate 35.7mW/°C above +70°C).....2857mW
Single-Layer PCB(derate 22.2mW/°C above +70°C)..1778mW
Operating Temperature Range.........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INPUT SUPPLIESVINDrain of external high-side MOSFET426
VBIASVCC, VDD1, VDD24.55.5Input Voltage Range
VDDIO1.02.7
VCC Undervoltage-Lockout
ThresholdVUVLOVCC rising 50mV typical hysteresis4.104.254.45V
VCC Power-On Reset
ThresholdVCC
Falling edge, typical hysteresis = 1.1V,
faults cleared and DL_ forced high when
VCC falls below this level
1.8V
VDDIO Undervoltage-Lockout
ThresholdVDDIO rising 100mV typical hysteresis0.70.80.9V
Quiescent Supply Current (VCC)ICCSkip mode, FBDC_ forced above their
regulation points510mA
Quiescent Supply Currents
(VDD1, VDD2)IDD1, IDD2Skip mode, FBDC_ forced above their
regulation points0.011µAui escent S up p l y C ur r ent ( V D D I O) IDDIO1025µA
Shutdown Supply Current (VCC)SHDN = GND0.011µA
Shutdown Supply Currents
(VDD1, VDD2)SHDN = GND0.011µA
Shutdown Supply Current (VDDIO)SHDN = GND0.011µA
Reference VoltageVREFVCC = 4.5V to 5.5V, no REF load1.9862.0002.014V
Sourcing: IREF = 0 to 500µA-2-0.2Reference Load RegulationSinking: IREF = 0 to -100µA0.216.2mV
REF Fault Lockout VoltageTypical hysteresis = 85mV1.84V
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
MAIN SMPS CONTROLLERSDAC codes from 0.8375V to 1.5500V-0.4+0.4%
DAC codes from 0.5000V to 0.8250V-4+4DC Output-Voltage Accuracy
(Note 1)VOUT
DAC codes below 0.4875V-10+10mV
DC Load RegulationEither SMPS, PWM mode, droop disabled,
zero to full load-0.1%
Line-Regulation ErrorEither SMPS, 4V < VIN < 26V0.03%/V
GNDS_ Input RangeVGNDS_Separate mode-200+200mV
GNDS_ GainAGNDS_
Separate: ΔVOUT_/ΔVGNDS_,
-200mV ≤ VGNDS_ ≤ +200mV;
combined: ΔVOUT/ΔVGNDS1,
-200mV ≤ VGNDS1 ≤ +200mV
0.951.001.05V/V
GNDS_ Input Bias CurrentIGNDS_-2+2µA
Combined-Mode Detection
Threshold
GNDS2, detection after REFOK, latched,
cleared by cycling SHDN0.70.80.9V
FBDC_ Input Bias CurrentIFBDC0_CSP_ = CSN_-3+3µA
ROSC = 143kΩ (fOSC = 300kHz nominal)-5+5
Switching-Frequency AccuracyfOSCROSC = 35.7kΩ (fOSC = 1.2MHz nominal) to
432kΩ (fOSC = 99kHz nominal)-7.5+7.5%
Maximum Duty FactorDMAX9092%
Minimum On-TimetONMIN175ns%SMPS1-to-SMPS2 Phase ShiftSMPS2 starts after SMPS1180D eg r ees
RTIME = 143kΩ, SR = 6.25mV/µs-10+10
During
transitionRTIME = 35.7kΩ to 357kΩ,
SR = 25mV/µs to 2.5mV/µs-15+15%TIME Slew-Rate Accuracy
Startup and shutdown1mV/µS
CURRENT LIMITCurrent-Limit Threshold ToleranceVLIMITVCSP_ - VCSN_ = 0.05 x (VREF - VILIM),
(VREF - VILM) = 0.2V to 1.0V-3+3mV
Zero-Crossing ThresholdVZXVGND_ - VLX_, SKIP mode3mV
Idle Mode™ Threshold ToleranceVIDLEVCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT-1.5+1.5mV
CS_ Input-Leakage CurrentCSP_ and CSN_-0.2+0.2µA
CS_ Common-Mode Input RangeCSP_ and CSN_02V
Phase-Disable ThresholdCSP23VCC
- 1
VCC
-0.4V
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DROOP AND CURRENT BALANCEDC Droop Amplifier
Transconductance
Gm(FBDC_)ΔIFBDC_/(ΔVCS_),
VFBDC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = -60mV to +60mV
0.971.001.03mS
DC Droop and Current-Balance
Amplifier OffsetIFBDC_/Gm(FBDC_)-1.5+1.5mV
AC Droop and Current-Balance
Amplifier TransconductanceGm(FBAC_)
ΔIFBAC_/(ΔVCS_),
VFBAC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = -60mV to +60mV
0.971.001.03mS
AC Droop and Current-Balance
Amplifier OffsetIFBAC_/Gm(FBAC_)-1.5+1.5mV
No-Load Positive Offset with
Offset EnabledOffset enabled, OPTION = REF or GND12.5mV
Transient Detection Threshold
Measured at FBDC_ with respect to steady-
state FBDC_ regulation voltage, 5mV
hysteresis (typ), transient phase-repeat
enabled, OPTION = OPEN or GND
-32-18mV
NB BUFFERDAC codes from 0.8375V to 1.5500V-0.4+0.4%
DAC codes from 0.5000V to 0.8250V-4+4NBV_BUF Output Voltage
AccuracyVNBV_BUF
DAC codes below 0.4875V to 0.0125V-10+10mV
RTIME = 143kΩ,
INBV_BUF = 7.0µA-10+10NBV_BUF Short-Circuit Current
(Sets Slew Rate Together with
External Capacitor CNBV_BUF)
DAC code set to
1.2V, VNBV_BUF
= 0.4V and 2VRTIM E = 35.7kΩ to 357kΩ ,
IN BV _BU F = 28µA to 2.8µA-15+15
GNDS_NB Input RangeVGNDS_NB-200+200mV
GNDS_NB GainAGNDS_NBΔVNBV_BUF/ΔVGNDS_NB,
-200mV ≤ VGNDS_NB ≤ +200mV0.951.001.05V/V
GNDS_NB Input Bias CurrentIGNDS_NB-2+2µA
FAULT DETECTIONNormal operation250300350mV
Output not in regulation
after a downward VID
transition
1.801.851.90Output Overvoltage Trip
ThresholdVOVP_
Measured at
FBDC_,
rising edge
Minimum OVP threshold0.8
Output Overvoltage Fault-
Propagation DelaytOVPFBDC_ forced 25mV above trip threshold10µs
Output Undervoltage-Protection
Trip ThresholdVUVPMeasured at FBDC_ with respect to
unloaded output voltage-450-400-350mV
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Undervoltage Fault-
Propagation DelaytUVPFBDC_ forced 25mV below trip threshold10µs
Measured at
FBDC_ with
respect to
unloaded output
voltage
Lower threshold, falling
edge (undervoltage)-350-300-250
PWRGD Threshold
15mV hysteresis
(typ)
Upper threshold, rising
edge (overvoltage)+150+200+250
PWRGD Propagation DelaytPWRGD_FBDC_ forced 25mV outside the PWRGD
trip thresholds10µs
PWRGD Output Low VoltageISINK = 4mA0.4V
PWRGD Leakage CurrentIPWRGD_High state, PWRGD forced to 5.5V1µA
PWRGD Startup Delay and
Transition Blanking TimetBLANK
Measured from the time when FBDC_
reaches the target voltage based on the
slew rate set by RTIMEµs
VRHOT Trip ThresholdMeasured at THRM, with respect to VCC,
falling edge, 115mV hysteresis (typ)29.53030.5%
VRHOT DelaytVRHOTTHRM forced 25mV below the VRHOT trip
threshold, falling edge10µS
VRHOT Output Low VoltageISINK = 4mA0.4V
VRHOT Leakage CurrentHigh state, VRHOT forced to 5V1µA
THRM Input Leakage-100+100nA
Thermal-Shutdown ThresholdTSHDNHysteresis = 15°C160°C
GATE DRIVERSHigh state (pullup)0.92.0DH_ Gate-Driver On-ResistanceRON(DH_)BST_ - LX_ forced
to 5VLow state (pulldown)0.72.0Ω
DL_, high state0.72.0DL_ Gate-Driver On-ResistanceRON(DL_)DL_, low state0.250.6Ω
DH_ Gate-Driver Source/Sink
CurrentIDH_DH_ forced to 2.5V, BST_ - LX_ forced to 5V2.2A
DL_ Gate-Driver Source CurrentIDL_
(SOURCE)DL_ forced to 2.5V2.7A
DL_ Gate-Driver Sink CurrentIDL_ (SINK)DL_ forced to 2.5V8A
tDH_DLDH_ low to DL_ high152540Dead TimetDL_DHDL_ low to DH_ high92035ns
Internal Boost Diode Switch RONBST1 to VDD1, BST2 to VDD2; measure with
10mA of current1020Ω
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= 0°C to +85°C, unless otherwise noted.Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
2-WIRE SVI BUS LOGIC INTERFACESVI Logic Input CurrentSVC, SVD-1+1µA
SVI Logic Input ThresholdSVC, SVD, rising edge,
hysteresis = 0.15VDDIO
0.3 x
VDDIO
0.7 x
VDDIOV
SVC Clock FrequencyfSVC3.4MHz
START Condition Hold TimetHD,STA160ns
Repeated START Condition
Setup TimetSU,STA160ns
STOP Condition Setup TimetSU,STO160ns
Data HoldtHD,DAT
A master device must internally provide a
hold time of at least 300ns for the SDA
signal (referred to the VIL of SCK signal) to
bridge the undefined region of SCL’s falling
edgens
Data Setup TimetSU,DAT10ns
SVC Low PeriodtLOW160ns
SVC High PeriodtHIGH60ns
SVC/SVD Rise and Fall TimetR, tFMeasured from 10% to 90% of VDDIO40ns
Pulse Width of Spike SuppressionInput filters on SVD and SVC suppress
noise spikes less than 50ns20ns
INPUTS AND OUTPUTSSHDN, PGD_IN-1+1Logic Input CurrentPRO, OPTION-3+3µA
Logic Input ThresholdSHDN, rising edge, hysteresis = 225mV0.82.0V
HighVCC -
Open3.153.85
REF1.652.35
Four-Level Input-Logic LevelsOPTION
Low0.4
HighVCC -
Open3.153.85Tri-Level Input-Logic LevelsPRO
Low0.4
PGD_IN Logic Input ThresholdPGD_IN0.3 x
VDDIO
0.7 x
VDDIOV
Low state, ISINK = 3mA0.4
NBSKP Logic Output VoltageHigh state, ISOURCE = 3mAVCC -
0.4
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= -40°C to +105°C, unless otherwise noted.)(Note 2)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
INPUT SUPPLIESVINDrain of external high-side MOSFET426
VBIASVCC, VDD1, VDD24.55.5Input Voltage Range
VDDIO1.02.7
VCC Undervoltage-Lockout
ThresholdVUVLOVCC rising 50mV typical hysteresis4.104.45V
VDDIO Undervoltage-Lockout
ThresholdVDDIO rising 100mV typical hysteresis0.80.9V
Quiescent Supply Current (VCC)ICCSkip mode, FBDC_ forced above their
regulation points10mA
Quiescent Supply Currents
(VDD1, VDD2)IDD1, IDD2Skip mode, FBDC_ forced above their
regulation points, TA = -40°C to +85°C1µAui escent S up p l y C ur r ent ( V D D I O) IDDIO25µA
Shutdown Supply Current (VCC)SHDN = GND, TA = -40°C to +85°C1µA
Shutdown Supply Currents
(VDD1, VDD2)SHDN = GND, TA = -40°C to +85°C1µA
Shutdown Supply Current (VDDIO)TA = -40°C to +85°C1µA
Reference VoltageVREFVCC = 4.5V to 5.5V, no REF load1.982.02V
Sourcing: IREF = 0 to 500µA-2Reference Load RegulationSinking: IREF = 0 to -100µA6.2mV
MAIN SMPS CONTROLLERSDAC codes from 0.8375V to 1.5500V-0.6+0.6%
DAC codes from 0.5000V to 0.8250V-6+6DC Output-Voltage Accuracy
(Note 1)VOUT
DAC codes from 0.4875V to 0.0125V-15+15mV
GNDS_ Input RangeVGNDS_Separate mode-200+200mV
GNDS_ GainAGNDS_
Separate: ΔVOUT_ /ΔVGNDS_,
-200mV ≤ VGNDS_ ≤ +200mV,
Combined: ΔVOUT/ΔVGNDS1,
-200mV ≤ VGNDS1 ≤ +200mV
0.951.05V/V
Combined-Mode Detection
Threshold
GNDS2, detection after REFOK, latched,
cleared by cycling SHDN0.70.9V
ROSC = 143kΩ (fOSC = 300kHz nominal)-7.5+7.5
Switching-Frequency AccuracyfOSCROSC = 35.7kΩ (fOSC = 1.2MHz nominal) to
432kΩ (fOSC = 99kHz nominal)-10+10%
Maximum Duty FactorDMAX90%
Minimum On-TimetONMIN185ns
RTIME = 143kΩ, SR = 6.25mV/µs-10+10
TIME Slew-Rate AccuracyDuring
transitionRTIME = 35.7kΩ to 357kΩ,
SR = 25mV/µs to 2.5mV/µs-15+15%
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= -40°C to +105°C, unless otherwise noted.)(Note 2)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
CURRENT LIMITCurrent-Limit Threshold ToleranceVLIMITVCSP_ - VCSN_ = 0.05 x (VREF - VILIM),
(VREF - VILM) = 0.2V to 1.0V-3+3mV
Idle Mode Threshold ToleranceVIDLEVCSP_ - VCSN_, SKIP mode, 0.15 x VLIMIT-1.5+1.5mV
CS_ Common-Mode Input RangeCSP_ and CSN_02V
Phase Disable ThresholdCSP23VCC -
0.4V
DROOP AND CURRENT BALANCEDC Droop Amplifier
TransconductanceGm(FBDC_)
ΔIFBDC_ /(ΔVCS_),
VFBDC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = -60mV to +60mV
0.971.03mS
DC Droop Amplifier OffsetIFBDC_ /Gm(FBDC_)-1.5+1.5mV
AC Droop and Current-Balance
Amplifier TransconductanceGm(FBAC_)
ΔIFBAC_ /(ΔVCS_),
VFBAC_ = VCSN_ = 1.2V,
VCSP_ - VCSN_ = -60mV to +60mV
0.971.03mS
AC Droop and Current-Balance
Amplifier OffsetIFBAC_/Gm(FBAC_)-1.5+1.5mV
Transient-Detection Threshold
Measured at FBDC_ with respect to
steady-state
FBDC_ regulation voltage,
5mV hysteresis (typ),
transient phase repeat enabled,
OPTION = OPEN or GND
-32-18mV
NB BUFFERDAC codes from 0.8375V to 1.5500V-0.6+0.6%
DAC codes from 0.5000V to 0.8250V-6+6NBV_BUF Output-Voltage
AccuracyVNBV_BUF
DAC codes from 0.4875V to 0.0125V-15+15mV
RTIME = 143kΩ,
INBV_BUF = 7.0µA-10+10NBV_BUF Short-Circuit Current
(Sets Slew Rate Together with
External Capacitor CNBV_BUF)
DAC code set to
1.2V, VNBV_BUF
= 0.4V and 2VRTI M E = 35.7kΩ to 357kΩ ,
IN B V _BU F = 28µA to 2.8µA-15+15
GNDS_NB Input RangeVGNDS_NB-200+200mV
GNDS_NB GainAGNDS_NBΔVNBV_BUF/ΔVGNDS_NB,
-200mV ≤ VGNDS_NB ≤ +200mV0.951.05V/V
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= -40°C to +105°C, unless otherwise noted.)(Note 2)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
FAULT DETECTIONOutput Overvoltage Trip
ThresholdVOVP_Measured at FBDC_,
rising edgeNormal operation250350mV
Output Undervoltage-Protection
Trip ThresholdVUVPMeasured at FBDC_ with respect to
unloaded output voltage-450-350mV
Measured at FBDC_
with respect to
unloaded output
voltage
Lower threshold,
falling edge
(undervoltage)
PWRGD Threshold
15mV hysteresis
(typ)
Upper threshold,
rising edge
(overvoltage)
+150+250
PWRGD Output Low VoltageISINK = 4mA0.4V
VRHOT Trip ThresholdMeasured at THRM, with respect to VCC,
falling edge, 115mV hysteresis (typ)29.530.5%
VRHOT Output Low VoltageISINK = 4mA0.4V
GATE DRIVERSHigh state (pullup)2.0DH_ Gate-Driver On-ResistanceRON(DH_)BST_ - LX_ forced
to 5VLow state (pulldown)2.0Ω
DL_, high state2.0DL_ Gate-Driver On-ResistanceRON(DL_)DL_, low state0.6Ω
tDH_DLDH_ low to DL_ high1540Dead TimetDL_DHDL_ low to DH_ high940ns
Internal Boost Diode Switch RONBST1 to VDD1, BST2 to VDD2, measured
with 10mA of current20Ω
2-WIRE SVI BUS LOGIC INTERFACESVI Logic Input ThresholdSVC, SVD, rising edge,
hysteresis = 0.15 x VDDIO
0.3 x
VDDIO
0.7 x
VDDIOV
SVC Clock FrequencyfSVC3.4MHz
START Condition Hold TimetHD,STA160ns
Repeated START Condition
Setup TimetSU,STA160ns
STOP Condition Setup TimetSU,STO160ns
Data HoldtHD,DAT
A m aster device must i nternal ly p rovid e a hold
tim e of at l east 300ns for the SD A sig nal (r efer r ed
to the VIL of S CK sig nal ) to b ri dg e the und efi nedeg ion of S CL’s fal li ng ed gens
Data Setup TimetSU,DAT10ns
SVC Low PeriodtLOW160ns
SVC High PeriodtHIGH60ns
SVC/SVD Rise and Fall TimetR, tFMeasured from 10% to 90% of VDDIO40ns
Note 1:When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error comparator
threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher than
the error comparator threshold by 50% of the ripple.
Note 2:Specifications to TA= -40°C to +105°C are guaranteed by design, not production tested.
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 2, VIN = 12V, VCC = VDD1 = VDD2 = SHDN= PGD_IN = 5V, VDDIO= 1.8V, PRO= OPTION = GNDS_NB = GNDS_ =
GND_, FBDC_ = FBAC_ = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA
= -40°C to +105°C, unless otherwise noted.)(Note 2)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
INPUTS AND OUTPUTSLogic Input ThresholdSHDN, rising edge, hysteresis = 225mV0.82.0V
HighVCC -
0.4V
Open3.153.85
REF1.652.35
Four-Level Input Logic LevelsOPTION
Low0.4
HighVCC -
Open3.153.85Tri-Level Input Logic LevelsPRO
Low0.4
PGD_IN Logic Input ThresholdPGD_IN0.3 x
VDDIO
0.7 x
VDDIOV
SVD
SVC
tSUSTPtSUDATtHDDAT
tCLHtHDSTT
VIH
VIL
tCLL
tBF
Figure 1. Timing Definitions Used in the Electrical Characteristics
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
1-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.2125V)MAX17009 toc01
LOAD CURRENT (A)
EFFICIENCY (%)1
VIN = 7V
VIN = 12V
VIN = 20V
2-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.2125V)MAX17009 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 7V
VIN = 12V
VIN = 20V
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.2125V, -1.2mV/A DROOP)MAX17009 toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)155
VIN = 12V
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.2000V, NO DROOP)MAX17009 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)155
VIN = 12V
1-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.8000V)MAX17009 toc05
LOAD CURRENT (A)
EFFICIENCY (%)1
VIN = 7V
VIN = 12V
VIN = 20V
2-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.8000V)MAX17009 toc06
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 7V
VIN = 12V
VIN = 20V
1-PHASE OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 0.8000V, -1.2mV/A DROOP)MAX17009 toc07
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)155
VIN = 12V
1-PHASE SWITCHING FREQUENCY
vs. LOAD CURRENTMAX17009 toc08
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)1
VIN = 7V
VIN = 12V
VIN = 20V
MAXIMUM INDUCTOR CURRENT
vs. INPUT VOLTAGEMAX17009 toc09
INPUT VOLTAGE (V)
INDUCTOR CURRENT (A)2010
PEAK CURRENT
DC CURRENT
VOUT = 1.2V
Typical Operating Characteristics(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
MAXIMUM INDUCTOR CURRENT
vs. TEMPERATUREMAX17009 toc10
TEMPERATURE (%)
INDUCTOR CURRENT (A)406080-200
PEAK CURRENT
DC CURRENT
VIN = 12V
VOUT = 1.2V
CURRENT BALANCE vs. LOAD CURRENTMAX17009 toc11
TOTAL LOAD CURRENT (A)
PER-PHASE CURRENT (A)304010
IOUT1
IOUT2
VOUT = 1.2V
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGEMAX17009 toc12
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)202510
IIN
IDD1 + IDD2
ICCVOUT = 1.2V
REFERENCE VOLTAGE DISTRIBUTIONMAX17009 toc13
REFERENCE VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 150
SMPS OUTPUT OFFSET
VOLTAGE DISTRIBUTIONMAX17009 toc14
OUTPUT OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)135-3
SAMPLE SIZE = 150VOUT1
VOUT2VDAC1 = VDAC2 = 1.200V
NBV_BUF OFFSET
VOLTAGE DISTRIBUTIONMAX17009 toc15
OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)135-3
SAMPLE SIZE = 150
VDAC_NB = 1.200V
FBDC TRANSCONDUCTANCE
DISTRIBUTIONMAX17009 toc16
TRANSCONDUCTANCE (mS)
SAMPLE PERCENTAGE (%)SAMPLE SIZE = 150FBDC1
FBDC2
REFERENCE VOLTAGE vs. LOAD CURRENT
MAX17009 toc17
REF LOAD CURRENT (μA)
REFERENCE VOLTAGE (V)608010020
Typical Operating Characteristics (continued)
(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
STARTUP WAVEFORMS (HEAVY LOAD)MAX17009 toc18
200μs/div
A. SHDN, 5V/div
B. ILX1, 10A/div
C. VOUT1, 0.5V/div
D. ILX2, 10A/div0
E. VOUT2, 0.5V/div
F. PWRGD, 5V/div
G. VNBV_BUF, 0.5V/div
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
STARTUP SEQUENCE WAVEFORMSMAX17009 toc19
400μs/div
A. SHDN, 5V/div
B. VNBV_BUF, 0.5V/div
C. VOUT1, 0.5V/div
D. VOUT2, 0.5V/div
VIN = 12V, VBOOT = 1.0V, ILOAD1 = ILOAD2 = 3A
E. PWRGD, 3.3V/div
F. PGD_IN, 3.3V/div
G. SVC, 2V/div
H. SVD, 2V/div
SHUTDOWN WAVEFORMSMAX17009 toc20
200μs/div
A. SHDN, 5V/div
B. DL1, 10V/div
C. VOUT1, 0.5V/div
D. DL2, 10V/div
VIN = 12V, ILOAD1 = ILOAD2 = 3A
3.3V
1.2V
1.2V
1.2V
3.3V
E. VOUT2, 0.5V/div
F. VNBV_BUF, 2V/div
G. PWRGD, 5V/div
1-PHASE LOAD TRANSIENT (-1.2mV/A DROOP)MAX17009 toc21
20μs/div
A. VOUT1, 50mV/div
B. ILX1, 10A/div
C. LX1, 10V/div
VIN = 12V
ILOAD1 = 3A TO 15A TO 3A
1.2V
15A
12V
1-PHASE TRANSIENT PHASE REPEAT
(-1.2mV/A DROOP)MAX17009 toc22
2μs/div
A. VOUT1, 50mV/div
B. ILX1, 10A/div
C. LX1, 10V/div
VIN = 12V
ILOAD1 = 3A TO 15A TO 3A
1.2V
15A
12V
1-PHASE LOAD TRANSIENT
(NO DROOP)MAX17009 toc23
20μs/div
A. VOUT1, 50mV/div
B. ILX1, 10A/div
C. LX1, 10V/div
VIN = 12V
ILOAD1 = 3A TO 15A TO 3A
1.2V
15A
12V
1-PHASE TRANSIENT PHASE REPEAT
(NO DROOP)MAX17009 toc24
2μs/div
A. VOUT1, 50mV/div
B. ILX1, 10A/div
C. LX1, 10V/div
VIN = 12V
ILOAD1 = 3A TO 15A TO 3A
1.2V
15A
12V
Typical Operating Characteristics (continued)(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
2-PHASE LOAD TRANSIENT
(-1.2mV/A DROOP)MAX17009 toc25
20μs/div
A. VOUT1, 50mV/div
VIN = 12V
1.2V
15A
15A
2-PHASE TRANSIENT PHASE REPEAT
(-1.2mV/A DROOP)MAX17009 toc26
2μs/div
A. VOUT1, 50mV/div
VIN = 12V
1.2V
15A
15A
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
1-PHASE OUTPUT OVERLOADMAX17009 toc27
200μs/div
A. PWRGD, 5V/div
B. VOUT1, 1V/div
C. DL1, 10V/div
D. VOUT2, 1V/div
E. DL2, 10V/div
F. VNBV_BUF, 1V/div
VIN = 12V, ILOAD1 = 3A TO 30A, ILOAD2 = 3A
3.3V
1.2A
1.2V
1.2V
1-PHASE OUTPUT OVERVOLTAGEMAX17009 toc28
200μs/div
A. PWRGD, 5V/div
B. VOUT1, 1V/div
C. DL1, 10V/div
D. VOUT2, 1V/div
E. DL2, 10V/div
F. VNBV_BUF, 1V/div
VIN = 12V, ILOAD1 = 50mA, ILOAD2 = 3A
3.3V
1.2A
1.2V
1.2V
DYNAMIC OUTPUT-VOLTAGE
TRANSITIONS (LIGHT LOAD)MAX17009 toc29
100μs/div
A. VNBV_BUF, 1V/div
B. LX1, 20V/div
C. VOUT1, 0.5V/div
D. LX2, 20V/div
E. VOUT2, 0.5V/div
F. SVC, 5V/div
G. SVD, 5V/div
VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V,
ILOAD1 = ILOAD2 = 3A
1.3V
12V
12V
2.5V
1.3V
1.3V
0.6V
0.6V
0.6V
2.5V
DYNAMIC OUTPUT-VOLTAGE
TRANSITIONS (HEAVY LOAD)MAX17009 toc30
100μs/div
A. VNBV_BUF, 1V/div
B. LX1, 20V/div
C. VOUT1, 0.5V/div
D. LX2, 20V/div
E. VOUT2, 0.5V/div
F. SVC, 5V/div
G. SVD, 5V/div
VIN = 12V, VDACS = 1.3V TO 0.6V TO 1.3V,
ILOAD1 = ILOAD2 = 10A
1.3V
12V
12V
2.5V
1.3V
1.3V
0.6V
0.6V
0.6V
2.5V
PGD_IN FALLING TRANSITIONSMAX17009 toc31
10μs/div
A. VNBV_BUF, 200mV/div
B. VOUT1, 200mV/div
C. VOUT2, 200V/div
D. LX1, 20V/div
E. LX2, 20V/div
F. PGD_IN, 5V/div
G. PWRGD, 5V/div
VIN = 12V, VBOOT = 1.1V, VDAC1 = 0.8V, VDAC2 = 1.3V,
VNBV_BUF = 0.8V, ILOAD1 = ILOAD2 = 3A
1.1V
1.1V
12V
12V
2.5V
0.8V
0.8V
1.3V
2.5V
Typical Operating Characteristics (continued)(Circuit of Figure 2, VIN = 12V, VDD= VCC= 5V, VDDIO= 2.5V, TA = +25°C, unless otherwise noted.)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Pin Description
PINNAMEFUNCTIONPWRGD
Open-Drain, Power-Good Output. PWRGD indicates when both SMPSs are in regulation.
PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions). After output-voltage transitions, except during power-up and power-down, if FBDC_ is in
regulation, then PWRGD is high impedance.
During startup, PWRGD is held low an additional 20μs after the MAX17009 reaches the startup boot
voltage set by the SVC, SVD pins. The MAX17009 stores the boot VID when PWRGD first goes high.
The stored boot VID is cleared by rising SHDN.
PWRGD is forced low in shutdown.
When in pulse-skipping mode, the upper PWRGD threshold comparator is blanked during a lower VID
transition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 4). NBV_BUF
North Bridge Buffered Reference Voltage. This output is connected to the REFIN input of the NB
controller (switcher or LDO) to set the NB regulator voltage. The NBV_BUF output current is set by the
TIME resistor. The NBV_BUF current and the total output capacitance set the NBV_BUF slew rate:
INBV_BUF = (7μA) x (143k / RTIME)
NBV_BUF Slew rate = INBV_BUF / CNBV_BUF
INBV_BUF is the same during startup, shutdown, and any VID transition.
Bypass to GND with a 100pF minimum low-ESR (ceramic) capacitor at the NBV_BUF pin. SHDN
Shutdown Control Input. Connect high (2V to VCC) for normal operation. Connect to ground to put the IC
into its 1μA max shutdown state.
During startup, the SMPS output voltages and the NBV_BUF voltage are ramped up to the voltage set
by the SVC, SVD inputs. The SMPSs start up and shut down at a fixed slew rate of 1mV/μs.
SVCSVDBOOT VOLTAGE (VBOOT)
(PRO = VCC OR GND)
BOOT VOLTAGE (VBOOT)
(PRO = OPEN)01.1 1.1 11.0 1.2 00.9 1.0 10.8 0.8
The MAX17009 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by
rising SHDN.REF
2.0V Reference Output. Bypass to GND with a 1μF maximum low-ESR (ceramic) capacitor. REF
sources up to 500μA for external loads. Loading REF degrades output accuracy, according to the REF
load-regulation error. ILIM
Current-Limit Adjust Input. The positive current-limit threshold voltage is precisely 1/20 of the voltage
between REF and ILIM over a 0.2V to 1.0V range of V(REF, ILIM). The IMIN minimum current-limit threshold
voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage. OSC
Oscillator Adjustment Input. Connect a resistor (ROSC) between OSC and GND to set the switching
frequency (per phase):
fOSC = 300kHz x 143k / ROSC
A 35.7k to 432k corresponds to switching frequencies of 1.2MHz to 100kHz, respectively.
Switching-frequency selection is limited by the minimum on-time. See the Switching frequency bullet
in the SMPS Design Procedure section.
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
PINNAMEFUNCTION7 TIMESlew-Rate Adjustment Pin. Connect a resistor RTIME from TIME to GND to set the internal slew rate:PWM Slew rate = (6.25mV/µs) x (143kΩ / RTIME)
NBV_BUF Slew rate = (7µA) x (143kΩ / RTIME) / CNBV_BUFwhere RTIME is between 35.7kΩ and 357kΩ for corresponding slew rates between 25mV/µs to 2.5mV/µs,
respectively, for the SMPSs, and NBV_BUF currents between 28µA and 2.8µA, respectively, for the
NBV_BUF.This slew rate applies to both upward and downward VID transitions, and to the transition from boot mode
to VID mode. Downward VID transition slew rate can appear slower because the output transition is not
forced by the SMPS.The SMPS slew rate for startup and shutdown is fixed at 1mV/µs.The NBV_BUF slew rate is the same during startup, shutdown, and normal VID transitions.8 SVC S er i al V ID C l ock. D ur i ng the p ow er - up seq uence and i n d eb ug m od e, S V C i s the M S B of the 2- b i t V ID D AC .9 SVD S er i al V ID D ata. D ur i ng the p ow er - up seq uence and i n d eb ug m od e, S V D i s the LS B of the 2- b i t V ID D AC .10 THRM Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between VCC and
GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of VCC) at the
desired high temperature.11 GNDS2
SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2 internally
connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage
drops from the regulator ground to the load ground.
Connect GNDS2 above 0.9V combined-mode operation (unified core). When operating in combined
mode, GNDS1 is used as the remote ground-sense input.12 FBDC2Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS2. Connect a resistor RFBDC2
between FBDC2 and the positive side of the feedback remote sense to set the DC steady-state droop
based on the voltage-positioning gain requirement:RFBDC2 = RDROOPDC / (RSENSE2 x Gm(FBDC2))where RDROOPDC is the desired voltage positioning slope and Gm(FBDC2) = 1mS typ. RSENSE2 is the
value of the current-sense resistor that is used to provide the (CSP2, CSN2) current-sense voltage.
To disable the load-line, short FBDC2 to the positive remote-sense point.
FBDC2 is high impedance in shutdown.13 FBAC2Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS2. The resistance between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:RFBAC2 = RDROOPAC / (RSENSE2 x Gm(FBAC2))where RDROOPAC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff
between stability and load transient response, Gm(FBAC2) and RSENSE2 is the value of the current-sense
resistor that is used to provide the (CSP2, CSN2) current-sense voltage.
The maximum difference between transient (AC) droop and DC droop should not exceed ±80mV at the
maximum allowed load current (DC droop is set at the FBDC2 pin).Internally, V(FBDC2 - GNDS2) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC2 -
GNDS2) goes to the error comparator (fast transient loop).
FBAC2 is high impedance in shutdown.
Note: The AC and DC droop cannot be different by more than ±3mV/A.14 VDDIO CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at VDDIO.15 GNDS_NB
North Bridge Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the
load. GNDS_NB internally connects to a transconductance amplifier that fine tunes the NBV_BUF output
voltage compensating for voltage drops from the regulator ground to the load ground.
Pin Description (continued)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
PINNAMEFUNCTION16CSN2Negative Current-Sense Input for SMPS2. Connect to the negative side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.17CSP2
Positive Current-Sense Input for SMPS2. Connect to the positive side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
Connect CSP2 to VCC to disable SMPS2. This allows the MAX17009 to operate as a 1-phase regulator.18 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum. A VCC
UVLO event that occurs while the IC is functioning is latched, and can only be cleared by cycling VCC
power or by toggling SHDN.19 NBSKPNorth Bridge Skip Push-Pull Control Output. When NBSKP is high, the NB switching regulator is set to
forced-PWM mode. When NBSKP is low, the NB switching regulator is set to pulse-skipping mode. The
NBSKP level is set through the serial interface during normal operation.
NBSKP is high in shutdown and during soft-shutdown.
NBSKP is high in startup until commanded otherwise.20 DH2 SMPS2 High-Side, Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.21 LX2 SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also
used as an input to phase 2’s zero-crossing comparator.22 BST2 Boost Flying-Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between VDD2
and BST2 charges the flying capacitor during the time the low-side FET is on.23VDD2
Supply Voltage Input for the DL2 Driver. VDD2 is also the supply voltage used to internally recharge the
BST2 flying capacitor during the off-time of phase 2. Connect VDD2 to the 4.5V to 5.5V system supply
voltage. Bypass VDD2 to GND with a 1µF or greater ceramic capacitor.24 DL2 SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to VDD2. DL2 is forced low in shutdown.
DL2 is also forced high when an output overvoltage fault is detected. DL2 is forced low in skip mode after
an inductor current zero crossing (GND2 - LX2) is detected.25 GND2 Power Ground for SMPS2. Ground connection for the DL2 driver. Also used as an input to SMPS2’s zero-
crossing comparator. GND1 and GND2 are internally connected.26 GND1 Power Ground for SMPS1. Ground connection for the DL1 driver. Also used as an input to SMPS1’s zero-
crossing comparator. GND1 and GND2 are internally connected.27 DL1 SMPS1 Low-Side, Gate-Driver Output. DL1 swings from GND1 to VDD1. DL1 is forced low in shutdown.
DL1 is also forced high when an output overvoltage fault is detected. DL1 is forced low in skip mode after
an inductor current zero crossing (GND1 - LX1) is detected.28VDD1
Supply Voltage Input for the DL1 Driver. VDD1 is also the supply voltage used to internally recharge the
BST1 flying capacitor during the off-time of phase 1. Connect VDD1 to the 4.5V to 5.5V system supply
voltage. Bypass VDD1 to GND with a 1µF or greater ceramic capacitor.29 BST1 Boost Flying-Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between VDD1
and BST1 charges the flying capacitor during the time the low-side FET is on.30 LX1 SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also
used as an input to phase 1’s zero-crossing comparator.31 DH1 SMPS1 High-Side, Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.32 VRHOT Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below
1.5V (30% of VCC). VRHOT is high impedance in shutdown.
Pin Description (continued)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
PINNAMEFUNCTIONPRO
Protection Disable. PRO also sets the MAX17009 in debug mode.
Connect PRO high to disable OVP protection.
Connect PRO to GND to enable OVP protection.
When PRO is floated, the MAX17009 disables the OVP protection and also enters debug mode (see the
SHDN pin description). When PGD_IN is low in debug mode, the MAX17009 DAC voltages are set by
the 2-bit boot VID. When PGD_IN is high, the MAX17009 changes to serial VID mode. CSP1 Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing resistor
or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. CSN1 Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor
or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing. PGD_IN
System Power-Good Input. Indicates to the MAX17009 that the system is ready to enter serial VID mode.
PGD_IN is low when SHDN first goes high, the MAX17009 decodes the boot VID to determine the boot
voltage. The boot VID can be changed dynamically while PGD_IN remains low and PWRGD. The boot
VID is stored after PWRGD goes high.
PGD_IN goes high after the MAX17009 reaches the boot voltage. This indicates that the SVI block is
active, and the MAX17009 starts to respond to the serial-interface commands.
After PGD_IN has gone high, if at anytime PGD_IN should go low, the MAX17009 regulates to the
previously stored boot VID. OPTION
Four-Level Input to Enable Offset and Transient-Phase Repeat
OPTIONOFFSET ENABLEDTRANSIENT-PHASE REPEAT ENABLEDVCC00
OPEN 01
REF 10
GND 11
When OFFSET is enabled, the MAX17009 enables a fixed +12.5mV offset on each of the SMPS VID
codes after PGD_IN goes high. This configuration is intended for applications that implement a load-
line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting the PSI_L
bit to zero through the serial interface.
When OFFSET is disabled, the intended application has no load-line, and the FBDC_ pins are directly
connected to the remote-sense points.
Transient phase repeat allows the MAX17009 to reenable the current phase in response to a load
transient, even after that phase has finished its on-pulse. FBAC1
Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The resistance between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
RFBAC1 = RDROOPAC / (RSENSE1 x Gm(FBAC1))
where RDROOPAC is the transient (AC) voltage-positioning slope that PROvides an acceptable tradeoff
between stability and load-transient response, Gm(FBAC1) and RSENSE1 is the value of the current-sense
resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage.
The maximum difference between transient (AC) droop and DC droop should not exceed ±80mV at the
maximum allowed load current (DC droop is set at the FBDC2 pin).
Internally, V(FBDC1 - GNDS1) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC1
- GNDS1) goes to the error comparator (fast-transient loop).
FBAC1 is high impedance in shutdown.
Note: The AC and DC droop cannot be different by more than ±3mV/A.
Pin Description (continued)
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
PINNAMEFUNCTIONFBDC1
Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS1. Connect a resistor
RFBDC1 between FBDC1 and the positive side of the feedback remote sense to set the DC steady-
state droop based on the voltage-positioning gain requirement:
RFBDC1 = RDROOPDC / (RSENSE1 x Gm(FBDC1))
where RDROOPDC is the desired voltage-positioning slope and Gm(FBDC1) = 1mS typ. RSENSE1 is the
value of the current-sense resistor that is used to PROvide the (CSP1, CSN1) current-sense voltage.
To disable the load-line, short FBDC2 to the positive remote-sense point.
FBDC1 is high impedance in shutdown. GNDS1
SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1 internally
connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage
drops from the regulator ground to the load ground.
GNDS1 is the remote ground-sense input in combined-mode operation. EPExposed Pad. Connect the exposed backside pad to GND1 and GND2.
Pin Description (continued)
COMPONENTVIN = 7V TO 20V
VOUT = 1.0V - 1.3V / 18A PER PHASE
VIN = 4.5V TO 14V
VOUT_ = 1.0V - 1.3V / 18A PER PHASEMODE Separate, 2-phase mobile
(GNDS2 not high)
Separate, 2-phase mobile
(GNDS2 not high)
Switching Frequency 280kHz
(ROSC = 154k)
600kHz
(ROSC = 71.5k)
CIN_, Input Capacitor (per Phase) (2) 10μF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10μF, 16V
Taiyo Yuden TMK432BJ106KM
COUT_, Output Capacitor
(per Phase)
(2) 470μF, 2V, 6m,
low-ESR capacitor
NEC/Tokin PSGD0E477M6 or
Panasonic EEFUD0D471L6
(2) 330μF, 2.5V, 6m,
low-ESR capacitor
Panasonic EEFSD0D331XR
NH_ High-Side MOSFET (1) Fairchildsemi
FDMS8690
(1) International Rectifier
IRF7811W
NL_ Low-Side MOSFET (2) Vishay
Si7336ADP
(2) Fairchildsemi
FDMS8660S
DL_ Schottky Rectifier
3A, 40V Schottky diode
Central Semiconductor
CMSH3-40
None
L_ Inductor
0.45μH, 30A, 1.1m power inductor
TOKO FDUE1040D-R45M or
NEC/Tokin MPC1040LR45
0.22μH, 25A, 1m power inductor
NEC/Tokin MPC0730LR20
Table 1. Component Selection for Standard ApplicationsTable 1 shows the component selection for standard applications and Table 2 lists component suppliers.
Note: Mobile applications should be designed for separate mode operation. Component selection dependent on AMD CPU AC andDC specifications.
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Standard Application CircuitsThe MAX17009 standard application circuit (Figure 2)
generates two independent 18A outputs for AMD
mobile CPU applications. See Table 1 for component
selections. Table 2 lists the component manufacturers.
Detailed DescriptionThe MAX17009 consists of a dual-fixed-frequency PWM
controller that generates the supply voltage for two inde-
pendent CPU cores. A reference buffer output
(NBV_BUF) sets the regulation voltage for a separate
NB regulator. The CPU cores can be configured as
independent outputs, or as a combined output based
on the GNDS2 pin strap (GNDS2 pulled to 1.5V - 1.8V,
which are the respective voltages for DDR3 and DDR2).
Both SMPS outputs and the NB buffer can be pro-
grammed to any voltage in the VID table (see Table 4)
using the SVI. The CPU is the SVI bus master, while the
MAX17009 is the SVI slave. Voltage transitions are
commanded by the CPU as a single-step command
from one VID code to another. The MAX17009 slews
the SMPS outputs at the slew rate programmed by the
external RTIMEresistor. For the NB buffer, the slew rate
is set by the combination of RTIMEand the total capaci-
tance on the output of the buffer.
By default, the MAX17009 SMPSs are always in pulse-
skip mode. In separate mode, the PSI_L bit does not
change the mode of operation, but removes the
+12.5mV offset, if enabled by the OPTION pin. In com-
bined mode, the PSI_L bit removes the +12.5mV offset
and switches from 2-phase to 1-phase operation. The
NB_SKPoutput always follows the state of PSI_L for the
NB regulator.
+5V Bias Supply (VCC, VDD)The MAX17009 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s main 95%-efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers.
The 5V bias supply powers both the PWM controller
and internal gate-drive power, so the maximum current
drawn is:
IBIAS= ICC+ fSWQG= 10mA to 60mA (typ)
where ICCis provided in the Electrical Characteristics
table, and fSWQG(per phase) is the driver’s supply cur-
rent, as defined in the MOSFET’s data sheet. If the +5V
bias supply is powered up prior to the battery supply,
the enable signal (SHDNgoing from low to high) must
be delayed until the battery voltage is present to ensure
startup.
Switching Frequency (OSC)Connect a resistor (ROSC) between OSC and GND to
set the switching frequency (per phase):
fSW= 300kHz x 143kΩ/ ROSC
A 35.7kΩto 432kΩcorresponds to switching frequencies
of 1.2MHz to 100kHz, respectively. High-frequency
(1.2MHz) operation optimizes the application for the
smallest component size, trading off efficiency due to
higher switching losses. This may be acceptable in
ultra-portable devices where the load currents are lower
and the controller is powered from a lower voltage sup-
ply. Low-frequency (100kHz) operation offers the best
overall efficiency at the expense of component size and
board space. Minimum on-time (tON(MIN)) must also be
taken into consideration. See the Switching frequency
bullet in the SMPS Design Proceduresection.
MANUFACTURERWEBSITEAVXwww.avxcorp.com
BI Technologieswww.bitechnologies.com
Central Semiconductorwww.centralsemi.com
Fairchild Semiconductorwww.fairchildsemi.com
International Rectifierwww.irf.com
KEMETwww.kemet.com
NEC Tokinwww.nec-tokin.com
Panasonicwww.panasonic.com
MANUFACTURERWEBSITEPulsewww.pulseeng.com
Renesaswww.renesas.com
SANYOwww.secc.co.jp
Siliconix (Vishay)www.vishay.com
Sumidawww.sumida.com
Taiyo Yudenwww.t-yuden.com
TDKwww.component.tdk.com
TOKOwww.tokoam.com
Table 2. Component Suppliers
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency ControllerREFIN
SKIP
VCORE_NB
AGND
FROM
MAX17009
NB CONTROL
POWER GROUND
ANALOG GROUND
PWRGD
+3.3V
+5V
LX1
DH1
BST1
DL1
VDD1
GND1
RVCC
10Ω
CVCC
2.2μF
CREF
0.22μF
ROSC
RTIME
VCC
VDDIO
ILIM
VIN
4.5V TO 28V
RSENSE1
1mΩ
COUT1
2 x 470μF
6mΩ
VCORE0/18A
0.45μH
CSP1
100kΩ
VR_HOT
LX2
DH2
BST2
DL2
GND2
SERIAL
INPUT
SVC
SVD
PGD_IN
SHDN
OPTION
TO NB
REGULATOR
OSC
TIME
REF
CNBV_BUF
CONNECT TO SYSTEM
1.8V VDDIO SUPPLY
CONNECT TO SYSTEM
PWROK SIGNAL
VDD2
1000pF
CSN1
CSP1
CSN2
CSP2
PRO 3-LEVEL OPTION:VCC = DISABLE OVP
OPEN = DEBUG MODEGND = ENABLE OVP
OPTION
VCCOPEN
REFGND0111
OFFSETPH-RPT
PWRAGND
AGND
AGND
AGND{
VCCFBDC1CORE0 SENSE_H
FBAC1
AGND
ENABLE
FBDC2
FBAC2
GNDS140
GNDS211
100kΩ
MAX17009
RILIM2
RTHRM
RNTC
RILIM1
PRO33
AGND
AGND
AGND
CSN1
NB_SKP19
NBV_BUF2
THRM10
10Ω
GNDS_NB15
AGND
CVDD1
1μF
CBST1
0.22μF
NH1
NL1DL1
PWR
CVDD2
1μF
PWR
CIN1
PWR
VIN
4.5V TO 28V
RSENSE2
1mΩ
COUT2
2 x 470μF
6mΩ
VCORE1/18A
0.45μH
CSP2PWRRFBAC1
1.5kΩ
RFBDC1
1.1Ω
100Ω
4700pFC3
1000pF
CSN2
CBST2
0.22μF
NH2
NL2DL2
CIN2
PWR
RCSP1
75Ω
CCSP1
2.2nF
CSP1
RCSN1
10Ω
CCSN1
1nF
CSN1
AGND
RCSP2
75Ω
CCSP2
2.2nF
CSP2
RCSN2
10Ω
CCSN2
1nF
CSN2
CORE1 SENSE_H
AGND
RFBAC2
1.5kΩ
RFBDC2
1.1Ω
100Ω
4700pFC41000pF
CORE0 SENSE_L
AGND
100Ω
4700pF
CORE1 SENSE_L
AGND
100Ω
4700pF
NB REGULATOR
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Interleaved Multiphase OperationThe MAX17009 interleaves both phases—resulting in
180°out-of-phase operation that minimizes the input and
output filtering requirements, reduces electromagnetic
interference (EMI), and improves efficiency. The high-
side MOSFETs do not turn on simultaneously during nor-
mal operation. The instantaneous input current is
effectively reduced by the number of active phases,
resulting in reduced input-voltage ripple, ESR power loss,
and RMS ripple current (see the Input-Capacitor
Selection section). Therefore, the controller achieves high
performance while minimizing the component count,
which reduces cost, saves board space, and lowers
component power requirements, making the MAX17009
ideal for high-power, cost-sensitive applications.
Transient-Phase RepeatWhen a transient occurs, the output-voltage deviation
depends on the controller’s ability to quickly detect the
transient and slew the inductor current. A fixed-fre-
quency controller typically responds only when a clock
edge occurs, resulting in a delayed transient response.
To minimize this delay time, the MAX17009 includes
enhanced transient detection and transient- phase-
repeat capabilities. If the controller detects that the out-
put voltage has dropped by 25mV, the transient-
detection comparator immediately retriggers the phase
that completed its on-time last. The controller triggers
the subsequent phases as normal on the appropriate
oscillator edges. This effectively triggers a phase a full
cycle early, increasing the total inductor-current slew
rate and providing an immediate transient response.
The OPTION pin setting enables or disables the tran-
sient phase-repeat feature. Keep OPTION OPEN or
connected to GND to enable transient-phase repeat.
Connect OPTION to VCCor REF to disable transient-
phase repeat. See the Offset and Transient-Phase
Repeat (OPTION)section.
Feedback Adjustment Amplifiers
Steady-State Voltage-Positioning
Amplifier (DC Droop)Each of the MAX17009 SMPS controllers includes two
transconductance amplifiers—one for steady-state DC
droop, and another for AC droop. The amplifiers’ inputs
are generated by summing their respective current-sense
inputs, which differentially sense the voltage across either
current-sense resistors or the inductor’s DCR.
The DC droop amplifier’s output (FBDC) connects to
the remote-sense point of the output through a resistor
that sets each phase’s DC voltage-positioning gain:
where the target voltage (VTARGET) is defined in the
Nominal Output-Voltage Selectionsection, and the
FBDC amplifier’s output current (IFBDC) is determined
by each phase’s current-sense voltage:
where VCS= VCSP- VCSNis the differential current-
sense voltage, and GM(FBDC)is typically 1mS as
defined in the Electrical Characteristics table.
DC droop is typically used together with the +12.5mV
offset feature to keep within the DC tolerance window of
the application. See the Offset and Transient-Phase
Repeat (OPTION)section. The ripple voltage on FBDC
must be less than the 18mV (min) transient phase
repeat threshold:
where ΔILis the inductor ripple current, RESRis the
effective output ESR at the remote sense point, RSENSEis
the current-sense element, and Gm(FBDC)is 1.03mS
(max) as defined in the Electrical Characteristics table.
The worst-case inductor ripple occurs at the maximum
input voltage and the minimum output-voltage conditions:
To disable voltage positioning, set RFBDCto zero.
Transient Voltage-Positioning Amplifier (AC Droop)The AC droop amplifier’s output (FBAC) connects to
the remote-sense point of the output through a resistor
that sets each phase’s AC voltage-positioning gain:
where the target voltage (VTARGET) is defined in the
Nominal Output-Voltage Selectionsection, and the
FBAC amplifier’s output current (IFBAC) is determined
by each phase’s current-sense voltage:
where VCS= VCSP- VCSNis the differential current-
sense voltage, and GM(FBAC)is 1.03mS (max), as
defined in the Electrical Characteristics table.
AC droop is required for stable operation of the
MAX17009. A minimum of 1mV/A is recommended. AC
droop must not be disabled.VFBACmFBACCS=()RIOUTTARGETFBACFBAC=−VVVLLMAX
OUTMININMAXOUTMINMAXOSC()()()=−()mVRRGFBDCLESRSENSEmFBDC≤−⎛⎜⎞⎟−18()ΔIRGRIRmVLSENSEmFBDCFBDCLESR()+≤18VFBDCmFBDCCS=()RIOUTTARGETFBDCFBDC=−
MAX17009
AMD Mobile Serial VID Dual-Phase
Fixed-Frequency ControllerThe maximum allowable AC droop is limited by the rec-
ommended integrator correction range of ±100mV and
on the DC droop:
Differential Remote SenseThe MAX17009 controller includes independent differ-
ential, remote-sense inputs for each CPU core to elimi-
nate the effects of voltage drops along the PC board
(PCB) traces and through the processor’s power pins.
The feedback-sense (FBDC_) input connects to the
voltage-positioning resistor (RFBDC_). The ground-
sense (GNDS_) input connects to an amplifier that
adds an offset directly to the target voltage, effectively
adjusting the output voltage to counteract the voltage
drop in the ground path. Connect the feedback-sense
(FBDC_) voltage-positioning resistor (RFBDC_), and
ground-sense (GNDS_) input directly to the respective
CPU core’s remote-sense outputs as shown in Figure 2.
GNDS2 has a dual function. At power-on, the voltage
level on GNDS2 configures the MAX17009 as two inde-
pendent switching regulators, or one higher current
two-phase regulator. Keep GNDS2 low during power-
up to configure the MAX17009 in separate mode.
Connect GNDS2 to a voltage above 0.8V (typ) for com-
bined-mode operation. In the AMD mobile system, this
is automatically done by the CPU that is plugged into
the socket that pulls GNDS2 to the VDDIOvoltage level.
The MAX17009 checks the GNDS2 level at the time
when the internal REFOK signal goes high, and latches
the operating mode information (separate or combined
mode). This latch is cleared by cycling the SHDNpin.
Integrator AmplifierAn internal integrator amplifier forces the DC average
of the FBDC_ voltage to equal the target voltage. This
transconductance amplifier integrates the feedback
voltage and provides a fine adjustment to the regulation
voltage (Figure 3), allowing accurate DC output-voltage
regulation regardless of the output-ripple voltage. The
integrator amplifier has the ability to shift the output
voltage by ±100mV (min).
The MAX17009 disables the integrator by connecting
the amplifier inputs together at the beginning of all VID
transitions done in pulse-skipping mode. The integrator
remains disabled until 20µs after the transition is com-
pleted (the internal target settles), and the output is in
regulation (edge detected on the error comparator).
When voltage positioning is disabled (RFBDC_= 0Ω),
the AC droop setting must be less than the ±100mV
minimum adjustment range of the integrator amplifier to
guarantee proper DC output-voltage accuracy. See the
Steady StateVoltage-Positioning Amplifiers (DC Droop)
and theTransient Voltage-Positioning Amplifiers (AC
Droop)sections.
2-Wire Serial Interface (SVC, SVD)The MAX17009 supports the 2-wire, write only, serial-
interface bus as defined by the AMD Serial VID
Interface Specification. The serial interface is similar to
the high-speed 3.4MHz I2C bus, but without the master
mode sequence. The bus consists of a clock line (SVC)
and a data line (SVD). The CPU is the bus master, and
the MAX17009 is the slave. The MAX17009 serial inter-
face works from 100kHz to 3.4MHz. In the AMD mobile
application, the bus runs at 3.4MHz.
The serial interface is active only after PGD_IN goes
high in the startup sequence. The CPU sets the VID
voltage of the three internal DACs and the PSI_L bit
through the serial interface.
During the startup sequence, the SVC and SVD inputs
serve an alternate function to set the 2-bit boot VID for
all three DACs while PWRGD is low. In debug mode,
the SVC and SVD inputs function in the 2-bit VID mode
when PGD_IN is low, and in the serial-interface mode
when PGD_IN is high.
Nominal Output-Voltage Selection
SMPS Output VoltageThe nominal no-load output voltage (VTARGET_) for
each SMPS is defined by the selected voltage refer-
ence (VID DAC) plus the remote ground-sense adjust-
ment (VGNDS) and the offset voltage (VOFFSET) as
defined in the following equation:
where VDACis the selected VID voltage of the SMPS
DAC, VGNDSis the ground-sense correction voltage,
and VOFFSETis the +12.5mV offset enabled by the
OPTION pin, when the PSI_L is set high.
NBV_BUF Output VoltageThe nominal output voltage (VTARGET) for the NBV_BUF
is defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (VGNDS), as
defined in the following equation:
where VDAC_is the selected VID voltage of the
NBV_BUF DAC, and VGNDS_NB_is the ground-sense
correction voltage. The offset voltage (VOFFSET) is not
applied to NBV_BUF.VVTARGETNBVBUFDACGNDSNB==+__VVVTARGETFBDCDACGNDSOFFSET==++RRmV
mSIRFBACFBDC
LOADMAXSENSE−≤100
103.()
