MAX1603EAI ,Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching NetworksApplicationsMAX157ACUA 0°C to +70°C 8 µMAX ±0.5Battery-Powered Systems InstrumentationMAX157BCUA 0° ..
MAX16047ETN+ ,12-/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault RegistersApplicationswatchdog input or output (WDI/WDO), or as a manualServersreset (MR).WorkstationsThe MAX ..
MAX1604EAI ,Dual-Channel CardBus and PCMCIA Power Switches with SMBus Serial InterfaceApplicationsVLMAX1601/MAX1604Desktop Computers Data Loggers VDDOVERCURRENTDECODESMBCLK AND SMBALER ..
MAX16052AUT+T ,High-Voltage, Adjustable Sequencing/Supervisory CircuitsElectrical Characteristics(V = 2.25V to 28V, V = V , T = T = -40°C to +125°C, unless otherwise spec ..
MAX16053AUT+T ,High-Voltage, Adjustable Sequencing/Supervisory CircuitsApplications(EN = low), the output deasserts (OUT = low). The devices provide a capacitor programma ..
MAX16054AZT+T ,On/Off Controller with Debounce and ±15kV ESD ProtectionELECTRICAL CHARACTERISTICS(V = +2.7V to +5.5V, T = T = -40°C to +125°C, unless otherwise noted. Typ ..
MAX4298EUB ,Ultra-High PSRR Stereo Drivers + Microphone Amp + 100mA Linear Regulator
MAX4298EUB ,Ultra-High PSRR Stereo Drivers + Microphone Amp + 100mA Linear Regulator
MAX4298EUB ,Ultra-High PSRR Stereo Drivers + Microphone Amp + 100mA Linear Regulator
MAX4298EUB+ ,Ultra-High PSRR Stereo Drivers + Microphone Amp + 100mA Linear RegulatorApplications Ordering InformationNotebook and Desktop AudioPART TEMP. RANGE PIN-PACKAGEHands-Free H ..
MAX4298EUB+T ,Ultra-High PSRR Stereo Drivers + Microphone Amp + 100mA Linear Regulatorfeatures the stereo headphone driver only. The♦ 93dB typ PSRR at 20kHz Operates Directly fromMAX429 ..
MAX4304ESA ,Low-noise, low-distortion op amp. Bandwidth 740MHz. Minimum stable gain 2V/V.ELECTRICAL CHARACTERISTICS(V = +5V, V = -5V, V = 0, R = 100kΩ, T = T to T , unless otherwise noted. ..
MAX1600EAI-MAX1603EAI
Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks
General DescriptionThe MAX157/MAX159 low-power, 10-bit analog-to-digi-
tal converters (ADCs) are available in 8-pin µMAX and
DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD= +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the 0.2µA automatic shutdown further
reduces power consumption.
The MAX157 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX159 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™ compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and a small package size, make
these converters ideal for battery-powered and data
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 12-bit upgrades, see the
MAX144/MAX145 data sheet.
ApplicationsBattery-Powered SystemsInstrumentation
Portable Data LoggingTest Equipment
Isolated Data AcquisitionMedical Instruments
Process-Control MonitoringSystem Supervision
FeaturesSingle-Supply Operation (+2.7V to +5.25V)Two Single-Ended Channels (MAX157)
Single Pseudo-Differential Channel (MAX159)Low Power
0.9mA (at 108ksps, +3V)
100µA(at 10ksps, +3V)
10µA (at 1ksps, +3V)
<0.2µA (power-down mode)Internal Track/Hold108ksps Sampling RateSPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial InterfaceSpace-Saving 8-Pin µMAX PackagePin-Compatible 12-Bit Upgrades Available
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX19-1388; Rev 0; 11/98
Pin Configuration
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National SemiconductorCorp.*Contact factory for availability.
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND...................-0.3V to (VDD+ 0.3V)
REF to GND................................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND.............................................-0.3V to (VDD+ 0.3V)
DOUT Sink Current............................................................25mA
Continuous Power Dissipation (TA= +70°C)
µMAX (derate 4.1mW/°C above +70°C)......................330mW
Plastic DIP (derate 9.09mW/°C above +70°C)............727mW
CERDIP (derate 8.00mW/°C above +70°C).................640mW
Operating Temperature Ranges
MAX157/MAX159_C_A.......................................0°C to +70°C
MAX157/MAX159_E_A....................................-40°C to +85°C
MAX157/MAX159_MJA.................................-55°C to +125°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX157/MAX159
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS(Figure 7)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3:Offset nulled.
Note 4:The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from GND to VDD(MAX159 only).
Note 7:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8:Guaranteed by design. Not subject to production testing.
Note 9:Measured as VFS(2.7V) - VFS(5.25V).
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Typical Operating Characteristics(VDD= +3.0V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAXypical Operating Characteristics (continued)(VDD= +3.0V, VREF= 2.5V, 0.1µF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Detailed DescriptionThe MAX157/MAX159 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track/hold (T/H) structure
to convert an analog signal to a serial, 10-bit digital out-
put data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX157 (2 channels, single-ended) and the
MAX159 (1 channel, pseudo-differential).
Single-Ended (MAX157) and Pseudo-
Differential (MAX159) Analog InputsThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode (MAX157), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted, and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however the output
data will still contain the channel identification bit
(before the MSB).
For the MAX159, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
Figure 1. Load Circuits for Enable and Disable Time
Pin Description
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAXThe capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 10-bit
resolution. This action is equivalent to transferring a
16pF · [(VIN+) - (VIN-)] charge from CHOLDto the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/HoldThe ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX157 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX159
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”), and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLDcharges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ= 7(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN(9kΩ) is the input resistance, and CIN (16pF)is the
input capacitance of the ADC. Source impedances
below 4kΩhave no significant impact on the AC perfor-
mance of the MAX157/MAX159.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX157/MAX159 T/H stage offers both a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
makes it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous
or switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband re-
sponse.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within GND - 300mV to VDD+ 300mV without
damage. However, for accurate conversions both
inputs must not exceed VDD+ 50mV or be less than
GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.Figure 2. MAX157/MAX159 Simplified Functional Diagram
Figure 3. Analog Input Channel Structure
