MAX157ACUA+ ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAXELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V, V = 2.5V, 0.1μF capacitor at REF, f = 2.17MHz, 16 c ..
MAX157BCPA+ ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAXFeaturesThe MAX157/MAX159 low-power, 10-bit analog-to-digi-♦ Single-Supply Operation (+2.7V to +5.2 ..
MAX157BCUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin ?MAXFeaturesThe MAX157/MAX159 low-power, 10-bit analog-to-digi-' Single-Supply Operation (+2.7V to +5.2 ..
MAX157BCUA+ ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAXApplicationsMAX157ACUA 0°C to +70°C 8 μMAX ±0.5Battery-Powered Systems InstrumentationMAX157BCUA 0° ..
MAX157BEUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin ?MAXMAX157/MAX15919-1388; Rev 0; 11/98+2.7V, Low-Power, 2-Channel,108ksps, Serial 10-Bit ADCs in 8-Pin ..
MAX157BEUA+T ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAXapplications, or for other circuits withdemanding power-consumption and space require-Ordering Info ..
MAX4242ESA+T ,Single/Dual/Quad, +1.8V/10µA, SOT23, Beyond-the-Rails Op AmpsELECTRICAL CHARACTERISTICS (V = +1.8V to +5.5V, V = 0, V = 0, V = V / 2, R = 100kΩ tied to V / 2, S ..
MAX4242EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op Ampsapplications.PIN- SOT PART TEMP. RANGEThe MAX4240 is offered in a space-saving 5-pin SOT23 PACKAGE ..
MAX4242EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsGeneral Description ________
MAX4242EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsGeneral Description ________
MAX4242EUA+ ,Single/Dual/Quad, +1.8V/10µA, SOT23, Beyond-the-Rails Op AmpsApplicationsMAX4242EUA -40°C to +85°C 8 µMAX —Two-Cell Battery- Strain GaugesMAX4242ESA -40°C to +8 ..
MAX4242EUA+T ,Single/Dual/Quad, +1.8V/10µA, SOT23, Beyond-the-Rails Op AmpsFeaturesThe MAX4240–MAX4244 family of micropower op amps♦ Ultra-Low-Voltage Operation:operate from ..
MAX157ACUA+-MAX157BCPA+-MAX157BCUA+-MAX157BEUA+T
+2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
neral DescriptionThe MAX157/MAX159 low-power, 10-bit analog-to-digi-
tal converters (ADCs) are available in 8-pin μMAX and
DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4μs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5μs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD= +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the 0.2μA automatic shutdown further
reduces power consumption.
The MAX157 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX159 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™ compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and a small package size, make
these converters ideal for battery-powered and data
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 12-bit upgrades, see the
MAX144/MAX145 data sheet.
ApplicationsBattery-Powered SystemsInstrumentation
Portable Data LoggingTest Equipment
Isolated Data AcquisitionMedical Instruments
Process-Control MonitoringSystem Supervision
aturesSingle-Supply Operation (+2.7V to +5.25V)Two Single-Ended Channels (MAX157)
Single Pseudo-Differential Channel (MAX159)Low Power
0.9mA (at 108ksps, +3V)
100μA(at 10ksps, +3V)
10μA (at 1ksps, +3V)
<0.2μA (power-down mode)Internal Track/Hold108ksps Sampling RateSPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial InterfaceSpace-Saving 8-Pin μMAX PackagePin-Compatible 12-Bit Upgrades Available2.7V, Low-Power, 2-Channe08ksps, Serial 10-Bit ADCs in 8-Pin μMAXCS/SHDN
REFGND
SCLK
DOUT
( ) ARE FOR MAX159 ONLY.
CH0 (CH+)
CH1 (CH-)
VDD
μMAX/DIP
TOP VIEW
MAX157
MAX159
19-1388; Rev 0; 11/98
Pin Configuration
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National SemiconductorCorp.*Contact factory for availability.8 CERDIP*-55°C to +125°CMAX159BMJA
±0.58 CERDIP*-55°C to +125°CMAX159AMJA8 Plastic DIP-40°C to +85°CMAX159BEPA
±0.58 Plastic DIP-40°C to +85°CMAX159AEPA8 μMAX-40°C to +85°CMAX159BEUA
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
INL
(LSB)8 CERDIP*
8 CERDIP*
8 Plastic DIP-40°C to +85°C
-55°C to +125°C
-55°C to +125°CMAX157BMJA
MAX157AMJA
MAX157BEPA
8 Plastic DIP
8 μMAX-40°C to +85°C
-40°C to +85°CMAX157AEPA
MAX157BEUA
8 μMAX
8 Plastic DIP0°C to +70°C
-40°C to +85°CMAX159AEUA
MAX159BCPA
8 Plastic DIP
8 μMAX
8 μMAX0°C to +70°C
0°C to +70°C
0°C to +70°CMAX159ACPA
MAX159BCUA
MAX159ACUA8 μMAX
8 Plastic DIP0°C to +70°C
-40°C to +85°CMAX157AEUA
MAX157BCPA
8 Plastic DIP
8 μMAX
8 μMAX
PIN-
PACKAGE
TEMP.
RANGE0°C to +70°C
0°C to +70°C
0°C to +70°CMAX157ACPA
MAX157BCUA
MAX157ACUA
PART
.7V, Low-Power, 2-Channel,08ksps, Serial 10-Bit ADCs in 8-Pin μMAXABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND...................-0.3V to (VDD+ 0.3V)
REF to GND................................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND.............................................-0.3V to (VDD+ 0.3V)
DOUT Sink Current............................................................25mA
Continuous Power Dissipation (TA= +70°C)
μMAX (derate 4.1mW/°C above +70°C)......................330mW
Plastic DIP (derate 9.09mW/°C above +70°C)............727mW
CERDIP (derate 8.00mW/°C above +70°C).................640mW
Operating Temperature Ranges
MAX157/MAX159_C_A.......................................0°C to +70°C
MAX157/MAX159_E_A....................................-40°C to +85°C
MAX157/MAX159_MJA.................................-55°C to +125°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS(fIN (sine wave) = 10kHz, VIN= 2.5Vp-p, 108ksps, external fSCLK= 2.17MHz, CH- = GND for MAX159)
PARAMETERSYMBOLMINTYPMAXUNITSGain Error (Note 3)±2LSB
Offset Error±2LSB
Differential NonlinearityDNL±0.5LSB
Gain Temperature Coefficient±0.8ppm/°C
Channel-to-Channel Offset
Matching±0.02LSB
Channel-to-Channel Gain
Matching±0.02LSB
ResolutionRES10Bits
Relative Accuracy (Note 2)INL±0.5LSB
Signal-to-Noise Ratio plus
DistortionSINAD66dB
Total Harmonic Distortion
(including 5th-order harmonic)THD-70dB
Spurious-Free Dynamic RangeSFDR70dB
Channel-to-Channel Crosstalk-75dB
Small-Signal Bandwidth2.25MHz
Full-Power Bandwidth1.0MHz
CONDITIONSNo missing codes over temperature
MAX15_B
External reference, VREF= 2.5V
fIN= 65kHz, VIN= 2.5Vp-p (Note 4)
-3dB rolloff
MAX15_A
MHz
2.7V, Low-Power, 2-Channe08ksps, Serial 10-Bit ADCs in 8-Pin μMAX
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONVERSION RATE0.5ISINK= 16mA
Three-State Output Capacitance15pFCOUTCS/SHDN = VDD(Note 8)
Output High VoltageVDD- 0.5VVOH
Output Low Voltage0.4VVOLISINK= 5mA
ISOURCE= 0.5mA
Input Capacitance15pFCIN
Input Leakage Current±1μAIINVIN= 0 or VDD
(Note 8)
Input Hysteresis0.2VVHYS3.0VDD> 3.6V
Input Low Voltage0.8VIL
Input High Voltage2.0VIHVDD≤3.6V
Shutdown REF Input Current0.0110μA
Input Resistance1825kΩ
Input Current100140μAVREF= 2.5V
Input Voltage Range (Note 7)0 VDD + 50mVVVREF
Analog Input Voltage Range
(Note 6)0VREFVVIN
Input Capacitance16μACIN
Multiplexer Leakage Current±0.01 ±1μAOn/off-leakage current, VIN= 0 to VDD
Aperture Delay25ns
Aperture Jitter<50ps
Serial Clock Frequency0.12.17fSCLK05MHzExternal clock mode
Internal clock mode, for data transfer only
PARAMETERSYMBOLMINTYPMAXUNITS7.4μsConversion Time (Note 5)tCONV7
T/H Acquisition TimetACQ2.5μs
CONDITIONSExternal clock, fSCLK= 2.17MHz, 16 clock
cycles per conversion
Internal clock
Three-State Output Leakage
Current±10μACS/SHDN = VDD
CONVERSION RATE
ANALOG INPUTS
EXTERNAL REFERENCE
DIGITAL INPUTS (CS/SHDN, SCLK) AND DIGITAL OUTPUT (DOUT)
.7V, Low-Power, 2-Channel,08ksps, Serial 10-Bit ADCs in 8-Pin μMAXELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS(Figure 7)(VDD= +2.7V to +5.25V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1:Tested at VDD= +2.7V.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3:Offset nulled.
Note 4:The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5:Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from GND to VDD(MAX159 only).
Note 7:ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Note 8:Guaranteed by design. Not subject to production testing.
Note 9:Measured as VFS(2.7V) - VFS(5.25V).
PARAMETERSYMBOLMINTYPMAXUNITS5SCLK Clock FrequencyfSCLK0.12.17MHz
SCLK Fall to Output Data ValidtDO20120ns
CS/SHDNFall to Output Enable
Wake-Up Time tWAKE2.5μs
tDV120ns
CS/SHDN Rise to Output
DisabletTR120ns
SCLK Pulse Width HightCH50ns
CONDITIONSInternal clock, SCLK for data transfer only
(Note 8)
Internal clock, SCLK for data transfer only
External clock= 100pF
External clock= 100pF (Figure 1)
CL = 100pF (Figure 1)SCLK to CS/SHDN SetuptSCLKS60
CS/SHDN Pulse WidthtCS60ns
SCLK Pulse Width LowtCL50nsInternal clock, SCLK for data transfer only
(Note 8)
External clock
POWER REQUIREMENTSPower-Supply Rejection
(Note 9)PSR±0.15mVVDD= 2.7V to 5.25V, full-scale input
PARAMETERSYMBOLMINTYPMAXUNITSPositive Supply VoltageVDD+2.7+5.25V
CONDITIONSPositive Supply CurrentIDD0.92.0mAOperating mode
Positive Supply CurrentIDD0.25μAShutdown, CS/SHDN = GND
POWER REQUIREMENTS
2.7V, Low-Power, 2-Channe08ksps, Serial 10-Bit ADCs in 8-Pin μMAXSUPPLY CURRENT
vs. SUPPLY VOLTAGE
AX157/159 toc01
VDD (V)
(μ
VREF = VDD
RL = ∞
CL = 50pF
CODE = 1010101000
SUPPLY CURRENT
vs. TEMPERATURE
157/159 toc02
TEMPERATURE (°C)
(μ
VREF = VDD
RL = ∞
CL = 50pF
CODE = 1010101000
10,000
0.111001k10k10100k
SUPPLY CURRENT
vs. SAMPLING RATEAX157/159 toc03
SAMPLING RATE (sps)
(μ
1000
VREF = VDD
CODE = 1010101000
CL = 50pF
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
AX157/159 toc04
VDD (V)
(n
VREF = VDD
OFFSET ERROR vs. TEMPERATURE
AX157/159 toc07
TEMPERATURE (°C)
(L
SHUTDOWN CURRENT
vs. TEMPERATURE
AX157/159 toc05
TEMPERATURE (°C)
(n
VREF = VDD
OFFSET ERROR vs. SUPPLY VOLTAGE
157/159 toc06
VDD (V)
(L
Typical Operating Characteristic(VDD= +3.0V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
.7V, Low-Power, 2-Channel,08ksps, Serial 10-Bit ADCs in 8-Pin μMAXTypical Operating Characteristics (continued)(VDD= +3.0V, VREF= 2.5V, 0.1μF capacitor at REF, fSCLK= 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
GAIN ERROR
vs. SUPPLY VOLTAGE
AX157/159 toc08
VDD (V)
(L
GAIN ERROR
vs. TEMPERATURE
AX157/159 toc09
TEMPERATURE (°C)
(L
INTEGRAL NONLINEARITY
vs. TEMPERATURE
157/159 toc12
TEMPERATURE (°C)
(L
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
AX157/8 toc10
OUTPUT CODE
L (L
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
157/159 toc11
VDD (V)
(L
2.7V, Low-Power, 2-Channe08ksps, Serial 10-Bit ADCs in 8-Pin μMAXtailed DescriptionThe MAX157/MAX159 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track/hold (T/H) structure
to convert an analog signal to a serial, 10-bit digital out-
put data stream.
This flexible serial interface provides easy interface to
microprocessors (μPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX157 (2 channels, single-ended) and the
MAX159 (1 channel, pseudo-differential).
Single-Ended (MAX157) and Pseudo-
Differential (MAX159) Analog InputsThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode (MAX157), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted, and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however the output
data will still contain the channel identification bit
(before the MSB).
For the MAX159, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1μF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input. CL
DOUT
a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-ZDOUT
GNDGND
VDD
b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-ZFigure 1. Load Circuits for Enable and Disable Time
Pin Description
NAMEFUNCTIONVDDPositive Supply Voltage, +2.7V to +5.25VCH0 (CH+)Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+).
PINCH1 (CH-)Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-).GNDAnalog and Digital GroundSCLKSerial Clock Input. DOUT changes on the falling edge of SCLK.DOUTSerial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN is high.CS/SHDNActive-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into
shutdown with a maximum current of 5μA.REFExternal Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the
part.
.7V, Low-Power, 2-Channel,08ksps, Serial 10-Bit ADCs in 8-Pin μMAXThe capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 10-bit
resolution. This action is equivalent to transferring a
16pF · [(VIN+) - (VIN-)] charge from CHOLDto the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/HoldThe ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX157 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX159
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”), and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLDcharges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ= 7(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN(9kΩ) is the input resistance, and CIN (16pF)is the
input capacitance of the ADC. Source impedances
below 4kΩhave no significant impact on the AC perfor-
mance of the MAX157/MAX159.
Higher source impedances can be used if a 0.01μF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input BandwidthThe MAX157/MAX159 T/H stage offers both a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
makes it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous
or switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband re-
sponse.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within GND - 300mV to VDD+ 300mV without
damage. However, for accurate conversions both
inputs must not exceed VDD+ 50mV or be less than
GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.MAX157
MAX159
10+2 BIT
SAR
ADC
SCLKOUT
ANALOG
INPUT
MUX
(2 CHANNEL)
CH0
(CH+)
CH1
(CH-)
REF
( ) ARE FOR MAX159
T/H
CONTROL
LOGIC
SCLK
CS/SHDN
INTERNAL
CLOCK
OUTPUT
REGISTER
DOUT
Figure 2. MAX157/MAX159 Simplified Functional Diagram
CH0
(CH+)
CH1
(CH-)
GND
CSWITCH
TRACK
T/H
RIN
HOLD
CAPACITIVE DAC
CONTROL
LOGIC
REF
ZERO
TO SAR
( ) ARE FOR MAX159
COMPARATOR+
CHOLD
16pF
SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN-
DIFFERENTIAL MODE: CH+ = IN+; CH- = IN-
INPUT
MUX
Figure 3. Analog Input Channel Structure
