MAX1576ETG ,480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera FlashELECTRICAL CHARACTERISTICS (Voltages Referenced to V , T = – 40° to 130°C* unless otherwise indicat ..
MAX1576ETG+ ,480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera FlashELECTRICAL CHARACTERISTICS(V = 3.6V, V = V = V = 0V, ENM1 = ENM2 = ENF1 = ENF2 = IN, R = R = 6.8kΩ, ..
MAX1576ETG+T ,480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera FlashFeaturesThe MAX1576 charge pump drives up to 8 white LEDs♦ Powers Up to 8 LEDswith regulated consta ..
MAX1577ZETA+ ,1.2A White LED Regulating Charge Pump for Camera Flashes and Movie LightsApplicationsWhite LED Flashes, Strobes, and Movie LightsOrdering InformationLCD BacklightingPIN- TO ..
MAX1578ETG+ ,Complete Bias and White LED Power Supplies for Small TFT DisplaysFeatures♦ Four Regulators in One PackageThe MAX1578/MAX1579 provide four regulated outputsto meet a ..
MAX1578ETG+T ,Complete Bias and White LED Power Supplies for Small TFT DisplaysELECTRICAL CHARACTERISTICS(Circuit of Figure 3, V = 3V, CTRL = ONBIAS = IN, T = -40°C to +85°C, typ ..
MAX4240EUK-T ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsFeaturesThe MAX4240–MAX4244 family of micropower op amps' Ultra-Low-Voltage Operation:operate from ..
MAX4241ESA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsApplicationsMAX4242EUA -40°C to +85°C 8 µMAX —Two-Cell Battery- Strain GaugesMAX4242ESA -40°C to +8 ..
MAX4241EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op Ampsapplications.PIN- SOT PART TEMP. RANGEThe MAX4240 is offered in a space-saving 5-pin SOT23 PACKAGE ..
MAX4241EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsApplicationsMAX4242EUA -40°C to +85°C 8 µMAX —Two-Cell Battery- Strain GaugesMAX4242ESA -40°C to +8 ..
MAX4241EUA ,Single/Dual/Quad / !.8V/10A / SOT23 / Beyond-the-Rails Op AmpsELECTRICAL CHARACTERISTICS — T = +25°CA(V = +1.8V to +5.5V, V = 0, V = 0, V = V / 2, R = 100kΩ tied ..
MAX4241EUA+ ,Single/Dual/Quad, +1.8V/10µA, SOT23, Beyond-the-Rails Op AmpsELECTRICAL CHARACTERISTICS (V = +1.8V to +5.5V, V = 0, V = 0, V = V / 2, R = 100kΩ tied to V / 2, S ..
MAX1576ETG
480mA White LED 1x/1.5x/2x Charge Pump for Backlighting and Camera Flash
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14489BM u Iti-Character
lED Display/lamp Driver
CMOS
The MC144898 is a flexible light-emitting-diode driver which directly in-
terfaces to individual lamps, 7-segment displays, or various combinations of
both. LEOs wired with common cathodes are driven in a multiplexed-by-5
fashion. Communication with an MCUIMPU is established through a synchro-
nous serial port. The MC 144898 features data retention plus decode and scan
circuitry, thus relieving processor overhead. A single, current-setting resistor
is the only ancillary component required.
A single device can drive anyone of the following: a 5-digit display plus
decimals, a 4-112-digit display plus decimals and sign, or 25 lamps. A special
technique allows driving 5 112 digits; see Figure 16. A configuration register
allows the drive capability to be partitioned off to suit many additional applica-
tions. The on-chip decoder outputs 7-segment-format numerals O to 9, hexa-
decimal characters A to F, plus 151etters and symbols.
The MC144898 is compatible with the Motorola SPI and National MI-
CRO-WIRETM serial data ports. The chip's patented 8itGrabberTM registers
augment the serial interface by allowing random access without steering or
address bits. A 24-bit transfer updates the display register. Changing the con-
figuration register requires an 8-bit transfer.
.Operating Voltage Range of Drive Circuitry: 4.5 to 5.5 V
.Operating Junction Temperature Range: -40° to 130°C
.Current Sources Controlled by Single Resistor Provide Anode Drive
.Low-Resistance FET Switches Provide Direct Common Cathode Interface
.Low-Power Mode (Extinguishes the LEDs) and Brightness Controlled via
Serial Port
.Special Circuitry Minimizes EMI when Display is Driven and Eliminates EMI
in Low-Power Mode
.Power-On Reset (POR) Blanks the Display on Power-Up, Independent of
Supply Ramp Up Time
.May Be Used with Double-Heterojunction LEDs for Optimum Efficiency
.Chip Complexity: 4300 Elements (FETs, Resistors, Capacitors, etc.)
BitGrabber is a trademark of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
REVO
BLOCK DIAGRAMDATA OUT
DATA INdefgh
CLOCK
ENABLE
BANK 1BANK 2BANK 3BANK 4BANK 5
PIN 3 = VDD
PIN 14 = VSS
MAXIMUM RATINGS* (Voltages Referenced to VSS)ÁÁÁÁ
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ÁÁÁMaximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and Vout should be constrained to the range
VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an ap-
propriate logic voltage level (e.g., either VSS or
VDD). Unused outputs must be left open.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TJ = – 40° to 130°C* unless otherwise indicated)See Thermal Considerations section.
AC ELECTRICAL CHARACTERISTICS (TJ = – 40° to 130°C*, CL = 50 pF, Input tr = tf = 10 ns)See Thermal Considerations section.
TIMING REQUIREMENTS (TJ = – 40° to 130°C*, Input tr = tf = 10 ns unless otherwise indicated)*See Thermal Considerations section.
**For a high–speed 8–Clock access, th for Enable is determined as follows:
VDD = 3 to 4.5 V, fclk > 1.78 MHz: th = 4350 – (7500/fclk)
VDD = 4.5 to 5.5 V, fclk > 2.34 MHz: th = 3300 – (7500/fclk)
where th is in ns and fclk is in MHz.
NOTES:This restriction does NOT apply for fclk rates less than those listed above. For “slow” fclk rates, use the th limits in the above table.This restriction does NOT apply for an access involving more than 8 Clocks. For > 8 Clocks, use the th limits in the above table.
Figure 1. Figure 2. VDD
1/fclk
DATA OUT
CLOCK
10%
tPLHtPHL
tTLHtTHLtwtr
BANK
OUTPUT
1/fR
VSS
Figure 3. Figure 4. DATA IN
CLOCK
VALID
50%
tsuth
VDD
VDD
CLOCK
ENABLE
tsu
FIRST
CLOCK
LAST
CLOCK
trec
50%
VDD
VDD
tw(H)tw(L)
VSS
VSS
VSS
VSS
Figure 5. Figure 6. TEST POINT*
*Includes all probe and fixture capacitance.
TEST POINT*
*Includes all probe and fixture capacitance.
VDD
