MAX155BEPI+ ,High-Speed, 8-Channel, 8-Bit ADC with Simultaneous Track/Holds and ReferenceApplicationsdata-acquisition system.● Phase-Sensitive Data Acquisition When operating from a single ..
MAX155BEWI ,8-/4-Channel ADCs with Simultaneous T/Hs and ReferenceELECTRICAL CHARACTERISTICS
(VDD = +5V, REFIN = +2.5V, External Reference, AGND = DGND = 0V, Vss ..
MAX155BEWI-T ,High-Speed, 8-Channel, 8-Bit ADC with Simultaneous Track/Holds and ReferenceFeaturesThe MAX155/MAX156 are high-speed, 8-bit, multichan- ● 8 Simultaneously Sampling Track/Hold ..
MAX1561ETA ,High-Efficiency / 26V Step-Up Converters for Two to Six White LEDsApplicationsTOPPART TEMP RANGE PIN-PACKAGECell Phones and Smart PhonesMARKPDAs, Palmtops, and Wirel ..
MAX1561ETA+ ,High-Efficiency, 26V Step-Up Converters for Two to Six White LEDsMAX1561/MAX159919-2731; Rev 1; 10/03High-Efficiency, 26V Step-Up Convertersfor Tw o to Six White LE ..
MAX1561ETA+T ,High-Efficiency, 26V Step-Up Converters for Two to Six White LEDsFeaturesThe MAX1561/MAX1599 step-up converters drive up to ♦ Accurate Current Regulation for Unifor ..
MAX421EWE ,±15V Chopper Stabilized Op AmpsELECTRICAL CHARACTERISTICS MAX420, MAX421
( + 2 +15V, V- = -15V, TA = +25°C1Testcircuitunless no ..
MAX4220EEE ,Miniature, 300MHz, Single-Supply, Rail-to-Rail Op Amps with Enableapplications).' Low Differential Gain/Phase: 0.02%/0.02°These devices require only 5.5mA of quiesce ..
MAX4220ESD ,Miniature, 300MHz, Single-Supply, Rail-to-Rail Op Amps with EnableMAX4212/MAX4213/MAX4216/MAX4218/MAX422019-1178; Rev 1; 6/98Miniature, 300MHz, Single-Supply, Rail-t ..
MAX4221CSE ,330MHz Buffered Video Switches/ Crosspoint Building BlocksFeaturesThe MAX4111/MAX4121/MAX4221 wideband video' -3dB Bandwidth of 330MHzswitches are optimized ..
MAX4221CSE ,330MHz Buffered Video Switches/ Crosspoint Building BlocksMAX4111/MAX4121/MAX422119-0402; Rev 0; 6/95330MHz Buffered Video Switches/Crosspoint Building Block ..
MAX4221CSE+ ,330MHz Buffered Video Switches Crosspoint Building BlocksApplicationsMAX4221CSE 0°C to +70°C 16 Narrow SOVideo-Router and Crosspoint ArraysBroadcast/HDTV-Qu ..
MAX155ACPI+-MAX155ACWI+-MAX155AEPI+-MAX155AEWI+-MAX155BCPI+-MAX155BEPI+-MAX155BEWI-T-MAX156AEWI+-MAX156BCNG+-MAX156BCWI+
High-Speed, 8-Channel, 8-Bit ADC with Simultaneous Track/Holds and Reference
General DescriptionThe MAX155/MAX156 are high-speed, 8-bit, multichan-
nel analog-to-digital converters (ADCs) with simultaneous
track/holds (T/Hs) to eliminate timing differences between
input channel samples. The MAX155 has 8 analog input
channels and the MAX156 has 4 analog input channels.
Each channel has its own T/H, and all T/Hs sample at the
same instant. The ADC converts a channel in 3.6µs and
stores the result in an internal 8x8 RAM. The MAX155/
MAX156 also feature a 2.5V internal reference and
power-down capability, providing a complete, sampling
data-acquisition system.
When operating from a single +5V supply, the MAX155/
MAX156 perform either unipolar or bipolar, single-ended
or differential conversions. For applications requiring
wider dynamic range or bipolar conversions around
ground, the VSS supply pin may be connected to -5V.
Conversions are initiated with a pulse to the WR pin, and data
is accessed from the ADC’s RAM with a pulse to the RD pin.
A bidirectional interface updates the channel configuration
and provides output data. The ADC may also be wired for
output-only operation.The MAX155 comes in 28-pin PDIP
and wide SO packages, and the MAX156 comes in 24-pin
narrow PDIP and 28-pin wide SO packages.
Features●8 Simultaneously Sampling Track/Hold Inputs●3.6µs Conversion Time Per Channel●Unipolar or Bipolar Input Range●Single-Ended or Differential Inputs●Mixed Input Configurations Possible●2.5V Internal Reference●Single +5V or Dual ±5V Supply Operation
Applications●Phase-Sensitive Data Acquisition ●Vibration and Waveform Analysis●DSP Analog Input●AC Power Meters ●Portable Data Loggers
Ordering Information appears at end of data sheet.For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX155.related.
AIN0
AIN1
T/H
8-BIT
A/D
3.6µs2.5V
VREF8
8 x 8
RAM
CONTROL
LOGIC
THREE-
STATE
BUFFER
T/H
AIN2T/H
AIN3T/H
AIN4T/H
AIN5T/H
AIN6T/H
AIN7T/H8
MODE
CLK
REFIN
REFOUT
8-BIT
DATA
BUS
MAX155
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Functional Diagram
EVALUATION KIT AVAILABLE
VDD to AGND .............................................................-0.3V, +6V
VDD to DGND .............................................................-0.3V, +6V
AGND to DGND ...........................................-0.3V, (VDD + 0.3V)
VSS to AGND..............................................................+0.3V, -6V
VSS to DGND .............................................................+0.3V, -6V
CS, WR, RD, CLK, MODE to DGND ...........-0.3V, (VDD + 0 3V)
BUSY, D0–D7 to DGND ...............................-0.3V, (VDD + 0 3V)
REFOUT to AGND .......................................-0.3V, (VDD + 0 3V)
REFIN to AGND ...........................................-0.3V, (VDD + 0 3V)
AIN to AGND ....................................(VSS - 0.3V), (VDD + 0 3V)
Output Current (REFOUT) .................................................30mA
Continuous Power Dissipation (TA = +70°C)
24-Pin PDIP (derate 8.7mW/°C above +70°C) ............696mW
28-Pin PDIP (derate 9.09mW/°C above +70°C) ..........727mW
28-Pin Wide SO (derate 12.5mW/°C above +70°C) ..1000mW
Operating Temperature Ranges:
MAX155/MAX156_C_ _ ......................................0°C to +70°C
MAX155/MAX156_E_ _ ..................................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(VDD = +5V, VREFIN = +2.5V. External Reference, VAGND = VDGND = 0V, VSS = 0V or -5V, fCLK = 5MHz external, Unipolar range
single-ended mode, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ACCURACY (Note 1)Resolution8Bits
Integral Linearity Error
MAX15_A±½
LSBMAX15_B±1
No Missing Codes ResolutionGuaranteed monotonic8Bits
Offset Error (Unipolar)MAX15_A±½LSBMAX15_B±1
Offset Error (Bipolar)
MAX15_A±1
LSBMAX15_B±2
Gain Error
UnipolarMAX15_A±1
LSBMAX15_B±1
BipolarMAX15_A±1
MAX15_B±2
Channel-to-Channel MatchingMAX15_A±½LSBMAX15_B±1
DYNAMIC PERFORMANCE (VIN = 50kHz, 2.5VP-P sine wave sampled at 220ksps)Signal-to-Noise and Distortion
RatioSINADMAX15_A48dBMAX15_B47
Total Harmonic DistortionTHD-60dB
Spurious-Free Dynamic RangeSFDR-62dB
Small-Signal Bandwidth4MHz
Aperture Delay20ns
Aperture Delay Matching (Note 2)4ns
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDD = +5V, VREFIN = +2.5V. External Reference, VAGND = VDGND = 0V, VSS = 0V or -5V, fCLK = 5MHz external, Unipolar range
single-ended mode, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG INPUTVoltage Range, Unipolar, Single-
EndedAIN_(+) to AGND0VREF
Unipolar DifferentialAIN_(+) to AIN_(-)0VREF
Bipolar, Single-EndedAIN_(+) to AGND-VREFVREF
Bipolar, DifferentialAIN_(+) to AIN_(-)-VREFVREF
Common-Mode RangeDifferential modeVSSVDD
DC Input ImpedanceAIN = VDD10MΩ
REFERENCE INPUTREFIN Range (For Speciied
Performance) (Note 2)2.3752.5002.625V
IREFVREFIN = 2.5V1mA
REFERENCE OUTPUT (CL = 4.7µF)Output Voltage IL = 0mA
TA = +25°C2.442.502.56TA = TMIN to
TMAX2.382.502.62
Load RegulationTA = +25°C, IOUT = 0 to 10mA-10mV
Power-Supply SensitivityTA = +25°C, VDD = 5V ±5%±1±3mV
Temperature Drift±100ppm/°C
LOGIC INPUTS (Mode = Open Circuit)CS, RD, WR, CLK, D0–D7 (When
Inputs) Input Low VoltageVIL0.8V
Input High VoltageVIH2.4V
Input CurrentIIN±10µA
Input Capacitance (Note 2)CIN15pF
MODEInput Low VoltageVIL0.5V
Input High VoltageVIHVDD -
0.5V
Input Midlevel VoltageVMIDVDD/2
- 0.5
VDD/2
+ 0.5V
Input Floating VoltageVFLTVDD/2V
Input CurrentIIN±50±100µA
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Electrical Characteristics (continued)
(VDD = +5V, VREFIN = +2.5V. External Reference, VAGND = VDGND = 0V, VSS = 0V or -5V, fCLK = 5MHz external, Unipolar range
single-ended mode, TA = TMIN to TMAX, unless otherwise noted.)
(VDD = +5V, VREFIN = +2.5V. External Reference, VAGND = VDGND = 0V, VSS = 0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOGIC OUTPUTSBUSY, D0–D7 Output Low VoltageVOLIOUT = 1.6mA0.4V
Output High VoltageVOHIOUT = -360µA4V
D0–D7 Floating State Leakage±10µA
Floating State Output Capacitance
(Note 2)COUT15pF
Conversion TimefCLK = 5MHz, single channel3.63.8µs
POWER REQUIREMENTSPositive Power-Supply VoltageVDD4.755.25V
Positive Power-Supply CurrentIDD
PD = 0MAX1551824mA
MAX156912
PD = 1
CLK, CS, WR,
RD = 0V or VDD;
DOUT = 0V or
VDD100µA
Negative Power-Supply VoltageVSS0-5V
Negative Power-Supply CurrentISSPD = 0250µA
PD = 1250
Power-Supply Rejection (Change
in Full-Scale Error)
VDD = 5V ±5%, VSS = 0V±0.1±0.25LSBVDD = 5V, VSS = -5V ±5%±0.1
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCS to WR Setup TimetCWS0ns
CS to WR Hold TimetCWH0ns
CS to RD Setup TimetCRS0ns
CS to RD Hold Time (Note 2)tCRH0ns
WR Low Pulse WidthtWRMAX15_C/E1002000ns
RD Low Pulse WidthtRDLMAX15_C/E100ns
RD High Pulse Width (Note 2)tRDHMAX15_C/E180ns
WR to RD Delay (Note 2)tWRDMAX15_C/E280ns
WR to BUSY Low DelaytWBDMAX15_C/E220ns
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
TIMING CHARACTERISTICS (Note 3, Figures 1–7)
Electrical Characteristics (continued)
Note 1: VDD = +5V, VREFIN = +2.5V, VSS = 0V. Performance at ±5% power-supply tolerance is guaranteed by Power-Supply
Rejection test.
Note 2: Guaranteed by design, not production tested.
Note 3: All input control signals are specified with tr = tf = 20ns (10% to 90% of +5V) and timed from a +1.6V voltage level. Output
signals are timed from VOH and VOL.
Note 4: tDV is the time required for an output to cross +0.8V or +2.4V measured with load circuit of Figure 1.
Note 5: tTR is the time required for the data lines to change 0.5V, measured with load circuits of Figure 2.
Figure 1. Load Circuits for Data-Access TimingFigure 2. Load Circuits for Three-State Output Timing
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBUSY High to WR Delay (to update coniguration register) (Notes 2, 3)tBWD50ns
CLK to WR Delay (Acquisition Time)
(Note 2)tACQ800ns
BUSY High to RD Delay (Notes 2, 3)tBRD50ns
Address-Setup TimetAS120ns
Address-Hold TimetAH0ns
RD to Data Valid (Note 4)tDVMAX15_C/E100ns
RD to Data Three-State Output (Note 5)tTRMAX15_C/E80ns
CLK to BUSY Delay (Note 2)tCB100300ns
CLK Frequency0.55.0MHz
3kΩ
3kΩ
DGND
HIGH-Z TO VOH
100pF
+5V
HIGH-Z TO VOL
100pF
DGND
3kΩ
3kΩ
VOH TO HIGH-Z
10pF
+5V
VOL TO HIGH-Z
10pF
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
TIMING CHARACTERISTICS (Note 3, Figures 1-7) (continued)(VDD = +5V, VREFIN = +2.5V. External Reference, VAGND = VDGND = 0V, VSS = 0V or -5V, TA = TMIN to TMAX, unless otherwise noted.)
Figure 3. Write and Read Timing
tCWS
tWR
tWBDtCONV
tBRD
tBWD
tACQ
tRDLtRDHtRDL
tWRD
tCWHtCRStCRHtCRStCRH
tCRS
DATA INDATA OUTDATA OUT
tAH
tAS
tDVtDVttRttR
BUSY
D0–D7
MODE
VSSAGND
AIN1
AIN0AIN3
VDD
AIN2
PDIPTOP VIEW
BUSYD1/A1REFOUT
D0/A0
REFIN
CLKD2916
D7/ALLD3/PD1015
D6/DIFFD4/INH1114
DGNDD5/BIP1213
MAX156AIN3
N.C.AIN0
AIN2
N.C.AIN1
N.C.
N.C
WIDE SOAGND
REFINCS24VDDMODE
VSS6
REFOUTRD821
D0/A0WR920
D1/A1BUSY1019CLK1118
D3/PDD7/ALL1217
D4/INHD6/DIFF1316
D5/BIPDGND1415
MAX156AIN1
AIN0AIN7
AIN3
AIN2AIN5
AIN6
AIN4
PDIP/SOREFOUT
MODE
VSSAGND
REFIN
VDDD0/A0920
BUSYD1/A11019
CLKD2/A21118
D7/ALL
D6/DIFF
DGND
D3/PD
D4/INH
D5/BIP171615
MAX155MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Pin Coniguration
PIN
NAMEFUNCTIONMAX155MAX156
PDIP/SOPDIPSO2326AIN3Sampling Analog Input, Channel 32428AIN2Sampling Analog Input, Channel 212AIN1Sampling Analog Input, Channel 124AIN0Sampling Analog Input, Channel 035MODEMode conigures multiplexer and converter. See Table 4.46VSSNegative Supply. Power VSS with -5V for extended input range.57CSCHIP SELECT Input must be low for the ADC to recognize RD, or WR68RDREAD Input reads data sequentially from RAM79WRWRITE Input’s rising edge initiates conversion and updates channel coniguration
register. Falling edge samples inputs.810BUSYBUSY Output low when conversion is in progress911CLKExternal Clock Input1012D7/ALLThree-State Data Output Bit 7 (MSB)/Sequential or Speciic Conversion1113D6/DIFFThree-State Data Output Bit 6/Single-Ended/Differential Select1214DGNDDigital Ground1315D5/BIPThree-State Data Output Bit 5/Unipolar/Bipolar Conversion1416D4/INHThree-State Data Output Bit 4/Inhibit Conversion Input1517D3/PDThree-State Data Output Bit 3/Power-Down Input1618D2/A2Three-State Data Output Bit 2/RAM Address Bit A2 (MAX155 Only)1719D1/A1Three-State Data Output Bit 1/RAM Address Bit A11820D0/A0Three-State Data Output Bit 0/RAM Address Bit A01921REFOUTReference Output, +2.5V2022REFINReference Input, +2.5 Normally2123AGNDAnalog Ground2224VDDPower-Supply Voltage, +5V Normally
25–28——AIN7–4Sampling Analog Input, Channels 7–4—1, 3,
25, 27N.C.No Connection. No internal connection—pin unconnected.
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Pin Description
Detailed Description
ADC OperationThe MAX155/MAX156 contain a 3.6µs successive approx-
imation ADC and 8/4 track-and-hold (T/H) inputs. When a
conversion is started, all AIN inputs are simultaneously
sampled. All channels sample whether or not they are
selected for the conversion. Either a single-channel or
multichannel conversion may be requested and channel
configurations may be mixed, ADC results are then stored
in an internal RAM.
In hard-wired mode (see the Multiplexer and AID
Configurations section) multichannel conversions are
initiated with one write operation. In input/output (I/O)
mode, multichannel configurations are set up prior to the
conversion by loading channel selections into the con-
figuration register. This register also selects single-ended/
differential, unipolar/bipolar (Figure 9), power-down, and
other functions. Each channel selection requires a sepa-
rate write operation (i.e. 8 writes for 8 channels), but only
after power-up. Once the desired channel arrangement
is loaded, each subsequent write converts all selected
channels without reconfiguring the multiplexer (mux). I/O
mode requires more write operations, but provides more
flexibility than hard-wired mode.
To access conversion results, successive RD pulses auto-
matically sence through RAM, beginning with channel 0.
Each RD pulse increments the RAM address counter,
which resets to 0 when WR goes low in multi channel
conversions. An arbitrary RAM location may also be read
by writing a 1 to INH while loading the RAM address (A0–
A2), and then performing a read operation.
Table 1. Multiplexer Configurations•Configuration inputs are shared with data outputs D0-D7. The functions of D0-D7 are not described in this table.
••DIFF and BIP are not implemented on the current conversion, but go into effect on the.following conversion.
PINNAMEFUNCTIOND0/A0
D1/A1
D2/A2
1 or 0A0–A2 select a multiple channel for the conigurations described below, or select a RAM address
for reading with a subsequent RD.
D3/PDNormal ADC operationPower-down reduces the power-supply current. Coniguration data may be loaded and is
maintained during power-down.
D4/INHA conversion starts when WR goes highInhibits the conversion when WR goes high. Allows mux coniguration to be loaded and RAM
locations to be accessed without starting a conversion.
D5/BIP**0Unipolar conversion (Figure 9a) for the channel speciied by A0–A2. Input range = 0V to VREF.Bipolar conversion (Figure 9b) for the channel speciied by A0–A2. Input range = ±VREF.
D6/DIFF**0Single-ended coniguration for the channel speciied by A0–A2 as described in Table 2Differential contiguration for the channel speciied by A0–A2 as described in Table 2
D7/ALLAll previously conigured channels are converted. Data is read with consecutive RD pulses, beginning with the lowest conigured channel.Only the channel speciied by A2–A0 is converted. A single RD pulse reads the result of that
conversion.
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Multiplexer and A/D ConigurationA conversion is started with a WR pulse. All channels
sample on WR’s falling edge. Mux configuration data is
loaded on WR’s rising edge. In I/O mode (MODE = Open
Circuit), selections for channel number, single or multi-
channel conversion, unipolar or bipolar input, and single-
ended or differential input are made with A0-A2, ALL, BIP,
and DIFF (Table 1). These input pins are also shared with
the RAM data outputs D0–D7. An alternate, simpler inter-
face is provided by the hard-wired mode, which selects
some general mux configurations without requiring ADC
programming. Hard-wired connections of MODE and VSS
select from 4 mux configurations as listed in Table 4 (see the
Hard-Wired Mode section).
On the rising edge of WR, the mux configuration register
is updated; falling edge initiates sampling of all inputs.
A channel selection can be implemented on the current
conversion, but changes from unipolar to bipolar (with
BIP) or from single ended to differential operation (with
DIFF) do not go into effect until the following WR. This can
be overcome by writing to the configuration register while
inhibiting the conversion (INH = 1), or by changing DIFF
and BIP one conversion early, i.e. on the previous write.
Table 2. Single-Ended Channel Selection (MODE = Open Circuit)
Table 3. Differential Channel Selection (MODE = Open Circuit)
Note: Shaded areas represent MAX156 operation.
Note: Shaded areas represent MAX156 operation.
MUX ADDRESSSINGLE-ENDED CHANNEL SELECTIONA1A2DIFF01234567AGND000+-000+-100+-100+-010+-010+-110+-110+-
MUX ADDRESSDIFFERENTIAL CHANNEL SELECTIONA1A2DIFF01234567001+-101+-011+-111+-001-+101-+011-+111-+
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
Interface Timing
Input/Output Mode, Multichannel Conversion
Timing I/O mode is selected when the MODE input is open
circuit. In I/O mode, the mux configuration register deter-
mines the conversion type. The register is updated on the
rising edge of WR.
Table 1 lists all conversion options. For example, at
D6/DIFF, a logic 0 or 1 selects a single-ended or differen-
tial conversion. Data is loaded into addressed locations
in the configuration register with a series of WR pulses.
If INH is high while writing, no conversion takes place. A
conversion is started by writing INH = 0 to the configura-
tion register. When a change is made to the contents of
the configuration register, a “dummy” conversion may be
necessary. This is due to a built-in latency of one full con-
version for unipolar/bipolar and single-ended/differential
selections.
It is not necessary to update the configuration register
before every conversion. A particular mux configuration
must be loaded only once after power-up (but the con-
figuration may require several writes to be loaded). A
mux configuration is retained for successive conversions
and during power-down (PD = 1) so that reconfiguring is
unnecessary when the ADC returns to normal operation
(PD = 0). Configuration and RAM data is lost only when
power is removed from the ADC at VDD.
When updating the configuration register, INH should be
high for all except the last WR so the conversion is not
started until the mux is set. On WR’s falling edge, all input
channels sample simultaneously. BUSY goes low at the
beginning of the conversion, and channels are converted
sequentially starting with the lowest selected channel.
When BUSY goes high, conversion results are stored
in RAM. At conversion end, a microprocessor (µP) can
access the RAM contents with consecutive RD pulses.
The first accessed data is the lowest channel’s result.
Subsequent RD pulses access conversion results for the
remaining channels.
The configuration data determines which RAM locations
are sequentially read by consecutive RD pulses, so new
data should be placed in the configuration register only
after a full RD operation. It is not necessary to update the
configuration register for every conversion. A new conver-
sion is initiated with a WR pulse (when INH = 0), regard-
less of the number of channe ls that have been read.
Figure 4a shows the MAX155 timing for an 8-channel
unipolar configuration. 8 channels are configured and
8 consecutive RD pulses access data. Figure 4b illus-
trates 4-channel differential conversion timing involving
4 sampled channels and 4 RD pulses. In cases where
conflicting differential configurations are loaded, the last
channel selected with DIFF = 1 will be the positive input
of the differential channel.
Input/Output Mode, Single-Channel Conver-
sion TimingFigure 5a shows timing for a single-channel (ALL = 1),
single-ended conversion; Figure 5b shows a differential
conversion. With MODE floating, the configuration reg-
ister is updated on the rising edge of WR. BUSY goes
low at the beginning of the conversion and returns high
when the channel designated by the configuration reg-
ister has been converted. All channels are sampled on
the falling edge of WR even if only a single channel has
been requested. At conversion end, the µP can read the
result for the selected channel with a single RD pulse.
Subsequent RD pulses will access old conversion results
remaining in other RAM locations. The next conversion
is initiated with a WR pulse, regardless of the number of
channels that have been read.
INH and A0–A2, in the configuration register, access loca-
tions in RAM. INH = 1 allows the RAM address pointer to
be updated without starting a conversion. A READ pulse
then reads the contents of the addressed location.
MAX155/MAX1568-/4-Channel ADCs with Simultaneous
T/Hs and Reference
