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MAX1544ETL+-MAX1544ETL+T-MAX1544ETL-T
Dual-Phase, Quick-PWM Controller for AMD Hammer CPU Core Power Supplies
General DescriptionThe MAX1544 is a dual-phase, Quick-PWM™, step-
down controller for AMD Hammer™ CPU core supplies.
Dual-phase operation reduces input ripple current
requirements and output voltage ripple while easing
component selection and layout difficulties. The Quick-
PWM control scheme provides instantaneous response
to fast load-current steps. The MAX1544 includes active
voltage positioning with adjustable gain and offset,
reducing power dissipation and bulk output capacitance
requirements.
The MAX1544 is intended for two different notebook CPU
core applications: stepping down the battery directly or
stepping down the 5V system supply to create the core
voltage. The single-stage conversion method allows this
device to directly step down high-voltage batteries for the
highest possible efficiency. Alternatively, two-stage con-
version (stepping down the 5V system supply instead of
the battery) at a higher switching frequency provides the
minimum possible physical size.
The MAX1544 complies with AMD’s desktop and
mobile CPU specifications. The switching regulator fea-
tures soft-start and power-up sequencing, and
soft-shutdown. The MAX1544 also features indepen-
dent four-level logic inputs for setting the suspend volt-
age (S0–S1).
The MAX1544 includes output undervoltage protection,
thermal protection, and voltage regulator power-OK
(VROK) output. When any of these protection features
detect a fault, the controller shuts down. Additionally, the
MAX1544 includes selectable overvoltage protection.
The MAX1544 is available in a low-profile, 40-pin 6mm
x 6mm thin QFN package. For other CPU platforms,
refer to the pin-to-pin compatible MAX1519/MAX1545
and MAX1532/MAX1546/MAX1547 data sheets.
ApplicationsAMD Hammer Desktop or Notebook PCs
Multiphase CPU Core Supply
Voltage-Positioned Step-Down Converters
Servers/Desktop Computers
FeaturesDual-Phase, Quick-PWM Controller±0.75% VOUTAccuracy Over Line, Load, and
Temperature (1.3V)Active Voltage Positioning with Adjustable Gain
and Offset5-Bit On-Board DAC: 0.675V to 1.55V Output
Adjust RangeSelectable 100kHz/200kHz/300kHz/550kHz
Switching Frequency4V to 28V Battery Input Voltage RangeAdjustable Slew-Rate ControlDrives Large Synchronous Rectifier MOSFETsSelectable Output Overvoltage ProtectionUndervoltage and Thermal-Fault ProtectionPower Sequencing and TimingSelectable Suspend VoltageSoft-ShutdownSelectable Single- or Dual-Phase Pulse Skipping
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power SuppliesVDD
DLM
LXM
BSTM
VROK
DHMSUS
OFS
REF
ILIM
VCC
TON
TIME1121314151617181920393837363534333231
OAIN-
OAIN+
OVP
CCI
GNDS
CCV
GND
CSNCMNCMPV+BSTSLXSDHSDLSPGNDCSP
THIN QFNMAX1544
TOP VIEW
SHDN
SKIP
Pin Configuration
Ordering Information19-2745; Rev 1; 9/03
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGEMAX1544ETL-40°C to +100°C40 Thin QFN 6mm ✕ 6mm
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
Hammer is a trademark of AMD.
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND..............................................................-0.3V to +30V
VCCto GND..............................................................-0.3V to +6V
VDDto PGND............................................................-0.3V to +6V
SKIP, SUS, D0–D4 to GND.......................................-0.3V to +6V
ILIM, FB, OFS, CCV, CCI, REF, OAIN+,
OAIN- to GND.........................................-0.3V to (VCC+ 0.3V)
CMP, CSP, CMN, CSN, GNDS to GND......-0.3V to (VCC+ 0.3V)
TON, TIME, VROK, S0–S1, OVP to GND....-0.3V to (VCC+ 0.3V)
SHDNto GND (Note 1)...........................................-0.3V to +18V
DLM, DLS to PGND....................................-0.3V to (VDD+ 0.3V)
BSTM, BSTS to GND..............................................-0.3V to +36V
DHM to LXM...........................................-0.3V to (VBSTM+ 0.3V)
LXM to BSTM............................................................-6V to +0.3V
DHS to LXS..............................................-0.3V to (VBSTS+ 0.3V)
LXS to BSTS.............................................................-6V to +0.3V
GND to PGND.......................................................-0.3V to +0.3V
REF Short-Circuit Duration.........................................Continuous
Continuous Power Dissipation (TA= +70°C)
40-Pin 6mm ✕6mm Thin QFN
(derate 23.2mW/°C above +70°C)...............................1.860W
Operating Temperature Range.........................-40°C to +100°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
PWM CONTROLLERBattery voltage, V+428Input Voltage RangeVCC, VDD4.55.5V
DAC codes ≥ 1V-10+10
DC Output Voltage Accuracy
(Note 2)
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.60V to 1V-15+15mV
Line Regulation ErrorVCC = 4.5V to 5.5V, V+ = 4.5V to 28V5mV
IFB, IGNDSFB, GNDS-2+2Input Bias CurrentIOFSOFS-0.1+0.1µA
OFS Input Range02V
ΔVOUT/ΔVOFS;ΔVOFS = VOFS, VOFS = 0 to 1V-0.129-0.125-0.117
OFS GainAOFSΔVOUT/ΔVOFS;
ΔVOFS = VOFS-VREF, VOFS = 1V to 2V-0.129-0.125-0.117
V/V
GNDS Input Range-20+200mV
GNDS GainAGNDSΔVOUT/ΔVGNDS0.970.991.01V/V
1000kHz nominal, RTIME = 15kΩ90010001100
500kHz nominal, RTIME = 30kΩ460500540
250kHz nominal, RTIME = 60kΩ225250275TIME Frequency AccuracyfTIME
Shutdown, RTIME = 30kΩ125
kHz
Note 1:SHDNmay be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables
fault protection and overlapping operation.
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSTON = GND
(550kHz)155180205
TON = REF
(300kHz)320355390
TON = open
(200kHz)475525575
On-Time (Note 3)tONV+ = 12V,
VFB = VCCI = 1.2V
TON = VCC
(100kHz)92010001140
TON = GND300375Minimum Off-Time (Note 3)tOFF(MIN)TON = VCC, open, or REF400480ns
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point, OAIN- = FB, V OAI N + = 1.3V 1.703.20mA
Quiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation point<15µA
Quiescent Battery Supply Current
(V+)IV+Measured at V+2540µA
Shutdown Supply Current (VCC)Measured at VCC, SHDN = GND410µA
Shutdown Supply Current (VDD)Measured at VDD, SHDN = GND<15µA
Shutdown Battery Supply Current
(V+)
Measured at V+, SHDN = GND,
VCC = VDD = 0 or 5V<15µA
Reference VoltageVREFVCC = 4.5V to 5.5V, IREF = 01.9902.0002.010V
Reference Load RegulationΔVREFIREF = -10µA to 100µA-10+10mV
FAULT PROTECTIONSKIP = VCC, measured at FB with respect
to unloaded output voltage131619%Output Overvoltage Protection
ThresholdVOVP
SKIP = REF or GND2.00V
Output Overvoltage Propagation
DelaytOVPFB forced 2% above trip threshold10µs
Output Undervoltage Protection
ThresholdVUVPMeasured at FB with respect to unloaded
output voltage677073%
Output Undervoltage Propagation
DelaytUVPFB forced 2% below trip threshold10µs
Lower threshold
(undervoltage)-12-10-8
VROK Threshold
Measured at FB
with respect to
unloaded output
voltage
Upper threshold
(overvoltage)
SKIP = VCC+10+12
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Undervoltage Fault and
VROK Transition Blanking Time
(Note 4)
tBLANK
Measured from the time when FB reaches
the voltage set by the DAC code; clock
speed set by RTIMEClks
VROK Startup Delay
Measured from the time when FB first
reaches the voltage set by the DAC code
after startup
357ms
VROK DelaytVROKFB forced 2% outside the VROK trip
threshold10µs
VROK Output Low VoltageISINK = 3mA0.4V
VROK Leakage CurrentHigh state, VROK forced to 5.5V1µA
VCC Undervoltage Lockout
ThresholdVUVLO(VCC)Rising edge, hysteresis = 90mV, PWM
disabled below this level4.04.254.4V
Thermal-Shutdown ThresholdTSHDNHysteresis = 10°C160°C
CURRENT LIMIT AND BALANCECurrent-Limit Threshold Voltage
(Positive, Default)VLIMITCMP - CMN, CSP - CSN; ILIM = VCC283032mV
VILIM = 0.2V81012Current-Limit Threshold Voltage
(Positive, Adjustable)VLIMITCMP - CMN, CSP - CSNVILIM = 1.5V737577mV
Current-Limit Threshold Voltage
(Negative)VLIMIT(NEG)CMP - CMN, CSP - CSN; ILIM = VCC,
SKIP = VCC-41-36-31mV
Current-Limit Threshold Voltage
(Zero Crossing)VZEROCMP - CMN, CSP - CSN; SKIP = GND1.5mV
CMP, CMN, CSP, CSN Input
Ranges02V
CMP, CMN, CSP, CSN Input
CurrentVCSP = VCSN = 0 to 5V-2+2µA
Secondary Driver-Disable
ThresholdVCSP3VCC - 1VCC -
0.4V
ILIM Input CurrentIILIMVILIM = 0 to 5V0.1200nA
Current-Limit Default Switchover
ThresholdVILIM3VCC - 1VCC -
0.4V
Current-Balance OffsetVOS(IBAL)
(VCMP - VCMN) - (VCSP - VCSN); ICCI = 0,
-20mV < (VCMP - VCMN) < 20mV,
1.0V < VCCI < 2.0V+2mV
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCurrent-Balance
TransconductanceGm(IBAL)400µS
GATE DRIVERSDH_ Gate-Driver On-ResistanceRON(DH)BST_ - LX_ forced to 5V1.04.5Ω
High state (pullup)1.04.5DL_ Gate-Driver On-ResistanceRON(DL)Low start (pulldown)0.42Ω
DH_ Gate-Driver Source/Sink
CurrentIDHDH_ forced to 2.5V,
BST_ - LX_ forced to 5V1.6A
DL_ Gate-Driver Sink CurrentIDL(SINK)DL_ forced to 5V4A
DL_ Gate-Driver Source CurrentIDL(SOURCE)DL_ forced to 2.5V1.6A
DL_ rising35Dead TimetDEADDH_ rising26ns
VOLTAGE-POSITIONING AMPLIFIERInput Offset VoltageVOS-1+1mV
Input Bias CurrentIBIASOAIN+, OAIN-0.1200nA
Op Amp Disable ThresholdVOAIN-3VCC - 1VCC -
0.4V
Common-Mode Input Voltage
RangeVCMGuaranteed by CMRR test02.5V
Common-Mode Rejection RatioCMRRVOAIN+ = VOAIN- = 0 to 2.5V70115dB
Power-Supply Rejection RatioPSRRVCC = 4.5V to 5.5V75100dB
Large-Signal Voltage GainAOARL = 1kΩ to VCC/280112dB
VCC - VFBH77300Output Voltage Swing|VOAIN+ - VOAIN-| ≥ 10mV,
RL = 1kΩ to VCC/2VFBL47200mV
Input Capacitance11pF
Gain-Bandwidth Product3MHz
Slew Rate0.3V/µs
Capacitive-Load StabilityNo sustained oscillations400pF
LOGIC AND I/OSHDN Input High VoltageVIH0.8V
SHDN Input Low VoltageVIL0.4V
SHDN No-Fault ThresholdV SHDNTo enable no-fault mode1215V
OVP Input High Voltage2.4V
OVP Input Low Voltage0.8V
High2.7
REF1.22.3Three-Level Input Logic LevelsSUS, SKIP
Low0.8
Logic Input CurrentSHDN, SKIP, SUS, OVP-1+1µA
D0–D4 Logic Input High Voltage1.6V
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSD0–D4 Logic Input Low Voltage0.8V
D0–D4 Input CurrentD0–D4-2+2µA
HighVCC -
Open3.153.85
REF1.652.35
Four-Level Input Logic LevelsTON, S0–S1
Low0.4
Four-Level Input CurrentTON, S0–S1 forced to GND or VCC-3+3µA
ELECTRICAL CHARACTERISTICS(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
PWM CONTROLLERBattery voltage, V+428Input Voltage RangeVCC, VDD4.55.5V
DAC codes ≥ 1V-13+13
DC Output Voltage Accuracy
(Note 2)
V+ = 4.5V to 28V,
includes load
regulation error
DAC codes from
0.60V to 1V-20+20mV
OFS Input Range02V
ΔVOUT/ΔVOFS;ΔVOFS = VOFS, VOFS = 0 to 1V-0.131-0.115
OFS GAINAOFSΔVOUT/ΔVOFS;
ΔVOFS = VOFS-VREF, VOFS = 1V to 2V-0.131-0.115
V/V
GNDS GainAGNDSΔVOUT/ΔVGNDS0.941.01V/V
1000kHz nominal, RTIME = 15kΩ8801120
500kHz nominal, RTIME = 30kΩ450550TIME Frequency AccuracyfTIME
250kHz nominal, RTIME = 60kΩ220280
kHz
TON = GND
(550kHz)150210
TON = REF
(300kHz)315395
TON = open
(200kHz)470580
On-Time (Note 3)tONV+ = 12V,
VFB = VCCI = 1.2V
TON = VCC
(100kHz)9101150
TON = GND380Minimum Off-Time (Note 3)tOFF(MIN)TON = VCC, open, or REF490ns
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINMAXUNITS
BIAS AND REFERENCEQuiescent Supply Current (VCC)ICCMeasured at VCC, FB forced above the
regulation point, OAIN- = FB, V OAI N + = 1.3V 3.2mA
Quiescent Supply Current (VDD)IDDMeasured at VDD, FB forced above the
regulation point20µA
Quiescent Battery Supply Current
(V+)IV+Measured at V+50µA
Shutdown Supply Current (VCC)Measured at VCC, SHDN = GND20µA
Shutdown Supply Current (VDD)Measured at VDD, SHDN = GND20µA
Shutdown Battery Supply Current
(V+)
Measured at V+, SHDN = GND,
VCC = VDD = 0 or 5V20µA
Reference VoltageVREFVCC = 4.5V to 5.5V, IREF = 01.9852.015V
FAULT PROTECTIONOutput Overvoltage Protection
ThresholdVOVPSKIP = VCC, measured at FB with respect
to unloaded output voltage1319%
Output Undervoltage Protection
ThresholdVUVPMeasured at FB with respect to unloaded
output voltage6773%
Lower threshold
(undervoltage)-13-7
VROK Threshold
Measured at FB
with respect to
unloaded output
voltage
Upper threshold
(overvoltage)
SKIP = VCC+13
VROK Startup Delay
Measured from the time when FB first
reaches the voltage set by the DAC code
after startup
3ms
VCC Undervoltage Lockout
ThresholdVUVLO(VCC)Rising edge, hysteresis = 90mV, PWM
disabled below this level3.904.45V
CURRENT LIMIT AND BALANCECurrent-Limit Threshold Voltage
(Positive, Default)VLIMITCMP - CMN, CSP - CSN; ILIM = VCC2733mV
VILIM = 0.2V713Current-Limit Threshold Voltage
(Positive, Adjustable)VLIMITCMP - CMN,
CSP - CSNVILIM = 1.5V7278mV
Current-Limit Threshold Voltage
(Negative)VLIMIT(NEG)CMP - CMN, CSP - CSN; ILIM = VCC,
SKIP = VCC-30-42mV
Current-Balance OffsetVOS(IBAL)
(VCMP - VCMN) - (VCSP - VCSN); ICCI = 0,
-20mV < (VCMP - VCMN) < 20mV,
1.0V < VCCI < 2.0V+3mV
GATE DRIVERSDH_ Gate-Driver On-ResistanceRON(DH)BST_ - LX_ forced to 5V4.5Ω
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)(Circuit of Figure 1, V+ = 15V, VCC= VDD= VSHDN= VTON= VSKIP= VS0= VS1= VOVP= 5V, VFB= VCMP= VCMN= VCSP= VCSN=
1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA
= -40°C to +100°C, unless otherwise specified.) (Note 5)
PARAMETERSYMBOLCONDITIONSMINMAXUNITSHigh state (pullup)4.5DL_ Gate-Driver On-ResistanceRON(DL)Low start (pulldown)2Ω
VOLTAGE-POSITIONING AMPLIFIERInput Offset VoltageVOS-2.0+2.0mV
Common-Mode Input Voltage
RangeVCMGuaranteed by CMRR test02.5V
VCC - VFBH300Output Voltage Swing|VOAIN+ - VOAIN-| ≥ 10mV,
RL = 1kΩ to VCC/2VFBL200mV
LOGIC AND I/OSHDN Input High VoltageVIH0.8V
SHDN Input Low VoltageVIL0.4V
High2.7
REF1.22.3Three-Level Input Logic LevelsSUS, SKIP
Low0.8
D0–D4 Logic Input High Voltage1.6V
D0–D4 Logic Input Low Voltage0.8V
OVP Input High Voltage2.4V
OVP Input Low Voltage0.8V
HighVCC -
Open3.153.85
REF1.652.35
Four-Level Input Logic LevelsTON, S0–S1
Low0.4
Note 2:DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises
(<0.5%) when transitioning from continuous conduction to no load.
Note 3:On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to
GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-
circuit times may be different due to MOSFET switching speeds.
Note 4:The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.
During normal operation (SUS = GND), the regulation voltage is set by the VID DAC inputs (D0–D4). During suspend mode
(SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0–S1).
Note 5:Specifications to TA= -40°C and +100°C are guaranteed by design and are not production tested.
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.50V)MAX1544 toc01
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)50301020
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.50V)
MAX1544 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
VIN = 20V
VIN = 12V
VIN = 8V
SKIP = REF
SKIP = VCC
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.00V)MAX1544 toc03
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)10302040
LOAD CURRENT (A)
EFFICIENCY (%)
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.00V)MAX1544 toc04
VIN = 20V
VIN = 12V
VIN = 8V
SKIP = REF
SKIP = VCC
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 0.80V)MAX1544 toc05
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
SUS = VCC20
LOAD CURRENT (A)
EFFICIENCY (%)
DUAL-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.80V)MAX1544 toc06
VIN = 20V
VIN = 8V
VIN = 12V
SKIP = REF
LOAD CURRENT (A)
EFFICIENCY (%)
SINGLE-PHASE EFFICIENCY vs. LOAD CURRENT
(VOUT = 0.80V)MAX1544 toc07
VIN = 20V
VIN = 8V
VIN = 12V
SKIP = GND
SWITCHING FREQUENCY
vs. LOAD CURRENTMAX1544 toc08
LOAD CURRENT (A)
SWITCHING FREQUENCY (kHz)1020
VOUT = 1V (NO LOAD)
SKIP MODE (SKIP = REF)
FORCED-PWM (SKIP = VCC)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FORCED-PWM MODE)MAX1544 toc09
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)2551510
IIN
SKIP = VCC
ICC + IDD
Typical Operating Characteristics(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN= SKIP= VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V
(SUS = VCC), OFS = GND, TA= +25°C, unless otherwise specified.)
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PULSE SKIPPING)MAX1544 toc10
INPUT VOLTAGE (V)
SUPPLY CURRENT (mA)2551510
IIN
SKIP = REF
ICC + IDD
OUTPUT OFFSET VOLTAGE
vs. OFS VOLTAGEMAX1544 toc11
OFS VOLTAGE (V)
OUTPUT OFFSET VOLTAGE (mV)
UNDEFINED
REGION
REFERENCE VOLTAGE
DISTRIBUTIONMAX1544 toc12
REFERENCE VOLTAGE (V)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 100
CURRENT-BALANCE OFFSET
VOLTAGE DISTRIBUTIONMAX1544 toc13
OFFSET VOLTAGE (mV)
SAMPLE PERCENTAGE (%)
SAMPLE SIZE = 100
CURRENT-LIMIT THRESHOLD
DISTRIBUTIONMAX1544 toc14
CURRENT LIMIT (mV)
SAMPLE PERCENTAGE (%)
VILIM = 0.20V
SAMPLE SIZE = 100
0.1101001k110k
VOLTAGE-POSITIONING AMPLIFIER
GAIN AND PHASE vs. FREQUENCY MAX1544 toc15
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEGREES)
GAIN
PHASE
VPS AMPLIFIER OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGEMAX1544 toc16
COMMON-MODE VOLTAGE (V)1205
OFFSET VOLTAGE (
VPS AMPLIFIER
DISABLED
INDUCTOR CURRENT DIFFERENCE
vs. LOAD CURRENTMAX1544 toc17
LOAD CURRENT (A)401020050
IL(CS)
- I
L(CM)
(A)
RSENSE = 1mΩ
SKIP = REF
SKIP = VCC
ypical Operating Characteristics (continued)(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN= SKIP= VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V
(SUS = VCC), OFS = GND, TA= +25°C, unless otherwise specified.)
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
POWER-UP SEQUENCEMAX1544 toc18B
1ms/div
A. SHDN, 5V/div
B. 1.5V OUTPUT, 1V/div
C. VROK, 5V/div
RTIME = 64.9kΩ
SOFT-STARTMAX1544 toc19
10A
1.5V
100μs/div
A. SHDN, 5V/div
B. 1.5V OUTPUT, 1V/div
C. IL1, 10A/div
D. IL2, 10A/div
RLOAD = 75mΩ, RTIME = 64.9kΩ
SOFT-SHUTDOWNMAX1544 toc20
10A
10A
1.5V
200μs/div
A. SHDN, 5V/div
B. 1.5V OUTPUT, 1V/div
C. IL1, 10A/div
D. IL2, 10A/div
RLOAD = 75mΩ, RTIME = 64.9kΩ
1.50V LOAD TRANSIENT
(10A TO 50A LOAD)MAX1544 toc21
50A
20A
20A
10A
1.5VB
20μs/div
A. LOAD CURRENT, (ILOAD = 10A TO 50A), 50A/div
B. OUTPUT VOLTAGE (1.50V NO LOAD), 100mV/div
C. IL1, 10A/div
D. IL2, 10A/div
ypical Operating Characteristics (continued)(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN= SKIP= VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V
(SUS = VCC), OFS = GND, TA= +25°C, unless otherwise specified.)
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Suppliesypical Operating Characteristics (continued)(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN= SKIP= VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V
(SUS = VCC), OFS = GND, TA= +25°C, unless otherwise specified.)
1.00V LOAD TRANSIENT
(10A TO 30A LOAD)MAX1544 toc22
30A
10A
10A
10A
1.0VB
20μs/div
A. LOAD CURRENT, (ILOAD = 10A TO 30A), 25A/div
B. OUTPUT VOLTAGE (1.00V NO LOAD), 50mV/div
C. IL1, 10A/div
D. IL2, 10A/div
OFFSET TRANSITIONMAX1544 toc23
0.2V
1.5VB
20μs/div
A. VOFS = 0 TO 200mV, 0.2V/div
B. VOUT = 1.500V TO 1.475, 20mV/div
C. IL1, 10A/div
D. IL2, 10A/div
10A LOAD
SUSPEND TRANSITION
(DUAL-PHASE PWM OPERATION)MAX1544 toc24
3.3V
2.5A
2.5A
1.5V
1.0V
40μs/div
A. SUS, 5V/div
B. VOUT = 1.5V TO 1.0V, 0.5V/div
C. IL1, 10A/div
D. IL2, 10A/div
5A LOAD, SKIP = VCC, RTIME = 64.9kΩ
SUSPEND TRANSITION
(SINGLE-PHASE SKIP OPERATION)MAX1544 toc25
3.3V
10A
10A
1.5V
1.0V
100μs/div
A. SUS, 5V/div
B. VOUT = 1.5V TO 1.0V, 0.5V/div
C. IL1, 10A/div
D. IL2, 10A/div
5A LOAD, COUT = (4) 680μF, SKIP = SUS, RTIME = 64.9kΩ
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Suppliesypical Operating Characteristics (continued)(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN= SKIP= VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V
(SUS = VCC), OFS = GND, TA= +25°C, unless otherwise specified.)
SINGLE-PHASE SKIP TO DUAL-PHASE
PWM TRANSITIONMAX1544 toc26
1.5VB
20μs/div
A. SKIP = VCC TO GND, 5V/div
B. 1.5V OUTPUT, 50mV/div
C. IL1, 10A/div
D. IL2, 10A/div
2A LOAD
DUAL-PHASE SKIP TO DUAL-PHASE
PWM TRANSITIONMAX1544 toc27
1.5VB
20μs/div
A. SKIP = VCC TO REF, 5V/div
B. 1.5V OUTPUT, 50mV/div
C. IL1, 10A/div
D. IL2, 10A/div
2A LOAD
100mV DAC CODE TRANSITIONMAX1544 toc28
3.3V
1.5V
1.4V
20μs/div
A. D1, 5V/div
B. VOUT = 1.50V TO 1.40V, 100mV/div
C. IL1, 10A/div
D. IL2, 10A/div
10A LOAD
400mV DAC CODE TRANSITIONMAX1544 toc29
3.3V
1.5V
1.1VB
40μs/div
A. D3, 5V/div
B. VOUT = 1.50V TO 1.10V, 0.5V/div
C. IL1, 10A/div
D. IL2, 10A/div
10A LOAD
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Pin Description
PINNAMEFUNCTIONTIMESlew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
150kΩ to 15kΩ resistor sets the clock from 100kHz to 1MHz, fSLEW = 500kHz × 30kΩ/RTIME.TON
On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the
DH_ on-time (see the On-Time One-Shot (TON) section): GND = 550kHz, REF = 300kHz, OPEN =
200kHz, VCC = 100kHzSUS
Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the
controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4.
The controller blanks VROK during the transition and another 24 RTIME clock cycles after the new
DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output
voltage:
3.3V or VCC (high) = Suspend mode; S0–S1 low-range suspend code (Table 5)
REF = Suspend mode; S0–S1 high-range suspend code (Table 5)
GND = Normal operation; D0–D4 VID DAC code (Table 4)
4, 5S0, S1
Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend
mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode
VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage
setting (Figure 3).SHDNhutd ow n C ontr ol Inp ut. Thi s i np ut cannot w i thstand the b atter y vol tag e. C onnect to V C C for nor m al
op er ati on. C onnect to g r ound to p ut the IC i nto i ts 1µA ( typ ) shutd ow n state. D ur i ng the tr ansi ti on fr om
nor m al op er ati on to shutd ow n, the outp ut vol tag e r am p s d ow n at 4 ti m es the outp ut- vol tag e sl ew r ater og r am m ed b y the TIM E p i n. In shutd ow n m od e, D LM and D LS ar e for ced to V D D to cl am p the outp ut tor ound . For ci ng SH DN to 12V ~ 15V d i sab l es b oth over vol tag e p r otecti on and und er vol tag e p r otecti on
ci r cui ts, d i sab l es over l ap op er ati on, and cl ear s the faul t l atch. D o not connect SH DN to > 15V .OFS
Voltage-Divider Input for Offset Control. For 0 < VOFS < 0.8V, 0.125 times the voltage at OFS is
subtracted from the output. For 1.2V < VOFS < 2V, 0.125 times the difference between REF and OFS
is added to the output. Voltages in the range of 0.8V < VOFS < 1.2V are undefined. The controller
disables the offset amplifier during suspend mode (SUS = REF or high).REF
2V Reference Output. Bypass to GND with 0.22µF or greater ceramic capacitor. The reference can
source 100µA for external loads. Loading REF degrades output voltage accuracy according to the
REF load regulation error.ILIM
Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to VCC. In
adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a
0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately VCC
- 1V.VCC
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V)
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC
as possible.GNDAnalog Ground. Connect the MAX1544’s exposed pad to analog ground.CCVVoltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF typ) capacitor from CCV
to analog ground (GND) to set the integration time constant.GNDS
Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally
connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the
regulator ground to the load ground.
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
PINNAMEFUNCTIONCCICurrent Balance Compensation. Connect a 470pF capacitor between CCI and FB. See the Current
Balance Compensation section.FBFeedback Input. FB is internally connected to both the feedback input and the output of the voltage-
positioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain.OAIN-
Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional
voltage-positioning gain, connect to the negative terminal of current-sense resistor through a resistor
as described in the Setting Voltage Positioning section. Connect OAIN- to VCC to disable the op amp.
The logic threshold to disable the op amp is approximately VCC - 1V.OAIN+
Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain,
connect to the positive terminal of current-sense resistor through a resistor as described in the Setting
Voltage Positioning section.SKIP
Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold:
3.3V or VCC (high) = Dual-phase forced-PWM operation
REF = Dual-phase pulse-skipping operation
GND = Single-phase pulse-skipping operationOVP
Overvoltage Protection Enable Input. Connect OVP to VCC to enable the output overvoltage fault
protection. Connect OVP to GND to disable the output overvoltage fault protection. During normal
forced-PWM operation (SKIP = high), the controller detects an OVP fault if the output voltage exceeds
the set DAC voltage by more than 13% (min). During pulse-skipping operation (SKIP = REF or GND),
the controller detects an OVP fault if the output voltage exceeds the fixed 2V (typ) threshold. If an
overvoltage fault occurs, the controller is immediately shutdown and the output is discharged. See
the Fault Protection section.
20–24D4–D0
Low-Voltage VID DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the
output voltage is set by the VID code indicated by the logic-level voltages on D0-D4. In suspend
mode (Table 5, SUS = REF or high), the decoded state of the four-level S0–S1 inputs sets the output
voltage.VROK
Open-Drain Power-Good Output. After output voltage transitions, except during power-up and power-
down, if OUT is in regulation then VROK is high impedance. The controller blanks VROK whenever
the slew rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup
resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms
(min) delay after the output reaches the regulation voltage.BSTMMain Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM
pullup current to be adjusted.LXMMain Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.DHMMain High-Side Gate-Driver Output. Swings LXM to BSTM.DLMM ai n Low - S i d e G ate- D r i ver O utp ut. D LM sw i ng s fr om P GN D to V D D . D LM i s for ced hi g h after theAX 1544 p ow er s d ow n.VDD
Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V
to 5.5V). Bypass VDD to PGND with a 2.2µF or greater ceramic capacitor as close to the IC as
possible.PGND Power Ground. Ground connection for low-side gate drivers DLM and DLS.
Pin Description (continued)
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Detailed Description
Dual 180°Out-of-Phase Operation The two phases in the MAX1544 operate 180°out-of-
phase (SKIP= REF or high) to minimize input and output
filtering requirements, reduce electromagnetic interfer-
ence (EMI), and improve efficiency. This effectively low-
ers component count—reducing cost, board space, and
component power requirements—making the MAX1544
ideal for high-power, cost-sensitive applications.
Typically, switching regulators provide transfer power
using only one phase instead of dividing the power
among several phases. In these applications, the input
capacitors must support high-instantaneous current
requirements. The high-RMS ripple current can lower
efficiency due to I2R power loss associated with the input
capacitor’s effective series resistance (ESR). Therefore,
the system typically requires several low-ESR input
capacitors in parallel to minimize input voltage
ripple, to reduce ESR-related power losses, and to meet
the necessary RMS ripple current rating.
With the MAX1544, the controller shares the current
between two phases that operate 180°out-of-phase, so
the high-side MOSFETs never turn on simultaneously
during normal operation. The instantaneous input cur-
rent of either phase is effectively cut in half, resulting in
reduced input voltage ripple, ESR power loss, and RMS
ripple current (see the Input Capacitor Selectionsec-
tion). As a result, the same performance can be
achieved with fewer or less-expensive input capacitors.
Table 1 lists component selection for standard multi-
phase selections and Table 2 is a list of component
suppliers.
Transient Overlap OperationWhen a transient occurs, the response time of the con-
troller depends on how quickly it can slew the inductor
current. Multiphase controllers that remain 180 degrees
out-of-phase when a transient occurs actually respond
slower than an equivalent single-phase controller. In
order to provide fast transient response, the MAX1544
supports a phase-overlap mode, which allows the dual
regulators to operate in-phase when heavy-load tran-
sients are detected, reducing the response time. After
either high-side MOSFET turns off, if the output voltage
does not exceed the regulation voltage when the mini-
mum off-time expires, the controller simultaneously
turns on both high-side MOSFETs during the next on-
time cycle. This maximizes the total inductor current
slew rate. The phases remain overlapped until the out-
put voltage exceeds the regulation voltage after the
minimum off-time expires.
Pin Description (continued)
PINNAMEFUNCTIONDLSS econd ar y Low - S i d e G ate- D r i ver O utp ut. D LS sw i ng s fr om P GN D to V D D . D LS i s for ced hi g h after theAX 1544 p ow er s d ow n.DHSSecondary High-Side Gate-Driver Output. Swings LXS to BSTS.LXSSecondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate
driver.BSTSSecondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the
DHS pullup current to be adjusted.V+Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely
proportional to input voltage over a range of 4V to 28V.CMPMain Inductor Positive Current-Sense InputCMNMain Inductor Negative Current-Sense InputCSNSecondary Inductor Positive Current-Sense InputCSPSecondary Inductor Negative Current-Sense Input
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power SuppliesAfter the phase-overlap mode ends, the controller auto-
matically begins with the opposite phase. For example,
if the secondary phase provided the last on-time pulse
before overlap operation began, the controller starts
switching with the main phase when overlap operation
ends.
Power-Up SequenceThe MAX1544 is enabled when SHDNis driven high
(Figure 2). The reference powers up first. Once the ref-
erence exceeds its UVLO threshold, the PWM controller
evaluates the DAC target and starts switching.
For the MAX1544, the slew-rate controller ramps up the
output voltage in 25mV increments to the proper operat-
ing voltage (see Tables 3 and 4) set by either D0–D4
(SUS = GND) or S0–S1 (SUS = REF or high). The ramp
rate is set with the RTIMEresistor (see the Output Voltage
Transition Timingsection).
The ramp rate is set with the RTIMEresistor (see the
Output Voltage Transition Timingsection). The con-
troller pulls VROK low until at least 3ms after the
MAX1544 reaches the target DAC code.
MAX1544
AMD MOBILE COMPONENTS
MAX1544
AMD DESKTOP COMPONENTSDESIGNATION
Circuit of Figure 1Circuit of Figure 12Input Voltage Range7V to 24V7V to 24V
VID Output Voltage
(D4–D0)
1.5V
(D4–D0 = 00010)
1.5V
(D4–D0 = 00010)
Suspend Voltage
(SUS, S0–S1)
Not used
(SUS = GND)
Not used
(SUS = GND)
Maximum Load Current60A70A
Number of Phases (ηTOTAL)Two phases
(1) MAX1544
Four phases
(1) MAX1544 + (2) MAX1980
Inductor (per Phase)0.6µH Panasonic ETQP1H0R6BFA0.7µH Panasonic ETQP2H0R7BFA
or 0.8µH Sumida CDEP105L-0R8
Switching Frequency300kHz (TON = REF)300kHz (TON = REF)
High-Side MOSFET
(NH, per phase)
Siliconix (1) Si7886DP or
International Rectifier (2) IRF6604
International Rectifier (1) IRF7811W
or Fairchild (1) FDS6694
Low-Side MOSFET
(NL, per phase)
Siliconix (2) Si7442DP or
International Rectifier (2) IRF6603Fairchild (2) FDS6688 or Siliconix (1) Si7442DP
Total Input Capacitance (CIN)
(8) 10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
(8) 10µF, 25V
Taiyo Yuden TMK432BJ106KM or
TDK C4532X5R1E106M
Total Output Capacitance
(COUT)
(4) 680µF, 2.5V
Sanyo 2R5TPD680M
(5) 680µF, 2.5V
Sanyo 2R5TPD680M
Current-Sense Resistor
(RSENSE, per Phase)
1mΩ
Panasonic ERJM1WTJ1M0U
1mΩ
Panasonic ERJM1WTJ1M0U
Table 1. Component Selection for Standard Multiphase Applications
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power SuppliesINPUT*
7V TO 24V
OUTPUT
VCC
VROK
SHDN
OFS
POWER
GOOD
OFF
DAC INPUTS
SUSPEND INPUTS
(FOUR-LEVEL LOGIC)
CBST1
0.22μF
NH1
NH2
NL1
CIN
1μF
CREF
0.22μF
R13
10ΩR12
100kΩ
CCCV
47pF
CCCI
470pF
CBST2
0.22μF
158kΩ±1%
100pF
R10
1.5kΩ
±1%
1.5kΩ
±1%
5V BIAS
SUPPLYC1
2.2μF
COUT
COUT
*LOWER INPUT VOLTAGES
REQUIRE ADDITIONAL
INPUT CAPACITANCE.
BST
DIODES
OVP
SUS
TIME
CCV
SKIP
RSENSE1
1.0mΩ
NL2
30.1kΩ
±1%
100kΩ
±1%
1kΩ±1%R5
1kΩ±1%
POWER GROUND
ANALOG GROUND
MAX1544
CIN
REF
TON
REF
VCC (OVP ENABLED)
1kΩ±1%
1kΩ±1%RTIME
64.9kΩ
RSENSE2
1.0mΩ
BSTM
DHM
LXM
DLM
PGND
GND
CMN
CMP
OAIN+
OAIN-
REF (300kHz)
CCI
CSP
CSN
BSTS
DHS
LXS
DLS
GNDS
VDD
ILIM
49.9kΩ±1%
SKIP
PWM
Figure 1. Standard Two-Phase AMD Mobile 60A Application Circuit
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
ShutdownWhen SHDNgoes low, the MAX1544 enters low-power
shutdown mode. VROK is pulled low immediately, and
the output voltage ramps down to 0V in LSB increments
at 4 times the clock rate set by RTIME:
where fSLEW= 500kHz ✕30kΩ/RTIME, VDACis the DAC
setting when the controller begins the shutdown
sequence, and VLSB= 25mV is the DAC’s smallest volt-
age increment. Slowly discharging the output capacitors
by slewing the output over a long period of time
(4/fSLEW) keeps the average negative inductor current
low (damped response), thereby eliminating the nega-
tive output voltage excursion that occurs when the con-
troller discharges the output quickly by permanently
turning on the low-side MOSFET (underdamped
response). fSHDNSLEW
DAC
LSB≤4
MANUFACTURERPHONEWEBSITEBI Technologies714-447-2345 (USA)www.bitechnologies.com
Central Semiconductor631-435-1110 (USA)www.centralsemi.com
Coilcraft800-322-2645 (USA)www.coilcraft.com
Coiltronics561-752-5000 (USA)www.coiltronics.com
Fairchild Semiconductor888-522-5372 (USA)www.fairchildsemi.com
International Rectifier310-322-3331 (USA)www.irf.com
Kemet408-986-0424 (USA)www.kemet.com
Panasonic847-468-5624 (USA)www.panasonic.com
Sanyo65-6281-3226 (Singapore)www.secc.co.jp
Siliconix (Vishay)203-268-6261 (USA)www.vishay.com
Sumida408-982-9660 (USA)www.sumida.com
Taiyo Yuden03-3667-3408 (Japan)
408-573-4150 (USA)www.t-yuden.com
TDK847-803-6100 (USA)
81-3-5201-7241 (Japan)www.component.tdk.com
TOKO858-675-8013 (USA)www.tokoam.com
Table 2. Component SuppliersVID (D0–D4)
SHDN
VCORE
tVROK(START)
3ms (TYP)
SOFT-SHUTDOWN
1 LSB PER 4 RTIME CYCLES
SOFT-START
1 LSB PER RTIME CYCLE
VROK
DO NOT CARE
Figure 2. Power-Up and Shutdown Sequence Timing Diagram
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power SuppliesThis eliminates the need for the Schottky diode normally
connected between the output and ground to clamp the
negative output voltage excursion. When the DAC
reaches the 0V setting, DL_ goes high, DH_ goes low,
the reference turns off, and the supply current drops to
about 1µA. When a fault condition—output undervoltage
lockout, output overvoltage lockout (OVP = VCC), or ther-
mal shutdown—activates the shutdown sequence, the
controller sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the con-
troller, toggle SHDNor cycle VCCpower below 1V.
When SHDNgoes high, the reference powers up. Once
the reference voltage exceeds its UVLO threshold, the
controller evaluates the DAC target and starts switching.
The slew-rate controller ramps up from 0V in LSB
increments to the currently selected output-voltage set-
ting (see the Power-Up Sequencesection). There is no
traditional soft-start (variable current-limit) circuitry, so
full output current is available immediately.
Internal MultiplexersThe MAX1544 has a unique internal DAC input
multiplexer (muxes) that selects one of three different
DAC code settings for different processor states
(Figure 3). On startup, the MAX1544 selects the DAC
code from the D0–D4 (SUS = GND) or S0–S1 (SUS = REF
or high) input decoders.
DAC Inputs (D0–D4)During normal forced-PWM operation (SUS = GND), the
digital-to-analog converter (DAC) programs the output
voltage using the D0–D4 inputs. Do not leave D0–D4
unconnected. D0–D4 can be changed while the
MAX1544 is active, initiating a transition to a new output
voltage level. Change D0–D4 together, avoiding
greater than 1µs skew between bits. Otherwise, incor-
rect DAC readings can cause a partial transition to the
wrong voltage level followed by the intended transition
to the correct voltage level, lengthening the overall tran-
sition time. The available DAC codes and resulting out-
put voltages are compatible with AMD Hammer voltage
specifications (Table 4).
Four-Level Logic InputsTON and S0–S1 are four-level logic inputs. These
inputs help expand the functionality of the controller
without adding an excessive number of pins. The four-
level inputs are intended to be static inputs. When left
open, an internal resistive voltage-divider sets the input
voltage to approximately 3.5V. Therefore, connect the
four-level logic inputs directly to VCC, REF, or GND
when selecting one of the other logic levels. See the
Electrical Characteristicsfor exact logic level voltages.
SHDN
SUSSKIP
OFSOUTPUT
VOLTAGEOPERATING MODEGNDxxxGND
Low-Power Shutdown Mode. DL_ is forced high, DH_ is
forced low, and the PWM controller is disabled. The supply
current drops to 1µA (typ).
VCCGNDVCCGND or REFD0–D4
(No offset)or m al Op er ati on. The no- l oad outp ut vol tag e i s d eter m i ned b y
the sel ected V ID D AC cod e ( D 0–D 4, Tab l e 4) .
VCCx
GND
REF
GND or REFD0–D4
(No offset)
Pulse-Skipping Operation. When SKIP is pulled low, the
MAX1544 immediately enters pulse-skipping operation
allowing automatic PWM/PFM switchover under light loads.
The VROK upper threshold is blanked.
VCCGNDx
0 to 0.8V
1.2V to 2V
D0–D4
(Plus offset)
Deep-Sleep Mode. The no-load output voltage is determined
by the selected VID DAC code (D0–D4, Table 4) plus the
offset voltage set by OFS.
VCC
REF
HighSUS, S0–S1
(No offset)
Suspend Mode. The no-load output voltage is determined by
the selected suspend code (SUS, S0–S1, Table 5),
overriding all other active modes of operation.
VCCxxxGND
Fault Mode. The fault latch has been set by either UVP, OVP,
or thermal shutdown. The controller remains in FAULT mode
until VCC power is cycled or SHDN toggled.
Table 3. Operating Mode Truth Table
MAX1544
Dual-Phase, Quick-PWM Controller for
AMD Hammer CPU Core Power Supplies
Suspend ModeWhen the processor enters low-power suspend mode, it
sets the regulator to a lower output voltage to reduce
power consumption. The MAX1544 includes independent
suspend-mode output voltage codes set by the four-level
S0–S1 inputs and the three-level SUS input. When the
CPU suspends operation (SUS = REF or high), the con-
troller disables the offset amplifier and overrides the 5-bit
VID DAC code set by either D0–D4 (normal operation).
The master controller slews the output to the selected
suspend-mode voltage. During the transition, the
MAX1544 blanks VROK and the UVP fault protection until
24 RTIMEclock cycles after the slew-rate controller reach-
es the suspend-mode voltage.
SUS is a three-level logic input: GND, REF, or high. This
expands the functionality of the controller without
adding an additional pin. This input is intended to be
driven by a dedicated open-drain output with the pullup
resistor connected either to REF (or a resistive divider
from VCC) or to a logic-level bias supply (3.3V or
greater). When pulled up to REF, the MAX1544 selects
the upper suspend voltage range. When pulled high
(2.7V or greater), the controller selects the lower sus-
pend voltage range. See the Electrical Characteristics
for exact logic level voltages.
Output Voltage Transition TimingThe MAX1544 is designed to perform mode transitions in
a controlled manner, automatically minimizing input surge
currents. This feature allows the circuit designer to
achieve nearly ideal transitions, guaranteeing just-in-time
arrival at the new output voltage level with the lowest pos-
sible peak currents for a given output capacitance.
At the beginning of an output voltage transition, the
MAX1544 blanks the VROK output, preventing it from
changing states. VROK remains blanked during the
transition and is enabled 24 clock cycles after the
slew-rate controller has set the final DAC code value.
The slew-rate clock frequency (set by resistor RTIME)
must be set fast enough to ensure that the transition is
completed within the maximum allotted time.
The slew-rate controller transitions the output voltage in
25mV steps during soft-start, soft-shutdown, and sus-
pend-mode transitions. The total time for a transition
depends on RTIME, the voltage difference, and the
accuracy of the MAX1544’s slew-rate clock, and is not
dependent on the total output capacitance. The greater
the output capacitance, the higher the surge current
required for the transition. The MAX1544 automatically
controls the current to the minimum level required to
complete the transition in the calculated time, as long
S0–S1
DECODER
SEL
SUS
SUSPEND
MUX
OUT1
SEL
DAC
1.0V
2.5VSUS 3-LEVEL
DECODER
OUT
D0–D4
DECODER
OUTD3
Figure 3. Internal Multiplexers Functional Diagram
