MAX149ACAP+ ,+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0; f = 2.0MHz; external clock (50% duty cycle ..
MAX149AEAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsELECTRICAL CHARACTERISTICSV = +2.7V to +5.25V; COM = 0V; f = 2.0MHz; external clock (50% duty cycle ..
MAX149BCAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsMAX148/MAX14919-0464; Rev 2; 5/98+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
MAX149BEAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsMAX148/MAX14919-0464; Rev 2; 5/98+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
MAX149BEAP+ ,+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0; f = 2.0MHz; external clock (50% duty cycle ..
MAX149BEAP+T ,+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCsFeaturesThe MAX148/MAX149 10-bit data-acquisition systems S 8-Channel Single-Ended or 4-Channel Dif ..
MAX4122EUK-T ,Single/Dual/Quad, Wide-Bandwidth, Low-Power, Single-Supply Rail-to-Rail I/O Op AmpsFeaturesThe MAX4122–MAX4129 family of operational amplifiers♦ 5-Pin SOT23 Package (MAX4122/4)combin ..
MAX4123ESA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsApplicationsMAX4123C/D 0°C to +70°C Dice* —Battery-Powered InstrumentsMAX4123ESA -40°C to +85°C 8 S ..
MAX4123EUA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsMAX4122–MAX412919-1087; Rev 1; 8/97Single/Dual/Quad, Wide-Bandwidth, Low-Power,Single-Supply Rail-t ..
MAX4123EUA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS (V = +2.7V to +6.5V, V = 0V, V = 0V, V = V /2, R tied to V /2, SHDN ‡ 2V ..
MAX4124EUK ,Single, wide-bandwidth, low-power, single-supply Rail-to-Rail I/O op amp. BW 25MHz.Applications Pin Configurations appear at end of data sheet.__________Typical Operating CircuitSele ..
MAX4124EUK+ ,Single/Dual/Quad, Wide-Bandwidth, Low-Power, Single-Supply Rail-to-Rail I/O Op AmpsApplicationsMAX4123C/D 0°C to +70°C Dice* —Battery-Powered InstrumentsMAX4123ESA -40°C to +85°C 8 S ..
MAX148BCAP+-MAX148BCAP+T-MAX148BEAP+-MAX149ACAP+-MAX149BEAP+-MAX149BEAP+T
+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCs
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
General Description
The MAX148/MAX149 10-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from a
single +2.7V to +5.25V supply, and sample to 133ksps.
Both devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI/
QSPIK and MICROWIREK devices without external
logic. A serial-strobe output allows direct connection to
TMS320-family digital signal processors. The MAX148/
MAX149 use either the internal clock or an external seri-
al-interface clock to perform successive-approximation
analog-to-digital conversions.
The MAX149 has an internal 2.5V reference, while the
MAX148 requires an external reference. Both parts
have a reference-buffer amplifier with a Q1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDN pin and
a software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX148/MAX149, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60FA at reduced sampling rates.
The MAX148/MAX149 are available in 20-pin PDIP and
20-pin SSOP packages.
For 4-channel versions of these devices, see the
MAX1248/MAX1249 data sheet.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Features8-Channel Single-Ended or 4-Channel Differential
InputsSingle-Supply Operation: +2.7V to +5.25VInternal 2.5V Reference (MAX149)Low Power: 1.2mA (133ksps, 3V Supply)54µA (1ksps, 3V Supply)1µA (Power-Down Mode)SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
19-0464; Rev 5; 1/12
Typical Operating Circuit
Ordering Information
Ordering Information continued at end of data sheet.
†Contact factory for availability of alternate surface-mount
package.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
PART†TEMP RANGEPIN-
PACKAGE
INL
(LSB)
MAX148ACPP+0°C to +70°C20 PDIP±1/2
MAX148BCPP+0°C to +70°C20 PDIP±1
MAX148ACAP+0°C to +70°C20 SSOP±1/2
MAX148BCAP+0°C to +70°C20 SSOP±1
CPU
VDD
VSS
VDD
DGND
AGND
COM
SCLK
DIN
DOUT
SSTRB
READJ
VREF
CH7
CH0
+3V
0.1FF
4.7FF
O TO
+2.5V
ANALOG
INPUTS
0.01FF
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
MAX149
SHDN
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
VDD to AGND, DGND ..............................................-0.3V to +6V
AGND to DGND ...................................................-0.3V to +0.3V
CH0–CH7, COM to AGND, DGND ...........-0.3V to (VDD + 0.3V)
VREF, REFADJ to AGND ...........................-0.3V to (VDD + 0.3V)
Digital Inputs to DGND ...........................................-0.3V to +6V
Digital Outputs to DGND ..........................-0.3V to (VDD + 0.3V)
Digital Output Sink Current ................................................25mA
Continuous Power Dissipation (TA = +70NC)
PDIP (derate 11.11mW/NC above +70NC) ...................889mW
SSOP (derate 8.00mW/NC above +70NC) ....................640mW
Operating Temperature Ranges
MAX148_C_P/MAX149_C_P ..............................0NC to +70NC
MAX148_E_P/MAX149_E_P ............................-40NC to +85NC
MAX149BMAP ...............................................-55NC to +125NC
Storage Temperature Range ............................-60NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless
otherwise noted.)
ABSOLUTE MAXIMUM RATINGS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)
Resolution10Bits
Relative Accuracy (Note 2)INLMAX14_A±0.5LSBMAX14_B±1.0
Differential NonlinearityDNLNo missing codes over temperature±1LSB
Offset ErrorMAX14_A±0.15±1LSBMAX14_B±0.15±2
Gain Error (Note 3)MAX14_A±1LSBMAX14_B±2
Gain Temperature Coefficient±0.25ppm/°C
Channel-to-Channel Offset
Matching±0.05LSB
DYNAMIC SPECIFICATIONS (10kHz Sine-Wave Input, 0 to 2.500VP-P, 133ksps, 2.0MHz External Clock, Bipolar Input Mode)
Signal-to-Noise + Distortion
NoiseSINAD66dB
Total Harmonic DistortionTHDUp to the 5th harmonic-70dB
Spurious-Free Dynamic RangeSFDR70dB
Channel-to-Channel Crosstalk65kHz, 2.500VP-P (Note 4) -75dB
Small-Signal Bandwidth-3dB rolloff2.25MHz
Full-Power Bandwidth1.0MHz
CONVERSION RATE
Conversion Time (Note 5)tCONV
Internal clock, SHDN = unconnected5.57.5Internal clock, SHDN = VDD3565
External clock = 2MHz, 12 clocks/
conversion6
Track/Hold Acquisition TimetACQ1.5µs
Aperture Delay30ns
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CONVERSION RATE (continued)
Internal Clock FrequencySHDN = unconnected1.8MHzSHDN = VDD0.225
External Clock Frequency0.12.0MHzData transfer only12.0
ANALOG/COM INPUTS
Input Voltage Range, Single-
Ended and Differential (Note 6)
Unipolar, COM = 00 to VREFVBipolar, VCOM = VREF/2±VREF/2
Multiplexer Leakage CurrentOn/off leakage current, VCH_ = 0 or VDD±0.01±1µA
Input Capacitance16pF
INTERNAL REFERENCE (MAX149 Only, Reference Buffer Enabled)
VREF Output VoltageTA = +25°C (Note 7)2.4702.5002.530V
VREF Short-Circuit Current30mA
VREF Temperature CoefficientMAX149±30ppm/°C
Load Regulation (Note 8)0 to 0.2mA output load0.35mV
Capacitive Bypass at VREFInternal compensation mode0µFExternal compensation mode4.7
Capacitive Bypass at REFADJ0.01µF
REFADJ Adjustment Range±1.5%
EXTERNAL REFERENCE AT VREF (Buffer Disabled)
VREF Input Voltage Range
(Note 9)1.0VDD +
50mVV
VREF Input CurrentVREF = 2.500V100150µA
VREF Input Resistance1825kΩ
Shutdown VREF Input Current0.0110µA
REFADJ Buffer-Disable ThresholdVDD -
0.5V
EXTERNAL REFERENCE AT REFADJ
Capacitive Bypass at VREFInternal compensation mode0µFExternal compensation mode4.7
Reference Buffer GainMAX1492.06V/VMAX1482.00
REFADJ Input CurrentMAX149±50µAMAX148±10
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7FF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless
otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
DIN, SCLK, CS Input High VoltageVIHVDD ≤ 3.6V2.0VVDD > 3.6V3.0
DIN, SCLK, CS Input Low VoltageVIL0.8V
DIN, SCLK, CS Input HysteresisVHYST0.2V
DIN, SCLK, CS Input LeakageIINVIN = 0 or VDD±0.01±1µA
DIN, SCLK, CS Input CapacitanceCIN(Note 10)15pF
SHDN Input High VoltageVSHVDD -
0.4V
SHDN Input Mid VoltageVSM1.1VDD -
1.1V
SHDN Input Low VoltageVSL0.4V
SHDN Input CurrentISSHDN = 0 or VDD±4.0µA
SHDN Voltage, UnconnectedVFLTSHDN = unconnectedVDD/2V
SHDN Maximum Allowed
Leakage, Mid InputSHDN = unconnected±100nA
DIGITAL OUTPUTS (DOUT, SSTRB)
Output-Voltage LowVOLISINK = 5mA0.4VISINK = 16mA0.8
Output-Voltage HighVOHISOURCE = 0.5mAVDD -
0.5V
Three-State Leakage CurrentILCS = VDD±0.01±10µA
Three-State Output CapacitanceCOUTCS = VDD (Note 10)15pF
POWER REQUIREMENTS
Positive Supply VoltageVDD2.705.25V
Positive Supply CurrentIDD
Operating mode, full-scale
input (Note 11)
VDD = 5.25V1.63.0mAVDD = 3.6V1.22.0
Full power-downVDD = 5.25V3.515VDD = 3.6V1.210
Fast power-down (MAX149)3070
Supply Rejection (Note 12)PSRFull-scale input, external reference =
2.500V, VDD = 2.7V to 5.25V±0.3mV
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300FVP-P.
Note 10: Guaranteed by design. Not subject to production testing.
Note 11: The MAX148 typically draws 400FA less than the values shown.
Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Acquisition TimetACQ1.5µs
DIN to SCLK SetuptDS100ns
DIN to SCLK HoldtDH0ns
SCLK Fall to Output Data ValidtDOFigure 1, MAX14_ _C/E20200ns
CS Fall to Output EnabletDVFigure 1240ns
CS Rise to Output DisabletTRFigure 2240ns
CS to SCLK Rise SetuptCSS100ns
CS to SCLK Rise HoldtCSH0ns
SCLK Pulse Width HightCH200ns
SCLK Pulse Width LowtCL200ns
SCLK Fall to SSTRBtSSTRBFigure 1240ns
CS Fall to SSTRB Output EnabletSDVExternal clock mode only, Figure 1240ns
CS Rise to SSTRB Output DisabletSTRExternal clock mode only, Figure 2240ns
SSTRB Rise to SCLK RisetSCKInternal clock mode only (Note 7)0ns
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25NC, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. CODE
MAX148-MAX149 toc01
CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX148-MAX149 toc02
SUPPLY VOLTAGE (V)
INL (LSB)
MAX149
MAX148
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX148-MAX149 toc03
TEMPERATURE (NC)
INL (LSB)
MAX149
MAX148
VDD = 2.7V
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX148-MAX149 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
RL = J
CODE = 1010101000
MAX149
MAX148
CLOAD = 50pF
CLOAD = 20pF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX148-MAX149 toc05
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
FULL POWER-DOWN
MAX149 INTERNAL REFERENCE
VOLTAGE vs. SUPPLY VOLTAGE
MAX148-MAX149 toc06
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX148-MAX149 toc07
TEMPERATURE (NC)
SUPPLY CURRENT (mA)
RL0AD = J
CODE = 1010101000
MAX149
MAX148
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX148-MAX149 toc08
TEMPERATURE (NC)
SHUTDOWN CURRENT (mA)
MAX149 INTERNAL REFERENCE
VOLTAGE vs. TEMPERATURE
MAX148-MAX149 toc09
TEMPERATURE (NC)
INTERNAL REFERENCE VOLTAGE (V)
VDD = 5.25V
VDD = 2.7V
VDD = 3.6V
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Pin Description
PINNAMEFUNCTION
1–8CH0–CH7Sampling Analog InputsCOMGround Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5 LSB.SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation
mode.VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.REFADJInput to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.AGNDAnalog GroundDGNDDigital GroundDOUT Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin
the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high
(external clock mode).DINSerial-Data Input. Data is clocked in at SCLK’s rising edge.CSActive-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.SCLKSerial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed (duty cycle must be 40% to 60%).VDDPositive Supply Voltage
a) HIGH-Z TO VOH AND VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
DGND
6kI
VDD
DGND
DOUT
6kI
CLOAD
50pF
CLOAD
50pF
b) VOL TO HIGH-Z a) VOH TO HIGH-Z
DOUT
DGND
6kICLOAD
50pF
VDD
DOUT
DGND
6kI
CLOAD
50pF
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Detailed Description
The MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (FPs). Figure 3 is a block diagram of the MAX148/
MAX149.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit (Figure
4). In single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following
pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7.
Configure the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain stable
within Q0.5 LSB (Q0.1 LSB for best results) with respect
to AGND during a conversion. To accomplish this, con-
nect a 0.1FF capacitor from IN- (the selected analog
input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acquisi-
tion interval, the T/H switch opens, retaining charge on
CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0 within
the limits of 10-bit resolution. This action is equivalent to
transferring a 16pF x [(VIN+) - (VIN-)] charge from CHOLD
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+, and
CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
SHDN
SCLK
DIN
CH01
INPUT
SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
ANALOG
INPUT
MUX
CLOCK10+2-BIT
SAR
ADC
+1.21V
REFERENCE
(MAX149)
REF
OUT
T/H
CONTROL
LOGIC
INT
CLOCK17
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DOUT
SSTRB
VDD
DGND
AGND
+2.500V
20kΩ
*A ≈ 2.00 (MAX148)
A ≈ 2.06*
REFADJ
VREF
MAX148
MAX149
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
CAPACITIVE DAC
CSWITCH
TRACK
T/H
SWITCH
RIN
9kΩ
CHOLD
HOLD
VREF
ZERO
16pF
INPUT
MUX-+
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ = 7 x (RS + RIN) x 16pF
where RIN = 9kI, RS = the source impedance of the
input signal, and tACQ is never less than 1.5Fs. Note that
source impedances below 4kI do not significantly affect
the ADC’s AC performance.
Higher source impedances can be used if a 0.01FF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with
the input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate
by using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 2mA.
Quick Look
To quickly evaluate the MAX148/MAX149’s analog per-
formance, use the circuit of Figure 5. The MAX148/
MAX149 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in
control bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In external
clock mode, the SSTRB output pulses high for one clock
period before the most significant bit of the conversion
result is shifted out of DOUT. Varying the analog input to
CH7 will alter the sequence of bits from DOUT. A total of
15 clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
Figure 5. Quick-Look Circuit
MAX148
MAX149
0.1µF
VDD
DGND
AGND
COM
SCLK
DIN
DOUT
SSTRB
+3V
N.C.
0.01µF
CH7
+3VREFADJ
VREFC1
0.1µF
0 TO
+2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1CH2CH3CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
+3V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
2.5V
1000pF
COMP
VOUT
+3V
MAX872
SHDN
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Table 1. Control-Byte Format
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
How to Start a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 are compatible with SPI/QSPI and
MICROWIRE devices. For SPI, select the correct clock
polarity and sampling edge in the SPI control registers:
set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and
QSPI all transmit a byte and receive a byte at the same
time. Using the Typical Operating Circuit, the simplest
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
conversion result). See Figure 20 for MAX148/ MAX149
QSPI connections.
BIT 7
(MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(LSB)
STARTSEL2SEL1SEL0UNI/BIPSGL//DIFPD1PD0
BITNAMEDESCRIPTION
7(MSB)STARTThe first logic “1” bit after CS goes low defines the beginning of the control byte.
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3) UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from
-VREF/2 to +VREF/2.SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).PD1Selects clock and power-down modes.
0(LSB)PD0
PD1PD0Mode0Full power-down1Fast power-down (MAX149 only)0Internal clock mode1External clock mode
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7COM00+-00+-01+-01+-10+-10+-11+-11+-
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK P 2MHz)
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull CS
low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB3.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three
trailing zeros. The total conversion time is a function of
the serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120Fs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the fall-
ing edge of SCLK in MSB-first format.
Clock Modes
The MAX148/MAX149 may use either an external serial
clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the exter-
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH700+-01+-10+-11+-00-+01-+10-+11-+4812162024
START
SEL2SEL1SEL0UNI/
BIP
SGL/
DIFPD1PD0
MSBB8B7B6B5B4B3B2B1S0S1B0
LSB
FILLED WITH
ZEROS
RB1RB2
IDLECONVERSION
RB3
ACQUISITION
(fSCLK = 2MHz)
IDLE1.5Fs
SCLK
tACQ
DIN
SSTRB
DOUT
A/D STATE
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
The T/H acquires the input signal as the last three bits of
the control byte are clocked into DIN. Bits PD1 and PD0
of the control byte program the clock mode. Figures 7–10
show the timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive- approxi-
mation bit decisions are made and appear at DOUT on
and DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic-low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time, or
droop on the sample-and-hold capacitors may degrade
conversion results. Use internal clock mode if the serial-
clock frequency is less than 100kHz, or if serial-clock
interruptions could cause the conversion interval to
exceed 120Fs.
tDO
SCLK
DIN
DOUT
tCSS
tDS
tDH
tDVtTR
tCSHtCL
tCHtCSH
PD0 CLOCKED IN
SCLK
tSSTRB
SSRTB
tSDVtSTR
tSSTRB
