MAX149ACAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsGeneral Description ________
MAX149ACAP+ ,+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0; f = 2.0MHz; external clock (50% duty cycle ..
MAX149AEAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsELECTRICAL CHARACTERISTICSV = +2.7V to +5.25V; COM = 0V; f = 2.0MHz; external clock (50% duty cycle ..
MAX149BCAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsMAX148/MAX14919-0464; Rev 2; 5/98+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
MAX149BEAP ,+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCsMAX148/MAX14919-0464; Rev 2; 5/98+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
MAX149BEAP+ ,+2.7V to +5.25V Low-Power 8-Channel Serial 10-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0; f = 2.0MHz; external clock (50% duty cycle ..
MAX4122EUK ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS (continued)(V = +2.7V to +6.5V, V = 0V, V = 0V, V = V /2, R tied to V /2 ..
MAX4122EUK+T ,Single/Dual/Quad, Wide-Bandwidth, Low-Power, Single-Supply Rail-to-Rail I/O Op AmpsMAX4122–MAX412919-1087; Rev 1; 8/97Single/Dual/Quad, Wide-Bandw idth, Low -Pow er,Single-Supply Rai ..
MAX4122EUK-T ,Single/Dual/Quad, Wide-Bandwidth, Low-Power, Single-Supply Rail-to-Rail I/O Op AmpsFeaturesThe MAX4122–MAX4129 family of operational amplifiers♦ 5-Pin SOT23 Package (MAX4122/4)combin ..
MAX4123ESA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsApplicationsMAX4123C/D 0°C to +70°C Dice* —Battery-Powered InstrumentsMAX4123ESA -40°C to +85°C 8 S ..
MAX4123EUA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsMAX4122–MAX412919-1087; Rev 1; 8/97Single/Dual/Quad, Wide-Bandwidth, Low-Power,Single-Supply Rail-t ..
MAX4123EUA ,Single/Dual/Quad / Wide-Bandwidth / Low-Power / Single-Supply Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS (V = +2.7V to +6.5V, V = 0V, V = 0V, V = V /2, R tied to V /2, SHDN ‡ 2V ..
MAX148ACAP-MAX148AEAP-MAX148BCAP-MAX148BCPP-MAX148BEAP-MAX149ACAP-MAX149AEAP-MAX149BCAP-MAX149BEAP
+2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs
General DescriptionThe MAX148/MAX149 10-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from a
single +2.7V to +5.25V supply, and sample to 133ksps.
Both devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial-strobe output allows direct connection to
TMS320-family digital signal processors. The MAX148/
MAX149 use either the internal clock or an external serial-
interface clock to perform successive-approximation
analog-to-digital conversions.
The MAX149 has an internal 2.5V reference, while the
MAX148 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX148/MAX149, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX148/MAX149 are available in a 20-pin DIP and a
20-pin SSOP.
For 4-channel versions of these devices, see the
MAX1248/MAX1249 data sheet.
________________________ApplicationsPortable Data LoggingData Acquisition
Medical InstrumentsBattery-Powered Instruments
Pen DigitizersProcess Control
____________________________Features8-Channel Single-Ended or 4-Channel
Differential InputsSingle-Supply Operation: +2.7V to +5.25V Internal 2.5V Reference (MAX149)Low Power:1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
MAX148/MAX149,Low-Power, 8-Channel,
Serial 10-Bit ADCs
__________Typical Operating Circuit
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc. MICROWIREis a trademark of National Semiconductor Corp.
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICSVDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMINto TMAX;unless
otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND.................................................-0.3V to 6V
AGND to DGND......................................................-0.3V to 0.3V
CH0–CH7, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF, REFADJ to AGND...........................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................................-0.3V to 6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX148_C_P/MAX149_C_P..............................0°C to +70°C
MAX148_E_P/MAX149_E_P............................-40°C to +85°C
MAX148_MJP/MAX149_MJP........................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)VDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMINto TMAX;unless
otherwise noted.)
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)VDD= +2.7V to +5.25V; COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX149—4.7µF capacitor at VREF pin; MAX148—external reference, VREF = 2.500V applied to VREF pin; TA= TMINto TMAX;unless
otherwise noted.)
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
__________________________________________Typical Operating Characteristics(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS(VDD= +2.7V to +5.25V, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Sample tested to 0.1% AQL.
Note 8:External load should not change during conversion for specified accuracy.
Note 9:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note10:Guaranteed by design. Not subject to production testing.
Note11:The MAX148 typically draws 400µA less than the values shown.
Note12:Measured as |VFS(2.7V) - VFS(5.25V)|.
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
______________________________________________________________Pin DescriptionFigure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable Time
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
_______________Detailed DescriptionThe MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX148/
MAX149.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN-(the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor CHOLD.
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
acquisition interval, the T/H switch opens, retaining
charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 10-bit resolution. This action is equiv-
alent to transferring a 16pF x [(VIN+) -(VIN-)] charge
from CHOLDto the binary-weighted capacitive DAC,
which in turn forms a digital representation of the analog
input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCsFigure 5.Quick-Look Circuit
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
How to Start a ConversionStart a conversion by clocking a control byte into DIN.
With CSlow, each rising edge on SCLK clocks a bit from
DIN into the MAX148/MAX149’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX148/MAX149 are compatible with SPI/
QSPI and MICROWIREdevices. For SPI, select the cor-
rect clock polarity and sampling edge in the SPI control
registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SPI, and QSPI all transmit a byte and receive a byte at
the same time.Using the Typical Operating Circuit,the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to clock
out the conversion result). See Figure 20 for MAX148/
MAX149QSPI connections.
Table 1.Control-Byte Format
Table 2.Channel Selection in Single-Ended Mode (SGL/DDIIFF
= 1)
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three trail-
ing zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock Modes
The MAX148/MAX149 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
Figure 6.24-Clock External Clock Mode Conversion Timing (MICROWIREand SPI-Compatible, QSPI-Compatible with fSCLK ≤2MHz)
Table 3.Channel Selection in Differential Mode (SGL/DDIIFF
= 0)
MAX148/MAX149
+2.7Vto +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CSgoes high; after the next CSfalling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
Internal Clock
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the µP
Figure 8.External Clock Mode SSTRBDetailed Timing
Figure 7.Detailed Serial-Interface Timing
