MAX1471ATJ+ ,315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne ReceiverApplications *0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BWAutomotive Remote Keyless Entry ..
MAX1472AKA ,300MHz-to-450MHz Low-Power, Crystal-Based ASK TransmitterELECTRICAL CHARACTERISTICS(Typical Application Circuit, output power is referenced to 50Ω , V = 2.1 ..
MAX1472AKA+T ,300MHz-to-450MHz Low-Power, Crystal-Based ASK TransmitterApplicationsOrdering InformationRemote Keyless EntryTEMP PIN- TOPPARTRANGE PACKAGE MARKRF Remote Co ..
MAX1472AKA+T ,300MHz-to-450MHz Low-Power, Crystal-Based ASK TransmitterFeaturesThe MAX1472 is a crystal-referenced phase-locked♦ 2.1V to 3.6V Single-Supply Operationloop ..
MAX1472AKA-T ,300MHz-to-450MHz Low-Power / Crystal-Based ASK TransmitterELECTRICAL CHARACTERISTICS(Typical Application Circuit, output power is referenced to 50Ω , V = 2.1 ..
MAX1472AKA-T10 ,300MHz-to-450MHz Low-Power, Crystal-Based ASK TransmitterMAX147219-2872; Rev 4; 6/12300MHz-to-450MHz Low-Power, Crystal-Based ASK Transmitter
MAX4053ACEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesFeaturesThe MAX4051/MAX4052/MAX4053 and MAX4051A/ ♦ Pin Compatible with Industry-Standard MAX4052A/ ..
MAX4053ACEE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4053ACPE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4053ACSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX4053ACSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4053ACSE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX1471ATJ+
315MHz/434MHz Low-Power, 3V/5V ASK/FSK Superheterodyne Receiver
General DescriptionThe MAX1471 low-power, CMOS, superheterodyne, RF
dual-channel receiver is designed to receive both ampli-
tude-shift-keyed (ASK) and frequency-shift-keyed (FSK)
data without reconfiguring the device or introducing any
time delay normally associated with changing modula-
tion schemes. The MAX1471 requires few external com-
ponents to realize a complete wireless RF digital data
receiver for the 300MHz to 450MHz ISM bands.
The MAX1471 includes all the active components
required in a superheterodyne receiver including: a low-
noise amplifier (LNA), an image-reject (IR) mixer, a fully
integrated phase-locked loop (PLL), local oscillator
(LO), 10.7MHz IF limiting amplifier with received-signal-
strength indicator (RSSI), low-noise FM demodulator,
and a 3V voltage regulator. Differential peak-detecting
data demodulators are included for both the FSK and
ASK analog baseband data recovery. The MAX1471
includes a discontinuous receive (DRX) mode for low-
power operation, which is configured through a serial
interface bus.
The MAX1471 is available in a 32-pin thin QFN package
and is specified over the automotive -40°C to +125°C
temperature range.
ApplicationsAutomotive Remote Keyless Entry (RKE)
Tire Pressure Monitoring Systems
Garage Door Openers
Wireless Sensors
Wireless Keys
Security Systems
Medical Systems
Home Automation
Local Telemetry Systems
FeaturesASK and FSK Demodulated Data on Separate
OutputsSpecified over Automotive -40°C to +125°C
Temperature Range Low Operating Supply Voltage Down to 2.4VOn-Chip 3V Regulator for 5V OperationLow Operating Supply Current
7mA Continuous Receive Mode
1.1µA Deep-Sleep ModeDiscontinuous Receive (DRX) Low-Power
ManagementFast-On Startup Feature < 250µsIntegrated PLL, VCO, and Loop Filter45dB Integrated Image RejectionRF Input Sensitivity*
ASK: -114dBm
FSK: -108dBmSelectable IF BW with External FilterProgrammable Through Serial User InterfaceRSSI Output and High Dynamic Range with AGC
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver+313029282726101112131415
MAX1471
THIN QFNTOP VIEW
DSA+
DSA-
OPA+
DFA
XTAL2
XTAL1
AVDDLNAIN
PDMAXAPDMINAADA
HVINSCLKDIO
FDA
DVDD
DGND
DFF
OPF+
DSF+
DSF-
PDMAXFPDMINF
IFIN-
AGND
IFIN+
MIXOUT
MIXIN-
MIXIN+
LNAOUTLNASRC
Pin Configuration19-3272; Rev 4; 9/11
*0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BW
Ordering Information
PARTTEMP RANGEPIN-PACKAGE MAX1471ATJ/V+ -40°C to +125°C 32 Thin QFN-EP**
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
**EP = Exposed pad.
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
High-Voltage Supply, HVIN to DGND......................-0.3V, +6.0V
Low-Voltage Supply, AVDD and DVDD to AGND....-0.3V, +4.0V
SCLK, DIO, CS, ADATA,
FDATA...................................(DGND - 0.3V) to (HVIN + 0.3V)
All Other Pins............................(AGND - 0.3V) to (AVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN (derate 21.3mW/°C above +70°C)...1702mW
Operating Temperature Range.........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)......................................+260°C
DC ELECTRICAL CHARACTERISTICS(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless other-
wise noted. Typical values are at VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICSSupply Voltage (5V)HVINAVDD and DVDD unconnected from HVIN,
but connected together4.55.05.5V
Supply Voltage (3V)VDDHVIN, AVDD, and DVDD connected to
power supply2.43.03.6V
Operating7.08.4mA
Polling duty cycle: 10%
duty cycle705855
DRX mode OFF current5.014.2
TA < +85°C
Deep-sleep current1.17.1
Operating8.5mA
Polling duty cycle: 10%
duty cycle865
DRX mode OFF current15.5
TA < +105°C
(Note 2)
Deep-sleep current13.4
Operating8.6mA
Polling duty cycle: 10%
duty cycle900
DRX mode OFF current44.1
Supply CurrentIDD
TA < +125°C
(Note 2)
Deep-sleep current36.4
Startup TimetONTime for final signal detection, does not
include baseband filter settling (Note 2)200250µs
DIGITAL OUTPUTS (DIO, ADATA, FDATA)Output High VoltageVOHISOURCE = 250µA (Note 2)VHVIN -
0.15V
Output Low VoltageVOLISINK = 250µA (Note 2)0.15V
DIGITAL INPUTS (CS, DIO, SCLK)Input High ThresholdVIH0.9 x
VHVINV0.1 x
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
DC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless other-
wise noted. Typical values are at VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput-High Leakage CurrentIIH(Note 2)-20µA
Input-Low Leakage CurrentIIL(Note 2)20µA
Input CapacitanceCIN(Note 2)2.0pF
VOLTAGE REGULATOROutput VoltageVREGVHVIN = 5.0V, ILOAD = 7.0mA3.0V
AC ELECTRICAL CHARACTERISTICS(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless other-
wise noted. Typical values are at VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
GENERAL CHARACTERISTICSASK-114
Receiver SensitivityRFIN
0.2% BER, 4kbps
Manchester Code, 280kHz
IF BW, 50ΩFSK-108
dBm
Maximum Receiver Input Power
LevelRFMAX0dBm
Receiver Input Frequency RangefRF300450MHz
Receiver Image RejectionIR(Note 3)45dB
LNA/MIXER (Note 4)fRF = 315MHz1 - j4.7LNA Input ImpedanceZIN_LNANormalized to 50ΩfRF = 434MHz1 - j3.4
Voltage Conversion Gain (High-
Gain Mode)47.5dB
Input-Referred 3rd-Order
Intercept Point (High-Gain Mode)-38dBm
Voltage Conversion Gain (Low-
Gain Mode)12.2dB
Input-Referred 3rd-Order
Intercept Point (Low-Gain Mode)-5dBm
LO Signal Feedthrough to
Antenna-90dBm
Mixer Output ImpedanceZOUT_MIX330Ω
Input ImpedanceZIN_IF330Ω
Operating FrequencyfIF10.7MHz
3dB Bandwidth10MHz
FM DEMODULATORDemodulator GainGFM2.2mV/kHz
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
AC ELECTRICAL CHARACTERISTICS (continued)(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless other-
wise noted. Typical values are at VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG BASEBANDMaximum Data Filter BandwidthBWDF50kHz
Maximum Data Slicer BandwidthBWDS100kHz
Maximum Peak Detector
BandwidthBWPD50kHz
Manchester coded33Maximum Data RateNonreturn to zero (NRZ)66kbps
CRYSTAL OSCILLATORCrystal FrequencyfXTAL9.0413.728MHz
Frequency Pulling by VDD3ppm/V
Crystal Load Capacitance3pF
DIGITAL INTERFACE TIMING (see Figure 8)Minimum SCLK Setup to Falling
Edge of CStSC30ns
Minimum CS Falling Edge to
SCLK Rising-Edge Setup TimetCSS30ns
Minimum CS Idle TimetCSI125ns
Minimum CS PeriodtCS2.125µs
Maximum SCLK Falling Edge to
Data Valid DelaytDO80ns
Minimum Data Valid to SCLK
Rising-Edge Setup TimetDS30ns
Minimum Data Valid to SCLK
Rising-Edge Hold TimetDH30ns
Minimum SCLK High Pulse WidthtCH100ns
Minimum SCLK Low Pulse WidthtCL100ns
Minimum CS Rising Edge to
SCLK Rising-Edge Hold TimetCSH30ns
Maximum CS Falling Edge to
Output Enable TimetDV25ns
Maximum CS Rising Edge to
Output Disable TimetTR25ns
Note 1:Production tested at TA= +85°C. Guaranteed by design and characterization over entire temperature range.
Note 2:Guaranteed by design and characterization. Not production tested.
Note 3:The oscillator register (0x3) is set to the nearest integer result of fXTAL/ 100kHz (see the Oscillator Frequency Registersection).
Note 4:Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration
from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50Ωin series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF fil-
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne ReceiverSUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1471 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
+125°C+105°C
+85°C
+25°C
-40°C
SUPPLY CURRENT
vs. RF FREQUENCY
MAX1471 toc02
RF FREQUENCY (MHz)
SUPPLY CURRENT (mA)
+125°C
-40°C
+25°C
+105°C+85°C
DEEP-SLEEP CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
DEEP-SLEEP CURRENT (
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (ASK DATA)
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)0.2% BER
fRF = 434MHz
fRF = 315MHz
280kHz IF BW100
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (FSK DATA)
AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE0.2% BER
fRF = 434MHz
fRF = 315MHz
280kHz IF BW
FREQUENCY DEVIATION = ±50kHz
SENSITIVITY
vs. TEMPERATURE (ASK DATA)
TEMPERATURE (°C)
SENSITIVITY (dBm)
280kHz IF BW
0.2% BER
fRF = 434MHz
fRF = 315MHz
SENSITIVITY
vs. TEMPERATURE (FSK DATA)
SENSITIVITY (dBm)
280kHz IF BW
0.2% BER
fRF = 434MHz
fRF = 315MHz
FREQUENCY DEVIATION = ±50kHz
SENSITIVITY vs. FREQUENCY
DEVIATION (FSK DATA)
SENSITIVITY (dBm)
280kHz IF BW
0.2% BER
RSSI vs. RF INPUT POWERRSSI (V)
AGC HYSTERESIS: 3dB
HIGH-GAIN MODE
LOW-GAIN MODE
AGC SWITCH
POINT
Typical Operating Characteristics(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne ReceiverRSSI AND DELTA vs. IF INPUT POWER
MAX1471 toc10
RF INPUT POWER (dBm)
RSSI (V)
DELTA (%)
RSSI
DELTA
FSK DEMODULATOR OUTPUT
vs. IF FREQUENCY
MAX1471 toc11
IF FREQUENCY (MHz)
FSK DEMODULATOR OUTPUT (V)
SYSTEM VOLTAGE GAIN
vs. IF FREQUENCY
MAX1471 toc12
IF FREQUENCY (MHz)
SYSTEM GAIN (dB)
45dB IMAGE
REJECTION
UPPER SIDEBAND
LOWER SIDEBAND
FROM RFIN
TO MIXOUT
fRF = 434MHz
IMAGE REJECTION
vs. TEMPERATURE
MAX1471 toc13
TEMPERATURE(°C)
IMAGE REJECTION (dB)
fRF = 315MHz
fRF = 434MHz
NORMALIZED IF GAIN
vs. IF FREQUENCY
MAX1471 toc14
IF FREQUENCY (MHz)
NORMALIZED IF GAIN (dBm)
-1010dB/
div
START: 50MHzSTOP: 1GHz
S11 LOG-MAGNITUDE PLOT WITH
MATCHING NETWORK OF RFIN (434MHz)MAX1471 toc15
0dB0dB
434MHz
-16.4dB
S11 SMITH CHART OF RFIN (434MHz)MAX1471 toc16
500MHz
200MHz
ypical Operating Characteristics (continued)(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
INPUT IMPEDANCE vs. INDUCTIVE
DEGENERATIONMAX1471 toc17
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (100
fRF = 315MHz
L1 = 0nH
IMAGINARY IMPEDANCE
REAL IMPEDANCE-325
IMAGINARY IMPEDANCE (
INPUT IMPEDANCE vs. INDUCTIVE
DEGENERATIONMAX1471 toc18
INDUCTIVE DEGENERATION (nH)
REAL IMPEDANCE (100
fRF = 434MHz
L1 = 0nH
IMAGINARY
IMPEDANCE
IMAGINARY IMPEDANCE (
REAL IMPEDANCE
1001k1M10M
PHASE NOISE vs. OFFSET FREQUENCYMAX1471 toc19
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
10k100k
fRF = 315MHz-50
1001k1M10M
PHASE NOISE vs. OFFSET FREQUENCYMAX1471 toc20
OFFSET FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
10k100k
fRF = 434MHz
ypical Operating Characteristics (continued)(Typical Application Circuit, VAVDD= VDVDD= VHVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)
PINNAMEFUNCTIONDSA-Inverting Data Slicer Input for ASK DataDSA+Noninverting Data Slicer Input for ASK DataOPA+Noninverting Op-Amp Input for the ASK Sallen-Key Data FilterDFAData-Filter Feedback Node. Input for the feedback of the ASK Sallen-Key data filter.XTAL22nd Crystal Input
Pin Description
MAX1471
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
PINNAMEFUNCTIONXTAL11st Crystal InputAVDDAnalog Power-Supply Voltage for RF Sections. AVDD is connected to an on-chip +3.0V low-dropout
regulator. Decouple to AGND with a 0.1µF capacitor.LNAINLow-Noise Amplifier InputLNASRCLow-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to AGND to set
LNA input impedance.LNAOUTLow-Noise Amplifier Output. Connect to mixer through an LC tank filter.MIXIN+Differential Mixer Input. Must be AC-coupled to driving input.MIXIN-Differential Mixer Input. Bypass to AGND with a capacitor.MIXOUT330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter.AGNDAnalog GroundIFIN-Differential 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor.IFIN+Differential 330Ω IF Limiter Amplifier Input. Connect to output of the 10.7MHz IF filter.PDMINFMinimum-Level Peak Detector for FSK Data. Connect to ground if peak detector is not used. See the
Peak Detectors section.PDMAXFMaximum-Level Peak Detector for FSK Data. Connect to ground if peak detector is not used. See the
Peak Detectors section.DSF-Inverting Data Slicer Input for FSK DataDSF+Noninverting Data Slicer Input for FSK DataOPF+Noninverting Op-Amp Input for the FSK Sallen-Key Data FilterDFFData-Filter Feedback Node. Input for the feedback of the FSK Sallen-Key data filter.DGNDDigital GroundDVDDDigital Power-Supply Voltage for Digital Sections. Connect to AVDD. Decouple to DGND with a 10nF
capacitor.FDATADigital Baseband FSK Demodulator Data OutputCSActive-Low Chip-Select InputDIOSerial Data Input/OutputSCLKSerial Interface Clock InputHVINHigh-Voltage Supply Input. For 3V operation, connect HVIN to AVDD and DVDD.ADATADigital Baseband ASK Demod Data OutputPDMINAMinimum-Level Peak Detector for ASK Output. Connect to ground if peak detector is not used. See the
Peak Detectors section.PDMAXAMaximum-Level Peak Detector for ASK Output. Connect to ground if peak detector is not used. See the
Peak Detectors section.EPExposed Pad. Connect to ground.
Pin Description (continued)
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne ReceiverFSK
DEMODULATOR
RSSI
90°
VCODIVIDE
BY 32
PHASE
DETECTOR
CRYSTAL
OSCILLATOR
SERIAL INTERFACE,
CONTROL REGISTERS,
AND POLLING TIMER
LOOP
FILTER
LNA
3.0V
REG
3.0VDFAOPA+DSA+PDMINAPDMAXADSA-ADATALNAINLNASRCXTAL1AGNDXTAL2DIOSCLKDGNDHVIN
AVDD7
LNAOUT
MIXIN+
MIXIN-
MIXOUT
IFIN-
IFIN+
FDATA
DSF-
PDMAXF
PDMINF
DSF+
OPF+
DFF
DVDD
IF LIMITING
AMPS
ASK DATA FILTER
FSK DATA
FILTER
IMAGE
REJECTION
ASK
FSK
RDF1
100kΩ
RDF2
100kΩ
RDF1
100kΩ
RDF2
100kΩ
MAX1471
Functional Diagram
MAX1471
Detailed DescriptionThe MAX1471 CMOS superheterodyne receiver and a
few external components provide a complete ASK/FSK
receive chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps using Manchester Code
(66kbps nonreturn to zero) can be achieved.
The MAX1471 is designed to receive binary FSK or
ASK data on a 300MHz to 450MHz carrier. ASK modu-
lation uses a difference in amplitude of the carrier to
represent logic 0 and logic 1 data. FSK uses the differ-
ence in frequency of the carrier to represent a logic 0
and logic 1.
Low-Noise Amplifier (LNA)The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 28dB of volt-
age gain that is dependent on both the antenna-match-
ing network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by con-
necting an inductor from LNASRC to AGND. This induc-
tor sets the real part of the input impedance at LNAIN,
allowing for a flexible match to low input impedances
such as a PCB trace antenna. A nominal value for this
inductor with a 50Ωinput impedance is 15nH at
315MHz and 10nH at 434MHz, but the inductance is
affected by PCB trace length. See the Typical
Operating Characteristicsto see the relationship
between the inductance and input impedance. The
inductor can be shorted to ground to increase sensitivi-
ty by approximately 1dB, but the input match is not
optimized for 50Ω.
The LC tank filter connected to LNAOUT comprises L2
and C9 (see the Typical Application Circuit). Select L2
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
where LTOTAL= L2 + LPARASITICSand CTOTAL= C9 +
CPARASITICS.
LPARASITICSand CPARASITICSinclude inductance and
capacitance of the PCB traces, package pins, mixer
input impedance, LNA output impedance, etc. These
parasitics at high frequencies cannot be ignored, and
can have a dramatic effect on the tank filter center fre-
quency. Lab experimentation should be done to opti-
mize the center frequency of the tank.
Automatic Gain Control (AGC)When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -64dBm,
the AGC switches on the LNA gain reduction attenuator.
The attenuator reduces the LNA gain by 35dB, thereby
reducing the RSSI output by about 0.55V. The LNA
resumes high-gain mode when the RSSI output level
drops back below 0.68V (approximately -67dBm at the
RF input) for a programmable interval called the AGC
dwell time. The AGC has a hysteresis of approximately
3dB. With the AGC function, the RSSI dynamic range is
increased, allowing the MAX1471 to reliably produce an
ASK output for RF input levels up to 0dBm with a modu-
lation depth of 18dB. AGC is not necessary and can be
disabled when utilizing only the FSK data path.
The MAX1471 features an AGC lock controlled by the
AGC lock bit (see Table 8). When the bit is set, the LNA
is locked in its present gain state.
MixerA unique feature of the MAX1471 is the integrated
image rejection of the mixer. This device was designed
to eliminate the need for a costly front-end SAW filter for
many applications. The advantage of not using a SAW
filter is increased sensitivity, simplified antenna match-
ing, less board space, and lower cost.
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., fLO= fRF- fIF). The image-rejection circuit
then combines these signals to achieve approximately
45dB of image rejection. Low-side injection is required
as high-side injection is not possible due to the on-chip
image rejection. The IF output is driven by a source fol-
lower, biased to create a driving impedance of 330Ωto
interface with an off-chip 330Ωceramic IF filter. The
voltage conversion gain driving a 330Ωload is approxi-
mately 19.5dB. Note that the MIXIN+ and MIXIN- inputs
are functionally identical.
Phase-Locked Loop (PLL)The PLL block contains a phase detector, charge
pump/integrated loop filter, voltage-controlled oscillator
(VCO), asynchronous 32x clock divider, and crystal
oscillator. This PLL does not require any external com-
ponents. The relationship between the RF, IF, and refer-
ence frequencies is given by:
fREF= (fRF- fIF)/32
To allow the smallest possible IF bandwidth (for best sen-
sitivity), the tolerance of the reference must be minimized.TOTALTOTAL×
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Intermediate Frequency (IF)The IF section presents a differential 330Ωload to pro-
vide matching for the off-chip ceramic filter. It contains
five AC-coupled limiting amplifiers with a bandpass-fil-
ter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi-
mately 16mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF.
FSK DemodulatorThe FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and determines the
difference between frequencies as logic-level ones and
zeros. The PLL is illustrated in Figure 1. The input to the
PLL comes from the output of the IF limiting amplifiers.
The PLL control voltage responds to changes in the fre-
quency of the input signal with a nominal gain of
2.2mV/kHz. For example, an FSK peak-to-peak devia-
tion of 50kHz generates a 110mVP-Psignal on the con-
trol line. This control line is then filtered and sliced by
the FSK baseband circuitry.
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula-
tor, see the Calibrationsection. The maximum calibra-
tion time is 120µs. In DRX mode, the FSK demodulator
calibration occurs automatically just before the IC
enters sleep mode.
Crystal OscillatorThe XTAL oscillator in the MAX1471 is used to generate
the local oscillator (LO) for mixing with the received sig-
nal. The XTAL oscillator frequency sets the received
signal frequency as:
fRECEIVE= (fXTALx 32) +10.7MHz
The received image frequency at:
fIMAGE= (fXTALx 32) -10.7MHz
is suppressed by the integrated quadrature image-
rejection circuitry.
For an input RF frequency of 315MHz, a reference fre-
quency of 9.509MHz is needed for a 10.7MHz IF fre-
quency (low-side injection is required). For an input RF
frequency of 433.92MHz, a reference frequency of
13.2256MHz is required.
The XTAL oscillator in the MAX1471 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, intro-
ducing an error in the reference frequency. Crystals
designed to operate with higher differential load capac-
itance always pull the reference frequency higher.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
where:is the amount the crystal frequency pulled in ppm.is the motional capacitance of the crystal.
Ccaseis the case capacitance.
Cspecis the specified load capacitance.
Cloadis the actual load capacitance.
When the crystal is loaded as specified, i.e., Cload=
Cspec, the frequency pulling equals zero.C
CCCCpm
caseloadcasespec=+−+⎜⎞⎟×210
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne ReceiverLOOP
FILTER
10.7MHz VCO
2.2mV/kHz
CHARGE
PUMP
PHASE
DETECTOR
IF
LIMITING
AMPS
TO FSK BASEBAND FILTER
AND DATA SLICER
MAX1471
Data FiltersThe data filters for the ASK and FSK data are imple-
mented as a 2nd-order lowpass Sallen-Key filter. The
pole locations are set by the combination of two on-
chip resistors and two external capacitors. Adjusting
the value of the external capacitors changes the corner
frequency to optimize for different data rates. The cor-
ner frequency in kHz should be set to approximately
1.5 times the fastest expected Manchester data rate in
kbps from the transmitter. Keeping the corner frequen-
cy near the data rate rejects any noise at higher fre-
quencies, resulting in an increase in receiver sensitivity.
The configuration shown in Figure 3 can create a
Butterworth or Bessel response. The Butterworth filter
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:
where fCis the desired 3dB corner frequency.
For example, choose a Butterworth filter response withbfa()()()()()()
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Figure 2. Typical Application Circuit
ASK DATA OUT
SCLK
DIO
FSK DATA OUT
MAX1471GND
OUT
DFF22
DSF-19
PDMAXF18
*SEE LAST PARAGRAPH OF
PEAK DETECTORS SECTION
PDMINF17
PDMAXA
PDMINA
ADATA
HVIN
SLCK
DIO26
FDATA
DSA+2
LNASRC
LNAOUT
MIXOUT
AGND
IFIN+
DVDD24
DGND23
C23
VDD
OPF+21
C21
C22
C27
DSF+20
VDD
OPA+3
OPF+21
C21
DSA-1
DFA4
XTAL25
C14
XTAL16C15
AVDD7
VDD
LNAIN
EXPOSED PADRF INPUTL3
MIXIN-
C10
IFIN-
C12
MIXIN+
C11
VDD
C26
3.0VVDD
Choosing standard capacitor values changes CF1to
470pF and CF2to 220pF. In the Typical Application
Circuit, CF1and CF2are named C4 and C3, respective-
ly, for ASK data, and C21 and C22 for FSK data.
Data SlicersThe purpose of a data slicer is to take the analog output
of a data filter and convert it to a digital signal. This is
achieved by using a comparator and comparing the ana-
log input to a threshold voltage. The threshold voltage is
chain (DSF- for the FSK receive chain), which is connect-
ed to the negative input of the data slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
4 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The sizes of R and C affect how fast the threshold
tracks to the analog amplitude. Be sure to keep the cor-
ner frequency of the RC circuit much lower than the
lowest expected data rate.
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configurationkkHzpFkkHzpF()()()()≈()()()()≈00041410031454504141003145225
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Table 1. Component Values for Typical Application Circuit
COMPONENTVALUE FOR 433.92MHz RFVALUE FOR 315MHz RFDESCRIPTION (%)220pF220pF10470pF470pF50.047µF0.047µF100.1µF0.1µF10100pF100pF5100pF100pF51.0pF2.2pF±0.1pF
C10220pF220pF10
C11100pF100pF5
C121500pF1500pF10
C1415pF15pF5
C1515pF15pF5
C21220pF220pF10
C22470pF470pF5
C230.01µF0.01µF10
C260.1µF0.1µF10
C270.047µF0.047µF1056nH100nH5 or better*16nH30nH5 or better*10nH15nH5 or better*25kΩ25kΩ525kΩ25kΩ513.2256MHz9.509MHzCrystek or Hong Kong X’tals10.7MHz ceramic filter10.7MHz ceramic filterMurata SFECV10.7 series
Note:Component values vary depending on PCB layout.
*Wire wound recommended.
