MAX146BCAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0V; f = ..
MAX146BCAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsFeaturesThe MAX146/MAX147 12-bit data-acquisition systems♦ 8-Channel Single-Ended or 4-Channel comb ..
MAX146BCPP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsFeaturesThe MAX146/MAX147 12-bit data-acquisition systems' 8-Channel Single-Ended or 4-Channel comb ..
MAX146BEAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsFeaturesThe MAX146/MAX147 12-bit data-acquisition systems' 8-Channel Single-Ended or 4-Channel comb ..
MAX146BEAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsGeneral Description ________
MAX1470EUI ,315MHz Low-Power / +3V Superheterodyne ReceiverElectrical Characteristics.Wireless SensorsOrdering InformationWireless Computer PeripheralsSecurit ..
MAX4052CSE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesFeaturesThe MAX4051/MAX4052/MAX4053 and MAX4051A/ ♦ Pin Compatible with Industry-Standard MAX4052A/ ..
MAX4052EEE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX4052EEE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4052EPE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4052ESE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 2; 10/05Low-Voltage, CMOS AnalogMultiplexers/Switches
MAX4052ESE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesFeaturesThe MAX4051/MAX4052/MAX4053 and MAX4051A/ ♦ Pin Compatible with Industry-Standard MAX4052A/ ..
MAX146ACAP-MAX146BCAP-MAX146BCPP-MAX146BEAP-MAX147BCAP-MAX147BCPP-MAX147BEAP
+2.7Low-Power, 8-Channel, Serial 12-Bit ADCs
_______________General DescriptionThe MAX146/MAX147 12-bit data-acquisition systems
combine an 8-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX146 oper-
ates from a single +2.7V to +3.6V supply; the MAX147
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320-
family digital signal processors. The MAX146/MAX147
use either the internal clock or an external serial-interface
clock to perform successive-approximation analog-to-
digital conversions.
The MAX146 has an internal 2.5V reference, while the
MAX147 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range.
These devices provide a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a con-
version. Accessing the serial interface automatically
powers up the MAX146/MAX147, and the quick turn-on
time allows them to be shut down between all conver-
sions. This technique can cut supply current to under
60µA at reduced sampling rates.
The MAX146/MAX147 are available in 20-pin DIP and
SSOP packages.
For 4-channel versions of these devices, see the
MAX1246/MAX1247 data sheet.
________________________ApplicationsPortable Data LoggingData Acquisition
Medical InstrumentsBattery-Powered Instruments
Pen DigitizersProcess Control
____________________________Features8-Channel Single-Ended or 4-Channel
Differential InputsSingle-Supply Operation:
+2.7V to +3.6V (MAX146)
+2.7V to +5.25V (MAX147)Internal 2.5V Reference (MAX146)Low Power:1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)SPI/QSPI/Microwire/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
__________Typical Operating CircuitSPI and QSPI are registered trademarks of Motorola, Inc.
Microwire is a registered trademark of National Semiconductor Corp.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND.................................................-0.3V to 6V
AGND to DGND......................................................-0.3V to 0.3V
CH0–CH7, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF, REFADJ to AGND...........................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................................-0.3V to 6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX146_C_P/MAX147_C_P..............................0°C to +70°C
MAX146_E_P/MAX147_E_P............................-40°C to +85°C
MAX146_MJP/MAX147_MJP........................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle); 15
clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500V applied to
VREF pin; TA= TMINto TMAX;unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
__________________________________________Typical Operating Characteristics(VDD= 3.0V, VREF = 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX146); VDD= +2.7V to +5.25V (MAX147); TA= TMINto TMAX; unless otherwise noted.)
Note 1:Tested at VDD= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX146—internal reference, offset nulled; MAX147—external reference (VREF = +2.500V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:External load should not change during conversion for specified accuracy.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Guaranteed by design. Not subject to production testing.
Note10:Measured as |VFS(2.7V) - VFS(VDD, MAX)|.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
____________________________Typical Operating Characteristics (continued)(VDD= 3.0V, VREF= 2.500V, fSCLK= 2.0MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
______________________________________________________________Pin DescriptionFigure 1.Load Circuits for Enable Time
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
_______________Detailed DescriptionThe MAX146/MAX147 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX146/
MAX147.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN-(the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a 16pF x [(VIN+) -
(VIN-)] charge from CHOLDto the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
Figure 3.Block Diagram
Figure 4. Equivalent Input Circuit
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsThe time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ= 9 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5µs. Note
that source impedances below 1kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand AGND, allow the channel input pins to swing
from AGND -0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
Quick LookTo quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
Table 1.Control-Byte Format
Table 2.Channel Selection in Single-Ended Mode (SGL/DIF= 1)
Table 3.Channel Selection in Differential Mode (SGL/DIF= 0)
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCsFigure 6.24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK≤2MHz)
How to Start a ConversionStart a conversion by clocking a control byte into DIN.
With CSlow, each rising edge on SCLK clocks a bit from
DIN into the MAX146/MAX147’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX146/MAX147 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time.Using the Typical Operating
Circuit,the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
20 for MAX146/MAX147 QSPI connections.
Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is two’s
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock ModesThe MAX146/MAX147 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX146/MAX147. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
