MAX1464AAI+ ,Low-Power, Low-Noise Multichannel Sensor Signal ProcessorElectrical Characteristics(V = V = 4.5V to 5.5V, V = V = 0V, f = 4.0MHz, T = T to T . Typical value ..
MAX14654EWC+T ,High-Current Overvoltage Protector with Adjustable OVLOApplications● Smartphones● Tablet PCs● Mobile Internet DevicesTypical Application CircuitPOWERIN OU ..
MAX146ACAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsGeneral Description ________
MAX146AEAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0; f = ..
MAX146BCAP ,+2.7Low-Power, 8-Channel, Serial 12-Bit ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX146); V = +2.7V to +5.25V (MAX147); COM = 0V; f = ..
MAX146BCAP+ ,+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCsFeaturesThe MAX146/MAX147 12-bit data-acquisition systems♦ 8-Channel Single-Ended or 4-Channel comb ..
MAX4052CPE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4052CSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4052CSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 0; 1/96Low-Voltage, CMOS AnalogMultiplexers/Switches___ ..
MAX4052CSE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX4052CSE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesFeaturesThe MAX4051/MAX4052/MAX4053 and MAX4051A/ ♦ Pin Compatible with Industry-Standard MAX4052A/ ..
MAX4052EEE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX1464AAI+
Low-Power, Low-Noise Multichannel Sensor Signal Processor
General DescriptionThe MAX1464 is a highly integrated, low-power, low-noise
multichannel sensor signal processor optimized for indus-
trial, and process-control applications such as pressure
sensing and compensation, RTD and thermocouple lin-
earization, weight sensing and classification, and remote
process monitoring with limit indication.
The MAX1464 accepts sensors with either single-ended
or differential outputs. The MAX1464 accommodates sen-
sor output sensitivities from 1mV/V to 1V/V. The MAX1464
provides amplification, calibration, signal linearization,
and temperature compensation that enable an overall
performance approaching the inherent repeatability of the
sensor without requiring any external trim components.
Two 16-bit voltage-output DACs and two 12-bit PWMs can
be used to indicate each of the temperature-compensated
sensor signals independently, as a sum or difference
signal, or user-defined relationship between each signal
and temperature. Uncommitted op amps are available to
buffer the DAC outputs, drive heavier external loads, or
provide additional gain and filtering.
The MAX1464 incorporates a 16-bit CPU, user-pro-
grammable 4kB of FLASH program memory, 128 bytes
of FLASH user information, one 16-bit ADC, two 16-bit
DACs, two 12-bit PWM digital outputs, four rail-to-rail op
amps, one SPI™-compatible interface, two GPIOs, and
one on-chip temperature sensor.
The MAX1464 operates from a single 5.0V (typ) supply
and is packaged for automotive, industrial, and commer-
cial temperature ranges in a 28-pin SSOP package.
Applications●Pressure Sensor Signal Conditioning●Weight Measurement Systems●Thermocouple and RTD Linearization●Transducers and Transmitters●Process Indicators●Calibrators and Controllers●GMR and MR Magnetic Direction Sensors
Features●Programmable Amplification, Calibration,
Linearization, and Temperature Compensation●Two Differential or Four Single-Ended ADC Input
Channels●Accommodates Sensor Output Sensitivities from
1mV/V to 1V/V●Two DAC/PWM Output Signal Channels●Supports 4–20mA Current Loop Applications●4kB of FLASH Memory for Code and Coefficients●128 Bytes of FLASH Memory for User Information●Integrated Temperature Sensing●Flexible Dual Op-Amp Block●Programmable Sensor Input Gain and Offset●Programmable Sensor Sampling Rate and Resolution●No External Trim Components Required
Functional Diagram and Detailed Block Diagram appear at
end of data sheet.*Dice are tested at TA = +25°C, DC parameters only.
SPI is a trademark of Motorola, Inc.
OUT2SM
AMP2M
AMP2P
OUT2LG
VREF
INP1
VDDF
INM1
INP2
INM2
VSS
VSSF
GPIO2
GPIO1
VSS
SCLK
CKIO
CKSEL
N.C.
VDD
N.C.
OUT1LG
AMP1P
AMP1M
OUT1SM
SSOPTOP VIEW
MAX1464
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARTTEMP RANGEPIN-PACKAGEMAX1464CAI0°C to +70°C28 SSOP
MAX1464C/W*0°C to +70°CDie
MAX1464EAI-40°C to +85°C28 SSOP
MAX1464AAI-40°C to +125°C28 SSOP
Ordering Information
Ordering Information
EVALUATION KIT AVAILABLE
VDD to VSS............................................................-0.3V to +6.0V
VDDF to VSS.........................................................-0.3V to +6.0V
VSSF to VSS..........................................................-0.3V to +0.3V
All Other Pins to VSS..................................-0.3V to (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.1mW/°C above +70°C) ..........727mW
Operating Temperature Ranges
MAX1464CAI .....................................................0°C to +70°C
MAX1464C/W.....................................................0°C to +70°C
MAX1464EAI...................................................-40°C to +85°C
MAX1464AAI ................................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SUPPLYSupply VoltageVDDVSS = VSSF = 0V4.55.05.5V
FLASH Supply VoltageVDDFVSS = VSSF = 0V4.55.05.5V
Base Operating CurrentIBOCPU stopped (Note 2)575720890µA
CPU CurrentICPUAll modules off, CPU = on, additive to IBO,
ICPU = IDD + IDDF (Note 3)5408401240µA
ADC Current (Note 3)IADC
All modules off, ADC = on, ADC clk = 1MHz,
additive to IBO; the CPU and ADC are not on
at the same time
All modules off, ADC = on, ADC clk = 7kHz,
additive to IBO; the CPU and ADC are not on
at the same time
DAC CurrentIDACnAll modules off, DAC = on, additive to IBO
(n = 1 or 2) (Note 4)425550730µA
Large Op-Amp CurrentIOPLGnAll modules off, CPU stopped, large op amp
= on (n = 1 or 2)4306731020µA
Small Op-Amp CurrentIOPSMnAll modules off, CPU stopped, small op amp
= on (n = 1 or 2)110190265µA
POWER-ON RESETVDDF POR ThresholdVDD > VDDF3.64.04.3V
VDDF POR Hysteresis-0.85V
ANALOG INPUTDifferential Input Impedance
(INP1 to INM1 and
INP2 to INM2)
RDIN
PGA[4:0] = 00000, CLK[2:0] = 000430PGA[4:0] = 01010, CLK[2:0] = 00055
PGA[4:0] = 11111, CLK[2:0] = 00036
PGA[4:0] = 00000, CLK[2:0] = 0113.4MΩ
PGA[4:0] = 01010, CLK[2:0] = 011440kΩPGA[4:0] = 11111, CLK[2:0] = 011288
PGA[4:0] = 00000, CLK[2:0] = 11027
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSingle-Sided Input Impedance
(INP1 to VSS, INM1 to VSS,
INP2 to VSS, INM2 to VSS)
RSIN
PGA[4:0] = 00000, CLK[2:0] = 000430PGA[4:0] = 01010, CLK[2:0] = 00055
PGA[4:0] = 11111, CLK[2:0] = 00036
PGA[4:0] = 00000, CLK[2:0] = 0113.4MΩ
PGA[4:0] = 01010, CLK[2:0] = 011440kΩPGA[4:0] = 11111, CLK[2:0] = 011288
PGA[4:0] = 00000, CLK[2:0] = 11027PGA[4:0] = 01010, CLK[2:0] = 1103.5
PGA[4:0] = 11111, CLK[2:0] = 1102.3
Common-Mode Rejection RatioCMRRCommon-mode voltage VCM = VSS to VDD 0.008%FS
Differential Signal-Gain RangeSelectable in 17 steps (Note 5)0.99 to 244V/V
Differential Signal GainAVDIFF
PGA[4:0] = 000000.950.991.05
V/V
PGA[4:0] = 000017.37.78.2
PGA[4:0] = 01010717782
PGA[4:0] = 10100137153168
PGA[4:0] = 11110203244283
Gain-Error Temperature CoeficientGETCADCPGA[4:0] = 00000-8ppm/°C
COARSE-OFFSET DACResolution3-bit plus sign4Bits
Effective Offset Adjustment at the
ADC InputOAADC
REF = VDD,
CO[3:0] = 0111
PGA[4:0] =
00000 to 01000137147157
% of
ADC
Ref
PGA[4:0] =
01010 to 10000273291308
PGA[4:0] =
10100 to 11110525578630
REF = VDD,
CO[3:0] = 0011
PGA[4:0] =
00000 to 01000576469
PGA[4:0] =
01010 to 10000113126136
PGA[4:0] =
10100 to 11110228251276
REF = VDD,
CO[3:0] = 0000
PGA[4:0] =
00000 to 01000-3-1+1
PGA[4:0] =
01010 to 10000-7-2.4+2
PGA[4:0] =
10100 to 11110-11-4+3
Electrical Characteristics (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSEffective Offset Adjustment at the
ADC InputOAADC
REF = VDD,
CO[3:0] = 1000
PGA[4:0] =
00000 to 01000-15-10-4
% of
ADC
Ref
PGA[4:0] =
01010 to 10000-29-19-10
PGA[4:0] =
10100 to 11110-56-38-20
REF = VDD,
CO[3:0] = 1011
PGA[4:0] =
00000 to 01000-79-73-66
PGA[4:0] =
01010 to 10000-155-145-135
PGA[4:0] =
10100 to 11110-317-287-257
REF = VDD,
CO[3:0] = 1111
PGA[4:0] =
00000 to 01000-162-156-150
PGA[4:0] =
01010 to 10000-327-309-293
PGA[4:0] =
10100 to 11110-675-614-555
SMALL OP AMPInput Offset VoltageVOS_SM0±15mV
Input Bias CurrentIB_SM±1nA
DC GainAVOL_SMOUTnSM = 0.5V to 4.5V (n = 1 or 2),
RLOAD = ∞100dB
Gain Bandwidth ProductGBW_SMAVOL_SM = +1V/V2.7MHz
Slew RateSR_SMAVOL_SM = +1V/V2.2V/µs
Common-Mode Input RangeCMR_SMVSS +
VDD -
0.02V
Common-Mode Rejection RatioCMRR_SMVCM_OPAMP = VSS to VDD70dB
Power-Supply Rejection RatioPSRR_SMAt DC70dB
Input-Referred Noise VoltageVN_SM0.1Hz to 1kHz8.5µVRMS0.1Hz to 1MHz100
Output High VoltageVOH_SM
RLOAD = ∞VDD - 0.1RLOAD = 4.7kΩ to VSSVDD - 0.15
Output Low VoltageVOL_SMRLOAD = ∞0.1VRLOAD = 4.7kΩ to VDD0.15
Output Source CurrentISRC_SMVOUTnSM = VOH_SM, RLOAD = 4.7kΩ to VSS-1.04mA
Output Sink CurrentISNK_SMVOUTnSM = VOL_SM, RLOAD = 4.7kΩ to VDD1.04mA
Maximum Output Load
CapacitanceCL_SMRLOAD = ∞, phase margin > 55°120pF
Electrical Characteristics (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LARGE OP AMPInput Offset VoltageVOS_LG0±6mV
Input Bias CurrentIB_LG±225nA
DC GainAVOL_LGOUTnLG = 0.5V to 4.5V (n = 1 or 2),
RLOAD = ∞100dB
Gain Bandwidth ProductGBW_LGAVOL_LG = +1V/V4.0MHz
Slew RateSR_LGAVOL_LG = +1V/V3.2V/µs
Common-Mode Input RangeCMR_LGVSS +
VDD -
0.02V
Common-Mode Rejection RatioCMRR_LGVCM OPAMP = VSS to VDD70dB
Power-Supply Rejection RatioPSRR_LGAt DC70dB
Input-Referred Noise VoltageVN_LG0.1Hz to 1kHz19µVRMS0.1Hz to 1MHz160
Output-Voltage High VOH_LG
RLOAD = ∞VDD - 0.1RLOAD = 1kW to VSSVDD - 0.125
Output-Voltage Low VOL_LGRLOAD = ∞0.03V
RLOAD = 1kΩ to VDD0.13
Output Source CurrentISRC_LGVOUTnLG = VOH_LG, RLOAD = 1kΩ to VSS-4.9mA
Output Sink CurrentISNK_LGVOUTnLG = VOL_LG, RLOAD = 1kΩ to VDD4.9mA
Maximum Output Load
CapacitanceCL_LGRLOAD = ∞, phase margin > 55°200pF
OP-AMP SWITCHAnalog Signal RangeVSWVSSVDDV
On-ResistanceRON5kΩ
Off-IsolationVISO80dB
DIGITAL-TO-ANALOG CONVERTERResolutionRESDAC16Bits
Integral NonlinearityINLDAC3Bits
Differential NonlinearityDNLDAC±1Bits
Offset ErrorVDAC OSDAC ref = VDD, DAC data = 0000hVDD/2
- 0.06
VDD/2
+ 0.06V
Bit WeightBWDACDAC ref = 5VDC91.55µV/LSB
Power-Supply RejectionPSRDACAt DC, DAC ref = VREF0.02%FS
Output NoiseONDACDAC buffer is the small op amp±3LSB
Output Settling TimeSTDACTo 0.1% of inal value250µs
PULSE-WIDTH MODULATORResolutionRESPWM(Note 6)12Bits
Electrical Characteristics (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSBit WeightBWPWM2µs/LSB
Offset ErrorVPWM_OSPWM data = 0000h ±1µs
Gain ErrorGEPWM(Note 7)±0.025%
Output JitterOJPWM1/4LSB
EXTERNAL REFERENCE INPUTReference Input Voltage RangeVREF2.252.52.75V
Reference Input ResistanceRREFVREF = 2.5V, ADC = ON, DACs = ON100kΩ
INTERNAL VOLTAGE REFERENCEInternal Voltage ReferenceVIR(Note 8)4.54.925.35V
Temperature CoeficientTCIR±110ppm/°C
TEMPERATURE SENSORSensitivitySensTSPGA[4:0] = 00001, CO[3:0] = 0110+2mV/°C
+95LSB/°C
Nonlinearity ErrorINLTS±0.5%FS
HysteresisHistTS±0.1%FS
ANALOG-TO-DIGITAL CONVERTERResolutionRESADC16Bits
Integral NonlinearityINLADC2Bits
Differential NonlinearityDNLADC±1LSB
ADC Offset ErrorVADC_OSPGA[4:0] = 00000 (0.99),
CO[3:0] = 0000 (Note 9)4%FS
Channel-to-Channel Offset Error
MatchingDVADC_OS±1LSB
ADC Offset-Supply RejectionOSRADCAt DC, ADC ref = VREF = 5V0.3%FS
ADC Gain-Supply RejectionGSRADCAt DC, ADC ref = VREF = 5V0.005%FS
Offset Temperature CoeficientTA = -40°C to +125°C0.03%FS
RatiometricityPGA[4:0] = 00000 to 010000.02%FS
Electrical Characteristics (continued)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to VSS.
Note 2: All modules are off, except internal reference, oscillator, and power-on reset (POR) and CKSEL bit is set to zero.
Note 3: The CPU and ADC are not on at the same time. The ADC and CPU currents are not additive.
Note 4: IDACn does not include output buffer currents (IOPLGn or IOPSMn).
Note 5: For gains above 240, an additional digital gain can be provided by the CPU.
Note 6: The PWM input data is the 12-bit left-justified data in the 16-bit input field.
Note 7: PWM gain error measured as:
OUTOUTPWMPWM(F00h)PWM(100h)GE100%3584×−×=×
Note 8: The internal reference voltage has a nominal value of 5V (4 x VBG) even when VDD is greater or less than 5VDC.
Note 9: A Input-referred offset error is the ADC offset error divided by the PGA gain.
Note 10: When the CKIO is configured in output mode to observe the internal oscillator signal, the total current is above the speci-fied limits.
Note 11: fCLK must be within 5% of 4MHz.
Note 12: Allow a minimum elapsed time of 4.2ms when executing a FLASH erase command, before sending any other command. Allow a minimum elapsed time of 80μs between FLASH write commands.
Note 13: FLASH programming current is guaranteed by design.(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS (GPIO1, GPIO2, SCLK, DI, CKSEL, CKIO, CS)Input High Threshold VoltageVIH0.8 x VDDV
Input Low Threshold VoltageVIL0.2 x VDDV
Input HysteresisVIHYS0.2V
Input Leakage CurrentIINCKSEL, CS = VSS38-90µAGPIO1, GPIO2, SCLK, DI, CKIO = VDD38+90
Input CapacitanceCIN5pF
DIGITAL OUTPUTS (GPIO1, GPIO2, DO, CKIO)Output-Voltage HighVOH
RLOAD = ∞
GPIO1, GPIO2, DOVDD - 0.1CKIO (Note 10)4.9
RLOAD = 2kΩ to VSSGPIO1, GPIO2, DOVDD - 0.15
CKIO (Note 10)4.6
Output-Voltage LowVOL
RLOAD = ∞GPIO1, GPIO2, DO0.05
CKIO (Note 10)0.1
RLOAD = 2kΩ to
VDD
GPIO1, GPIO2, DO0.2
CKIO (Note 10)0.4
FLASH MEMORYMaximum Erase Cycles(Notes 11, 12)10kCycles
Minimum Erase TimetERASE(Notes 11, 12)4.2ms
Minimum Write TimetWRITE(Notes 11, 12)80µs
FLASH Programming CurrentIDDFPWriting to the FLASH or erasing the FLASH
(Note 13)30mA
Electrical Characteristics (continued)
(VDDF = VDD = 4.5V to 5.5V, VSSF = VSS = 0V, fCLK = 4.0MHz, TA = TMIN to TMAX. Typical values are at VDDF = VDD = 5.0V, VSSF
= VSS = 0V, TA = +25°C, unless otherwise noted.) (Note 1)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSProgramming TemperatureTPROG125°C
Internal Oscillator Clock
FrequencyfICLKOSC[4:0] = 000003.34.155.3MHz
External Clock FrequencyfECLKVCKSEL = 0
Min0.2
MHzMax5
External Master Clock Input Low
TimefECLKIN_LOtECLK = 1 / fECLK 4060%
tECLK
External Master Clock Input High
TimefECLKIN_HItECLK = 1 / fECLK 4060%
tECLK
SERIAL INTERFACE (Figure 1)SCLK Setup to Falling Edge CStSC30ns
CS Falling Edge to SCLK Rising
Edge Setup TimetCSS30ns
CS Idle TimetCSIfCLK = 4MHz1.5µs
CS PeriodtCSfCLK = 4MHz4µs
SCLK Falling Edge to Data Valid
DelaytDOCLOAD = 200pF80ns
Data Valid to SCLK Rising Edge
Setup TimetDS30ns
Data Valid to SCLK Rising Edge
Hold TimetDH30ns
SCLK High Pulse WidthtCH100ns
SCLK Low Pulse WidthtCL100ns
CS Rising Edge to SCLK Rising
Edge Hold TimetCSH30ns
CS Falling Edge to Output EnabletDVCLOAD = 200pF25ns
CS Rising Edge to Output DisabletTRCLOAD = 200pF25ns
Timing Characteristics
(VADD = 5.0V, TA = +25°C, unless otherwise noted.)
Figure 1. Serial Interface Timing Diagram
SCLK
tCSStCLtCH
tCSHtSC
tCS
tDS
tDH
tDS
tDH
tCSI
tCSStCLtCHtSCtCSH
tDOtTRtDVtDVtDOtTR
SUPPLY CURRENT
vs. INTERNAL CLOCK FREQUENCYMAX1464 toc02
INTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT, I
(mA)
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADCCLK = 1MHz
DAC1 ON
SMALL OP AMP ON
MODULE CURRENT
vs. TEMPERATUREMAX1464 toc03
TEMPERATURE (°C)
MODULE CURRENT (mA)704315-13
DAC + LARGE OP AMP
DAC + SMALL OP AMP
ADC
BASE
BASE OPERATING CURRENT
vs. SUPPLY VOLTAGEMAX1464 toc04
BASE OPERATING CURRENT, I
(mA)
TA = +125°C
TA = +25°C
TA = -40°C
ADC RATIOMETRICITY ERROR
vs. SUPPLY VOLTAGEMAX1464 toc05
ADC
RATIOMETRICITY
ERROR (%FS)
ADC INPUT = 0.75 x VDD
ADC INPUT = 0.5 x VDD
ADC INPUT = 0
ADC INPUT = -0.75 x VDD
ADC INPUT = -0.5 x VDD
ADCREF = VDD
PGA[4:0] = 00000
ADC INLMAX1464 toc06
ADC NONLINEARITY ERROR (%FS)-0.004
PGA[4:0] = 01000
SUPPLY CURRENT
vs. SUPPLY VOLTAGEMAX1464 toc01
SUPPLY VOLTAGE, VDD (V)
SUPPLY CURRENT, I
(mA)
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADCCLK = 1MHz
DAC1 ON
SMALL OP AMP ON
TA = +125°C
TA = +25°C
TA = -40°C
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Typical Operating Characteristics
(VADD = 5.0V, TA = +25°C, unless otherwise noted.)
ADC DNLMAX1464 toc07
INPUT VOLTAGE NORMALIZED TO FULL SCALE
ADC DNL ERROR (LSB)
PGA[4:0] = 01000
DAC INLMAX1464 toc08
INPUT NORMALIZED TO FULL SCALE
DAC NONLINEARITY ERROR (%FS)
DAC DNL
MAX1464 toc09
INPUT VOLTAGE NORMALIZED TO FULL SCALE
DAC DNL ERROR (LSB)
DAC DYNAMIC RESPONSE
200µs/div
1V/div
DAC CODE = 4000h
DAC CODE = C000h
MAX1464 toc10
DAC RATIOMETRICITY ERROR
vs. SUPPLY VOLTAGEMAX1464 toc11
SUPPLY VOLTAGE, VDD (V)
ERROR (%FS)
DAC INPUT = 5555CH (4.5V AT VDD = 5V)
DAC INPUT = 0000CH (2.5V AT VDD = 5V)
DAC INPUT = AAABCH (0.5V AT VDD = 5V)
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGEMAX1464 toc12
INTERNAL OSCILLATOR FREQUENCY (MHz)
TA = -40°C
TA = +125°C
TA = +25°C
OSCILLATOR
FREQUENCY TRIMMED
TO 4MHz AT +25°C,
VDD = 5V
TEMPERATURE SENSOR OUTPUT
vs. TEMPERATUREMAX1464 toc13
TEMPERATURE SENSOR OUTPUT (ADC CODE)
12,000
10,000
14,000
16,000
PGA[4:0] = [00001]
CO[3:0] = 0110
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Typical Operating Characteristics (continued)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
PINNAMEFUNCTIONOUT1SMSmall Op Amp 1 OutputAMP1MOp Amp 1 Negative Input AMP1POp Amp 1 Positive InputOUT1LGLarge Op Amp 1 Output
5, 7N.C.No ConnectionVDDPositive Supply Voltage Input. Bypass VDD to VSS with a 0.1µF ceramic capacitor.CKSELClock-Select Digital InputCKIOClock Digital Input/Output CSSPI Chip-Select Digital Input. Active low.DOSPI Data OutputDISPI Data InputSCLKSPI Interface Clock
14, 19VSSNegative Power-Supply InputVDDFPositive Supply Voltage for FLASH Memory. Bypass VDDF to VSS with a 0.1µF ceramic capacitor.GPIO1General-Purpose Digital Input/Output 1GPIO2General-Purpose Digital Input/Output 2VSSFNegative Power-Supply Input for FLASH MemoryINM2Negative Input for ADC Channel 2INP2Positive Input for ADC Channel 2INM1Negative Input for ADC Channel 1INP1Positive Input for ADC Channel 1VREFExternal Reference Voltage Input for ADC and DACsOUT2LGLarge Op Amp 2 OutputAMP2POp Amp 2 Positive InputAMP2MOp Amp 2 Negative Input OUT2SMSmall Op Amp 2 Output
Pin Description
Typical Application CircuitAnalog ratiometric output configuration (Figure 2) pro-
vides an output that is proportional to the power-supply
voltage. Ratiometricity is an important consideration for
battery-operated instruments, and some industrial appli-
cations.
Detailed DescriptionThe MAX1464 is a highly integrated, low-power, low-
noise multichannel sensor signal processor optimized for
industrial, and process-control applications, such as pres-
sure sensing and compensation, RTD and thermocouple
linearization, weight sensing and classification, and
remote process monitoring with limit indication.
The MAX1464 incorporates a 16-bit CPU, user-program-
mable 4kB of FLASH memory, 128 bytes of FLASH user
information, 16-bit ADC, two 16-bit DACs, two 12-bit
PWM digital outputs, four rail-to-rail op amps, SPI inter-
face, two GPIOs, and one on-chip temperature sensor.
Each sensor signal can be amplified, compensated for
temperature, linearized, and the offset and full scale can
be adjusted to the desired value. The MAX1464 can pro-
vide outputs as analog voltage (DAC) or digital (PWM,
GPIOs), or simple on/off alarm indication (GPIOs). The
uncommitted op amps can be used to implement 4–20mA
current loops or for additional gain and filtering. Each
DAC output is routed to either a small or large op amp.
Large op amps are capable of driving heavier external
loads. The unused circuit functions can be turned off to
save power.
All sensor linearization and on-chip temperature com-
pensation is done by a user-defined algorithm stored
in FLASH memory. The user-defined algorithm is pro-
grammed over the serial interface and stored in 4kB of
integrated FLASH memory.
The MAX1464 uses an internal 4MHz oscillator or an
externally supplied 4MHz clock. CPU code execution and
ADC operation is fully synchronized to minimize the noise
interference of a CPU-based sensor processor system.
The CPU sequentially executes instructions stored in
FLASH memory.
Sensor InputThe MAX1464 provides two differential signal inputs,
INP1-INM1 and INP2-INM2. These inputs can also be
configured as four single-ended signals. Each input can
have a common-mode range from VDD to VSS and a
0.99V/V to 244V/V programmable-gain range. The dif-
ferential input signals are summed with the output of the
coarse offset DAC (CO DAC) for offset correction prior
to being amplified by the programmable-gain amplifier
(PGA). The resulting signal is applied to the differential
input of the ADC for conversion. The CPU can be pro-
grammed to measure one or two differential inputs plus
the internal temperature sensor defined in user-supplied
algorithm. For example, the differential inputs can be
measured many times while the temperature can be mea-
sured less frequently.
Figure 2. Basic Bridge Sensor Ratiometric Output Configuration
5VDC
VDD
SENSOR
VSS
VDDF
OUTnSMOUT
0.1µF0.1µF100pF
INPn
INMn
GND
22Ω
MAX1464MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
On-Chip Temperature SensingThe on-chip temperature sensor changes +2mV/°C over
the operating range. The ADC converts the temperature
sensor in a similar manner as the sensor inputs. During
an ADC conversion of the temperature sensor, the ADC
automatically uses four times the internal 1.25V reference
as the ADC full-scale reference (5V). The temperature
data format is 15-bit plus sign in two’s-complement for-
mat. Gain offset compensation can be programmed to
utilize the full-scale range of the ADC. Offset compen-
sation by the CO DAC is provided so that the nominal
temperature measurement can be centered at the ADC
output value. Use the CPU to provide additional digital
gain and offset correction.
Output FormatThere are two output modules in the MAX1464—DOP1
(DAC Op Amp PWM 1) and DOP2 (DAC Op Amp PWM
2). Each of the DOP modules contains a 16-bit DAC, a
12-bit digital PWM converter, a small op amp, and a large
op amp with high-output-drive capability. Each module
can be configured in several different modes to suit a wide
range of output signal requirements. Either the DAC or the
PWM can be selected as the primary output signal. The
DAC output signal must be routed to one of the two op
amps before being made available to a device pin. See the
DAC, Op Amp, PWM Modules (DPOn) section for details.
Additional digital outputs are available on the GPIOs.
InitializationA user-defined initialization routine is required to config-
ure the oscillator frequency and various analog modules,
e.g., PGA gain, ADC resolution, ADC clock settings, etc.
After the initialization routine, the CPU can start execution
of the main program.
Power-On Reset (POR)The MAX1464 contains a POR circuit to disable CPU execu-
tion until adequate VDD and VDDF voltage are available for
operation. Once the power-on state has been reached, the MAX1464 is kept under reset condition for 250μs before the
CPU starts execution. Below the POR threshold, all internal
CPU registers are set to their POR default state. Power-on
control bits for internal modules are reset to the OFF condition.
CPU ArchitectureThe CPU provides a wide range of functionality to be
incorporated in an embedded system. The CPU can com-
pensate nonlinear and temperature-dependent sensors,
check for over/underlimit conditions, output sensor or
The CPU can perform a limited amount of signal process-
ing (filtering). A timer is included so that uniform sampling
(equally spaced ADC conversions) of the input sensors
can be performed.
The CPU registers and ports are implemented in volatile,
static memory. There are several registers contained in
various peripheral modules that provide module configu-
ration settings, control functions, and data. These module
registers are accessible through an indirect addressing
scheme as described in detail in the CPU Registers, CPU
Ports, and Modules sections. Figure 3 shows the CPU
architecture.
CPU RegistersThe MAX1464 incorporates a CPU with 16 internal
registers. All the CPU registers have a 16-bit data word
width. Five of the 16 registers have predefined functional
operations that are dependent on the instruction being
executed. The remaining registers are general purpose.
The CPU registers are embedded in the CPU itself and
are not all directly accessible by the serial interface. The
accumulator register (A), the pointer register (P), and the
instruction (FLASH data) can be read through the serial
interface when the CPU is halted. This enables a single-
FLASH MEMORY
(4kB)
SERIAL INTERFACE
SCLKDIDOCS
R0 POINTER (P)
R1 ACCUMULATOR (A)
R3 MULTIPLICAND (N)
R4 MULTIPLIER (M)
CPU REGISTERS
INSTRUCTION
CPU
FLASH DATA
ADDRESS
CPU PORTS
R5 INDEX (I)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
step mode of code execution to ease code writing and
debugging. A special program instruction sequence is
required to observe the other CPU registers. Table 1 lists
the CPU registers.
CPU PortsThe MAX1464 incorporates 16 CPU ports that are directly
accessible by the serial interface. All the CPU ports have
a 16-bit data word width. The contents of the ports can
be read and written by transferring data to and from the
accumulator register (A) using the RDX and WRX instruc-
tions. No other CPU instructions act on the CPU ports.
Three CPU ports PD, PE, and PF have uniquely defined
operation for reading and writing data to and from the
peripheral modules. All CPU ports are static and volatile.
Table 2 lists the CPU ports.
ModulesThe MAX1464 modules are the functional blocks used to
process analog and digital signals to and from the CPU.
Each module is addressed through CPU ports PD, PE, and , as described in the CPU Ports section. All modules use
static, volatile registers for data retention. There are three
types of module registers: configuration, data, and control.
They are used to put a module into a particular mode of
operation. Configuration registers hold configuration bits
that control static settings such as PGA gain, coarse offset,
etc. Data registers hold input data such as DAC and PWM
input words or output data such as the result of an ADC
conversion. Control registers are used to initiate a process
(such as an ADC conversion or a timer) or to turn modules
on and off (such as op amps, DAC outputs, PWM outputs,
etc.) Table 3 lists the module registers.
ADC ModuleThe ADC module (Figure 4) contains a 9-bit to 16-bit
sigma-delta converter with multiplexed differential and
single-ended signal inputs, a CO DAC, four reference
voltage inputs, two differential or four single-ended exter-
nal inputs, and 15 single-ended internal voltages for
measurement. The ADC output data is 16-bit two’s
complement format. The conversion channel, modes,
and reference sources are all set in ADC configura-
tion registers. The conversion time is a function of the
selected resolution and ADC clock frequency. The CPU
can be programmed to convert any of the inputs and the
internal temperature sensor in any desired sequence. For
example, the differential inputs may be converted many
times and conversions of temperature performed less
frequently. See Table 4.
which is an internally generated bandgap reference volt-
age. Note that because VREF external = 2.5V and VBG
= 1.25V, the ADC’s reference voltage is always close to
5.0V. The ADC voltage reference is also used by the CO
DAC to maintain a signal conversion that is completely
ratiometric to the selected reference source.
The four analog inputs (INP1, INM1, INP2, INM2) and
several internal circuit nodes can be multiplexed to the
ADC for a single-ended conversion relative to VSS. The
selection of which circuit node is multiplexed to the ADC
is controlled by the ADC_Control register. The ADC can
measure each of the op-amp output nodes with gain for
converting user-defined circuits or incorporating sys-
tem diagnostic test functions. The DAC outputs can be
converted by the ADC with either op amp arranged as
unity-gain buffers on the DAC outputs. The internal power
nodes, VDD and VSS, and the bandgap reference, VBG
can be multiplexed to the ADC for conversion as well.
These measurement modes are defined and initiated in
the ADC_Control register. See Tables 5 and 7 for the
single-ended configuration.
ADC RegistersThe ADC module has 10 registers for configuration, control,
and data output. There are three conversion channels in the
ADC; channel 1, channel 2, and temperature. Channels 1
and 2 are associated with the differential signal input pairs
INP1-INM1 and INP2-INM2, respectively. The temperature
channel is associated with the integrated temperature
sensor. Each channel has two configuration registers
(ADC_Config_nA and ADC_Config_nB where n = 1, 2, or
T) for setting conversion resolution, reference input, coarse
offsets, etc. The data output from a conversion of channel
1, 2, or T is stored in the respective data output register
ADC_Data_n where n = 1, 2, or T. Each of the channels can
be used to convert single-ended inputs as listed in Table
7. The ADC_Control register controls which channel is to
be converted and what single-ended input, if any, is to be
directed to that channel. See Tables 8 through 13.
Conversion StartTo initiate an ADC conversion, a word is written to the
ADC_Control register with either CNVT1, CNVT2, or
CNVTT bit set to a 1 (Table 6). When an ADC conversion
is initiated, the CPU is halted and all CPU and FLASH
activities cease. All CNVT1, CNVT2, and CNVTT bits are
cleared after the ADC conversion is completed.
Upon completion of the conversion, the ADC result is
latched into the respective ADC_Data_n register. In addi-
tion, the convert bits in control register 0 are all reset to
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Single-ended inputs can be converted by either channel
1 or 2 by initiating a conversion on the appropriate chan-
nel with the SE[3:0] bits set to the desired single-ended
input (Table 7). Several of the single-ended signals are
converted with a fixed gain. The reduced gain of 0.7V/V
allows signals at or near the supply rails to be converted
without concern of saturation. Other single-ended signals
can be converted with the full selectable PGA gain range.
Programmable-Gain Amplifier
The gain of the differential inputs and several single-
ended inputs can be set to values between 0.99V/V to
244V/V as shown in Table 14. The PGA bits are set in
ADC_Config_nA where n = 1, 2, or T. The gain setting
must be selected prior to initiating a conversion.
ADC Conversion Time and ResolutionThe ADC conversion time is a function of the selected
resolution, ADC clock (fADC), and system clock frequency
(fCLK). The resolution can be selected from 9 bits to 16
by bits RESn[2:0]. The lower resolution settings (9 bit)
convert faster than the higher resolution settings (16 bit).
The ADC clock fADC is derived from the primary system
clock fCLK by a prescalar divisor. The divisor can be set
from 4 to 512, producing a range of fADC from 1MHz
down to 7.8125kHz when fCLK is operating at 4.0MHz.
Other values of fCLK produce other scaled values of fADC.
See Tables 15 and 16.
Systems operating with very low power consumption
benefit from the reduced fADC clock rate. Slower clock
speeds require less operating current. Systems operat-
ing from a larger power consumption budget can use the
highest fADC clock rate to improve speed performance
over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The con-
version time is calculated by the formula:
tCONVERT = (no. of fADC clocks per conversion) /fADC
Figure 4. ADC Module
INP1
INM1
INP2
INM2
DAC
REF
TEMPERATURE
SENSOR
VBG
VDD
4 x VBG
2 x VREF
ADC
INMn
VBG
OUTnSM
OUTnLG
VDD
VSS
DACnOUT VIA OUTnSM
INPn
NO.
SINGLE-ENDEDDACnOUT VIA OUTnLG
00hADC_Control
08hADC_Config_TA
07hADC_Data_T
06hADC_Config_2B
09hADC_Config_TB
02hADC_Config_1A
05hADC_Config_2A
04hADC_Data_2
03h
01hADC_Data_1
ADC_Config_1B
PGA
VSS
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Coarse-Input Offset AdjustmentDifferential input signals that have an offset can be par-
tially nulled by the input coarse-offset (CO) DAC. An offset
voltage is added to the input signal prior to gaining the
signal. This allows a maximum gain to be applied to the
differential input signal without saturating the conversion
channel. The CO signal added to the differential signal is
a percentage of the full-scale ADC reference voltage as
referred to the ADC inputs. Low PGA gain settings add
smaller amounts of coarse offset to the differential input.
Large PGA gain settings enable correspondingly larger
amounts of coarse offset to be added to the input signal.
The CO DAC also applies to the temperature channel
enabling offset compensation of the temperature signal.
See Table 18.
Bias Current SettingsThe analog circuitry within the ADC module operates from
a current bias setting that is programmable. The program-
mable levels of operation are fractions of the full bias cur-
rent. The operating power consumption of the ADC can
be reduced at the penalty of increased conversion times
that may be desirable in very-lowpower applications. It is
recommended operating the ADC at full bias when pos-
sible. The amount of bias as a fraction of full bias is shown
in Table 19. The setting is controlled by the BIASn[2:0]
bits in the ADC_config_nb registers where n = 1, 2, or T.
Reference Input Voltage SelectThe ADC can use one of three different reference voltage
inputs depending on the conversion channel and REFn
setting as shown in Table 20. The differential inputs can
be converted ratiometrically to the supply voltage (VDD),
converted ratiometrically to an externally supplied voltage
at VREF, or converted nonratiometrically using a fixed
voltage source derived from the internal bandgap voltage
source. The temperature channel is always converted
using the internal bandgapderived voltage source and
therefore is not selectable.
Output Sample RateGenerally, the sensor and temperature data are converted
and calculated by an algorithm in the execution loop. The
output sample rate of the data depends on the conver-
sion time, the CPU algorithm loop time, and the time to
store the result in the DOPn_DATA register. To achieve
uniform sampling, the instruction code must be written to
provide a consistent algorithm loop time, including branch
instruction variations. This total loop time interval should
be repeatable for a uniform output rate.
ing of the serial interface, if required, can be completed
before timeout. The GPIO pins can be utilized to interrupt
an external master microcontroller when the ADC conver-
sion is done and/or when the CPU computations are done
so the serial interface can be read quickly.
DAC, Op Amp, PWM Modules (DOPn)There are two output modules in the MAX1464—DOP1
and DOP2 (Figure 5). Each of the DOP modules contains
a 16-bit DAC, a 12-bit digital PWM converter, a small op
amp, and a large op amp with high-outputdrive capability.
Switches in the DOP module enable a range of intercon-
nectivity among the converters, op amps, and the external
pins. Either the DAC or the PWM can be selected as the
primary output signal. The DAC output signal is routed to
one of the op amps and made available to a device pin.
The signal-switching arrangement also allows the unused
op amp to be configured as an uncommitted device with
all connections available to external pins.
The DAC and op amps have a power-control bit in the
power module. When power is disabled, all circuits in the
DAC and the op amp are disabled with inputs and out-
puts in a tri-state condition. The proper bits in the power
module must be enabled for operation of the DAC and
op amps.
The DAC input is a 16-bit two’s-complement value. An
input value of 0000h produces an output voltage of one
half the DAC reference voltage. The DAC output voltage
increases for positive two’s-complement numbers, and
decreases for negative two’s-complement numbers.
The PWM input is a 12-bit two’s complement value. It
shares the same input register (DOPn_Data) as the DAC,
using the 12 MSBs of the 16-bit register. An input value
of 000Xh produces a 50% duty cycle waveform at the
output. The PWM output duty cycle increases for positive
two’s-complement numbers, and decreases for negative
two’s-complement numbers.
DOP_n Coniguration OptionsEach of the DOP modules can be configured in sev-
eral different modes to suit a wide range of output signal
requirements. The Functional Diagram shows the various
switch settings of the configuration and control registers.
In situations where configuration settings create a conflict
in switch activation, a priority is applied to the switch logic
to prevent the conflict.
The DAC and/or the PWM can be selected as the output
signal source. The DAC output signal is routed to one of
the op amps and made available to a device pin. Selecting
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
unity-gain buffer configuration is automatically selected,
and it provides the DAC output signal directly to the device
pin OUTnLG. With the large op amp selected, the small op
amp can be used as an independent device for external cir-
cuit applications when the PWM is disabled. Alternatively,
the PWM can also be enabled to drive the OUTnSM device
pin, in which case the small op amp is OFF.
Selecting the small op amp as the DAC output driver
device is useful for routing the output signal to other cir-
cuits in an embedded control system with high-impedance
load connections. The unity-gain buffer configuration is
automatically selected, and it provides the DAC output
signal directly to the device pin OUTnSM. With the small
op amp selected, the large op amp can be used as an
independent device for external circuit applications when
the PWM is disabled. Alternatively, the PWM can also be
enabled to drive the OUTnLG device pin, in which case
the large op amp is OFF.
The DAC has two reference voltage sources available by
selection, VDD and VREF input. When the external refer-
ence is selected (VREF), the actual DAC reference is 2 x
VREF. See VREF to 2.5V for nominal operation. The out-
put of the DAC is a voltage proportional to the reference
The DOP module also provides a 12-bit digital PWM
output. At a nominal 4MHz frequency, the frequency of
the PWM is 122Hz (PWM period = 8.192ms). The DAC
and the PWM share the same input register, DOPn_Data,
where the PWM uses the 12 MSBs, in two’s-complement
format. An input of 000Xh (4 LSBs are ignored) outputs
a 50% duty cycle waveform at the selected output pin
(either OUTnSM or OUTnLG). The PWM bit weight is 2μs, at a nominal frequency of 4MHz. The minimum duty
cycle is obtained when the input is 800Xh (duty cycle is 0
/ 4096 = 0), and the maximum duty cycle at 7FFXh (duty
cycle is 4095 / 4096 = 99.98%). A new PWM input word is
only effective at the end of a current PWM cycle, therefore
preventing PWM glitches on the output.
Either the small or the large op amp in the DOP module
can also be selected as an uncommitted op amp in the
MAX1464. The op amps can be configured as a unitygain
buffer, where the output is internally connected to the
negative terminal of the op amp, or a stand-alone op amp,
where both AMPnM and AMPnP can be externally con-
nected for various analog functions. In the case of a buffer,
the device pin AMPnM is in high-impedance mode, as the
feedback loop around the op amp is connected internally.
Figure 5. DOP1 and DOP2 Modules
DAC10h OR 13hDOPn_Data
12h OR 15hDOPn_Config
30hOpAmp_Config
11h OR 14hDOPn_Control
REF
PWM
SW0
SW1
SW2
SW3
SW4
SW5
SW6SW7
SW8
SW9
2 x VREF
VDD
OUTnSM
AMPnM
AMPnP
OUTnLG
SW10
SW11
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Every function of the DOP module can be selected indi-
vidually (DAC, PWM, or op amp), or two out of the three
functions of the DOP module can be selected at the same
time (PWM and op amp, or DAC and PWM, or DAC and
op amp), as there are only two output pins for the mod-
ule, OUTnSM and OUTnLG. The various configuration
options for the DOP are shown in Table 21. The PWRDAC
and PWROP bits are in the power-on control register
(address = 31h), and the remaining bits are in the DOP
registers. See Tables 21 through 27.
Timer ModuleThe timer module (Figure 6) comprises a 12-bit counter,
a 4-bit prescalar, and control and configuration registers.
When the timer is enabled and initiated, the system mas-
ter clock, MCLK, is prescaled by the divisor set by PS[3:0]
in the TMR_Config register and the result applied to the
12- bit upcounter. When the counter value matches the
timeout value TO[11:0] in register TMR_Config, bit TMDN
is set to 1. The CPU can poll the timer done bit TMDN to
check its status.
The timer module provides a feature that enables the
CPU to be put into a low-power halt mode for the dura-
tion of the timer interval. Setting the ENAHALT bit in the
TMR_Control register while starting the timer (setting the
timer enable bit TMEN to 1), or while the timer is already
enabled and counting halts the CPU at the present
instruction until the TMDN bit becomes set by the counter.
The CPU commences execution with the next instruction.
All CPU registers and ports are fully static and retain all
data during the elapsed time interval.
The time interval between TMEN being set to 1, and
TMDN being set to 1 can be computed as follows:
Time Interval = (2 / fOSC) x {(prescale value N)
x (timeout value TO[11:0]) + 1.5}
The maximum time interval given fOSC = 4MHz clock is
786ms.
Power ControlThe power to various subcircuits in the MAX1464 can
be turned on and off by CPU control and by the serial
interface. Unused subcircuits and modules can be turned
off to reduce power consumption. The default state after
power-on is all subcircuits and modules powered off. This
enables low-power embedded systems to turn on only the
needed modules after exiting a low-power CPU halt timer
interval. Modules can be turned on and off as needed;
however, care must be exercised to allow for module ini-
tialization and settling prior to use.
Oscillator ControlThe MAX1464 has a fully integrated oscillator with a
nominal 4MHz frequency. An external clock source can be
used when the clock-select pin CKSEL = 0, operating all
internal timing functions. CKIO can also be configured as
an output source of the internal oscillator clock.
GPIO ModuleThe MAX1464 contains two general-purpose digital input/
output (GPIO) modules, GPIO1 and GPIO2, which can
be written and read by CPU control and by the serial
interface. These two I/O pins operate independently of
each other. They can be configured as inputs, outputs, or
one input and one output. When configured as an input,
there are two modes of sensing digital inputs; as a voltage
or logic level, or as an edge detector. In edge-detector
mode, either a rising or falling edge can be selected for
detection. A bit is set in the GPIO control register upon
detection of the selected edge.
The GPIO pins have nominal 100kΩ pulldown resistors to
VSS as in Figure 6. Pulldown resistors provide a low logic
level when the pin is unconnected. The GPIO may also
serve as an input pin and its state is read from the GPIO
control register (Tables 28 and 29). When using the GPIO
pin as a general-purpose output, its output state is defined
by writing to the GPIO control register.
The GPIOn pins can be configured as an alert output that
goes low or high whenever a fault condition happens,
e.g., remote sensor line disconnection, overflow condi-
tions in the CPU program execution, etc.
All input and output control for the GPIO1 and GPIO2
pins are contained in GPIO1_Control (address = 40h)
and GPIO2_Control (address = 41h), respectively. Figure
7 shows the GPIO1 and GPIO2 modules.
Serial Interface Timing and OperationThe MAX1464 serial interface is a high-speed asynchro-
20hTMR_Control
21hTMR_Config
PRESCALER
12-BIT COUNTER
TIMEOUT VALUE
MCLK
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
and write accessible by the serial inter-face for program-
ming of instruction code and calibration coefficients.
The MAX1464 serial interface can operate in 4-wire
SPI-compatible mode or in a 3-wire mode (default on
power-up). In 3-wire mode, the DI and DO lines can be
connected together, forming a bidirectional data line. The
serial interface lines consist of chip-select (CS), serial
clock (SCLK), data in (DI), and data out (DO).
The MAX1464 serial interface is selected by asserting
CS low. The serial input clock, SCLK, is gated internally
to begin sequencing the DI input data and outputting
the output data onto DO. When CS rises, the data that
was clocked into DI is loaded into an internal register set
(IRS[7:0]). The MAX1464 chip-select line CS cannot be
connected low continuously for normal operation.
The serial interface can be used both during sensor cali-
bration, as well as during normal operation. Each byte of
data written into the MAX1464 serial port contains a 4-bit
addresses nibble (IRSA [3:0]) and a 4-bit data nibble
(IRSD [3:0]). The IRS register holds both the IRSD and
IRSA nibbles as follows:
IRS [7:0] = IRSD [3:0], IRSA [3:0]
Four bytes of IRS information must be written into the
serial interface to transfer 16 bits of data through IRSD
into a MAX1464 internal register. All serial data written
into the MAX1464 is transferred through the IRS register.
The DI is read in with the LSB of the IRSA nibble first and
the MSB of the IRSD nibble last. Figure 8 shows serial
interface data input.
The IRSA bits are decoded to determine which register
the IRSD bits should be latched into. The IRSA bits can
address the DHR, the PFAR, the CR, and the IMR.
All serial data read from the serial interface is sourced
from the 16-bit DHR. Any data to be read by the serial
interface must first be placed into the internal DHR register
The entire 16-bit content of the DHR register is read
out through the DO pin by applying 16 successive clock
pulses to SCLK while CS remains low. DHR is clocked out
MSB bit first. Figure 9 shows the 4-wire mode data read
from the DHR register In 4-wire mode, data is transferred
into DI during the clocking of data out of DO. Therefore,
the last 8 bits clocked into the DI pin during this data trans-
fer are latched into the IRS register and decoded when CS
returns high.
When the MAX1464 serial interface is configured in 3-
wire mode, the 16-bit DHR data is read out immediately
following the command for 3-wire mode enable. Figure
10 shows the 3-wire enable command (IRS[7:0] = 19h)
clocked into DI with a subsequent 16-bit read of DHR
on DO. DO remains in high impedance (tri-state) until
the 3-wire enable command is received. Then DO goes
into low-impedance drive mode during the next low cycle
of CS. As SCLK is clocked 16 times, the data in DHR
is clocked out at DO. The 3-wire enable command is
the command that sets the MAX1464 ready for output
on DO on the next low cycle of CS. Following the DHR
output on the low cycle of CS, the DO line returns to high-
impedance state until the next 3-wire enable command is
received. The MAX1464 can receive an indefinite number
of inputs to DI without the need for a 3-wire enable com-
mand to be received.
When the IRSD[3:0] nibble is written to the command
register (CR), i.e., when IRSA[3:0] = 1000, the nibble is
decoded and a command operation is initiated. The com-
mand register decoding is shown in Table 39.
When the IRSD[3:0] nibble is written to the IMR, i.e.,
when IRSA[3:0] = 1000, the nibble is decoded and a
command operation is initiated. The IMR decoding is
shown in Table 40.
Note that after power is applied and the POR function
completes, the serial interface default is the 3-wire mode
for receiving data on DI only. The DO line is a highimped-
ance output until the MAX1464 receives either the 4-wire
or 3-wire mode command in the IMR. In the case of a
3-wire mode command, DO switches from a high imped-
ance state to a driving state only for the next cycle of CS,
returning to high impedance afterwards.
All commands, with the exception of programming or eras-
ing the FLASH memory, are completed within eight internal
master clock cycles of CS returning from low to high. This is 4μs for a 4MHz oscillator frequency or external clock
input (1 internal master clock = 2 external/internal oscil-
lator periods). FLASH memory programming and erasing
Figure 7. GPIO1 and GPIO2 Modules
GPIOn
40h OR 41hGPIOn_Control
EDGE OR LEVEL DETECT
VSS
100kΩ
TRI-STATE
BUFFER
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
FLASH MemoryThere are 4096 bytes of programmable/erasable FLASH
memory for CPU program instructions and coefficients
storage. In addition, there are 128 bytes of FLASH memory
accessible only by the serial interface for storage of user
information data.
These two FLASH memory locations are separated as par-
titions. The program/coefficient memory is FLASH partition
0 and the information memory is FLASH partition 1. Each
partition is accessible by the serial interface for reading,
erasing, and writing data. Program/ coefficient memory
partition 0 is accessible by the CPU as read only, and parti-
tion 1 is not accessible by the CPU. The CPU cannot erase
or write data to either of the FLASH memory partitions.
FLASH partition 0 is selected during the POR cycle. FLASH
partition 1 is selected by sending the halt CPU command
(IRS[7:0] = 78h) and changing the partition selected by
sending the change partition command (IRS[7:0] = F8h).
A following halt command (IRS[7:0] = 78h) resets the
selected partition to partition 0.
Modifying the FLASH ContentsThe MAX1464 FLASH memory contents must be erased
(contents = FFh) before the desired contents can be writ-
ten. There is no individual byte-erase command, but either
a total-erase command (IRS[7:0] = E8h) where all the
selected partition is erased (4kB for partition 0 or 128 bytes
for partition 1) or a page-erase command (IRS[7:0] = D8h),
where only 64 bytes are erased, and the page is selected
by PFAR[11:6]. There are 64 pages in FLASH partition 0,
and only 2 pages in FLASH partition 1.
The programming of the MAX1464 FLASH memory must
use the following procedure (all the commands are to be
sent through the serial interface, and are hexadecimal
values of IRS[7:0]):
Figure 8. Serial Interface Data Input
Figure 9. 4-Wire Mode Data Read from DHR Register
Figure 10. 3-Wire Mode Data Read from DHR Register
IRS0
IRSA0
IRS1
IRSA1
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
SCLK
IRS0
IRSA0
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
IRS0
IRSA0
IRS1
IRSA1
IRS2
IRSA2
IRS3
IRSA3
IRS4
IRSD0
IRS5
IRSD1
IRS6
IRSD2
IRS7
IRSD3
DHR15DHR14DHR13DHR12DHR11DHR10DHR9DHR8DHR7DHR6DHR5DHR4DHR3DHR2DHR1DHR0
SCLK
IRS1
IRSA1
DHR15DHR14DHR13DHR12DHR11DHR10DHR9DHR8DHR7DHR6DHR5DHR4DHR3DHR2DHR1DHR0
IRSA0
IRSA1
IRSA2
IRSA3
IRSD0
IRSD1
IRSD2
IRSD3
SCLK
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
1) Halt the CPU:
2) If partition 1 is to be modified, enter the following
command:
Otherwise, partition 0 is selected.
3) Turn off all analog modes:
03 02 01 00 (write 0000h to DHR[15:0])D4 (write Dh to PFAR[3:0])
08 (write DHR, 1000h to CPU port
pointed by PFAR[3:0], port D)
03 02 31 10 (write 0031h to DHR[15:0])
E4 (write Eh to PFAR[3:0])08 (write DHR, 0031h to CPU port-
pointed by PFAR[3:0], port E)
83 02 01 00 (write 8000h to DHR[15:0])
F4 (write Fh to PFAR[3:0])08 (write DHR, 8000h to CPU port-
pointed by PFAR[3:0], port F)
At this point, all the MAX1464 analog modules are off.
4) For erasing the whole partition, send the following
command:
Otherwise, if only a page erase is required, first write
PFAR[11:6] with the page address, as:
07 X6 X5 X4 (write 0XX0h to PFAR[15:0])Note that the 2 lower bits of PFAR[7:4] should be
zero, and only the upper 2 bits of that nibble should
be set to the desired value. Then, after writing the
page address, send the page-erase command:
5) Wait at least 4.2ms before sending any other com-
mand to allow the necessary time for the erase
operation to complete.
6) Write the address of the FLASH byte to be written to
PFAR[15:0]:
07 X6 X5 X4 (write 0XXXh to PFAR[15:0])7) Write the contents of the byte to DHR[7:0]:
X1 X0 (write XXh to DHR[7:0], high nibble at DHR[7:4])
8) Send the command to execute the FLASH write:
9) Repeat steps 6, 7, and 8 for all the bytes to be writ-
ten. It is not necessary to send the whole address and
data for every byte that is written. Only the nibbles
that are modified in the PFAR and in the DHR from
previous values must be changed. The time interval
between successive write commands (18h) must be at least 80μs.
10) If partition 1 was selected in step 2, and the user
wants to switch back to partition 0, send the following
command:
At this point, partition 0 is selected. The user may
want to go back to step 4 to program partition 0, or
just continue on.
Reading the FLASH ContentsThe procedure to read the FLASH contents is no different
from reading any other information from the MAX1464.
The FLASH contents must be copied to the DHR and read
through the serial interface:
1) If the CPU is not halted, halt the CPU:
2) If partition 1 is to be read, enter the following
command:
Otherwise, partition 0 is selected.
3) Write the address of the flash byte to be read to
PFAR[15:0]:
07 X6 X5 X4 (write 0XXXh to PFAR[15:0])4) Copy the contents of FLASH addressed by PFAR to
DHR:
5) If the interface is configured in 3-wire mode, send
to enable DO on the next CS cycle. Then tristate the
DI driver, and send 16 SCLK pulses on the following
CS cycle, and DO outputs DHR[15:0]. The FLASH
data is present at DHR[7:0]. See Figure 10 for details.
If the interface is configured in 4-wire mode, there is
no need to enable the DO line, as it has already been
enabled by a previous IRS command 09h. Send the
16 SCLK pulses and retrieve the data on the DO line.
6) Repeat steps 3, 4, and 5 for every byte to be read.
Only the nibbles that are modified in the PFAR regis-
ter are required to be sent.
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Program and Coeficient MemoryThe program and coefficient memory, FLASH partition
0, is addressed by the CPU and by the serial interface
sequentially from 0000h (0 dec) to 0FFFh (4095 dec).
Program execution by the CPU always begins at address
0000h and proceeds toward 0FFFh in 1-byte increments.
Although both the CPU and the serial interface can
address a 16-bit field, the FLASH size only uses 12 bits.
Therefore, the leading 4 MSBs of the address field are
ignored. It is advisable to have all leading bits of the 16-bit
address in PFAR[15:0] set to zero. The FLASH memory
in partition 0 can be erased in individual 64-byte pages
using the page-erase command, or erased in bulk using
the all-erase command. The information data memory
(partition 1) is unaffected by any operation performed on
partition 0.
Information Data MemoryThe information data memory, FLASH partition 1, is
addressed by bytes sequentially from 00h (0 dec) to 7Fh
(127 dec). The addressed byte should have all leading
bits of the 16-bit address in PFAR[15:0] set to zero. The
FLASH memory in partition 1 has only two 64-byte pages
that can be erased separately using the pageerase com-
mand, or erased together using the all-erase command.
Data in partition 0 is not affected by any operation per-
formed on partition 1.
MAX1464 CPU Instruction SetThe MAX1464 CPU has 16 instructions used to perform
all calculations for sensor compensation, linearization,
and signal output functions. Each instruction comprises
a 4-bit op code and a 4-bit CPU register address. The op
code describes what operation to perform; the register
address describes what register, or registers, to perform
the operation on.
Instruction FormatAll instructions are single-byte instructions with the excep-
tion of load data from instruction memory. LDX fetches the following bytes of instruction memory and loads them
into a register. This is how calibration and compensation
coefficients are stored within the MAX1464. Any number
of coefficients can be stored in instruction memory. The
instruction code format is as follows:
Instruction Set Details
LDX Load Register XOp-code: 0000 XXXXBINARY 0Xh
Operation:
X-register ← [PC+1] : [PC+2]
PC-register ← PC + 3 (point to next instruction)
CPU Cycles required:
3 cycles
Instruction:
Loads the next 2 bytes of program memory into CPU reg-
ister X. Register X can be any of the 16 CPU registers.
Program counter (PC) is incremented twice during the
fetches of the next 2 bytes and incremented a third time
to point to the next instruction in program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
CLX Clear Register XOp-code: 0001 XXXXBINARY 1Xh
Operation:
X-register ← 0000h
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Clear the contents of register X to 0000h.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
ANX AND Register X with Register AOp-code: 0010 XXXXBINARY 2Xh
Operation:
A-register ← A-register AND X-register
PC-register ← PC + 1 (point to next instruction)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
COMMAND OP CODE
(BITS 7–4)
REGISTER OP CODE
(BITS 3–0)Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Description:
Perform a 16-bit logical AND operation, bit for bit, on
the contents of the A-register and the contents of the
Xregister. Store the 16-bit result back into the A-register.
The previous contents of the A-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
ORX OR Register X with Register AOp-code: 0011 XXXXBINARY 3Xh
Operation:
A-register ← A-register OR X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit logical OR operation, bit for bit, on
the contents of the A-register and the contents of the
X-register. Store the 16-bit result back into the A-register.
The previous contents of the A-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
ADX ADD Register X to Register AOp-code: 0100 XXXXBINARY 4Xh
Operation:
A-register ← A-register + X-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
from the addition operation is lost. The previous contents
of the A-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
STX Store Register XOp-code: 0101 XXXXBINARY 5Xh
Operation:
X-register ← A-register
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit move operation from the A-register into
the X-register. The A-register contents are unchanged.
The previous contents of the X-register are overwritten
and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
SLX Shift Left Register XOp-code: 0110 XXXXBINARY 6Xh15131211109876543210
BIT: 15131211109876543210BIT: 15131211109876543210BIT:
REGISTER X
Operation when X 6h:
REGISTER R6
REGISTER M: R4
Operation when X = 6h:
PC-register ← PC + 1 (point to next instruction)
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
Description:
Perform a 16-bit shift-left operation on the contents of
X-register. The most significant bit, bit 15, is truncated and
lost. If register X is any CPU register other than register
R6, then a zero is appended into the LSB, bit 0. If X is
CPU register R6, then the data appended into the LSB
bit 0 is copied from the MSB of register R4. The contents
of register R4 are not affected. The operation does not
preserve the two’s-complement sign bit-15. The operation
is equivalent to an arithmetic multiplication by 2 on an
unsigned integer value stored in register X. The result is
stored back into the X-register. The previous contents of
the X-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is not preserved.
No branching occurs.
No other registers are affected.
SRX Shift Right Register XOp-code: 0111 XXXXBINARY 7Xh15131211109876543210BIT:
REGISTER X
Operation
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 15-bit shift-right operation on the contents of
X-register, preserving the contents of the two’s-comple-
ment sign bit-15 and propagating the sign bit, bit-15, into
bit-14. The least significant bit, bit 0, is truncated and lost.
The operation is equivalent to an arithmetic division by 2.
The result is stored back into the X-register. The previous
contents of the X-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
INX Increment Register XOp-code: 1000 XXXXBINARY 8Xh
Operation:
X-register ← X-register + 1
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit increment operation on the contents of
the X-register. Should the increment result in an overflow,
the overflow bit is truncated and lost. The result is stored
back into the X-register. The previous contents of the
X-register are overwritten and lost.
Register X can be any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
DEX Decrement Register XOp-code: 1001 XXXXBINARY 9Xh
Operation:
X-register ← X-register - 1
PC-register ← PC + 1 (point to next instruction)
CPU Cycles required:
1 cycle
Description:
Perform a 16-bit decrement operation on the contents of
the X-register. Should the decrement result in an under-
flow, the underflow bit is truncated and lost. The result is
stored back into the X-register. The previous contents of
the X-register are overwritten and lost. Register X can be
any of the 16 CPU registers.
PC is incremented once to point to the next instruction in
program memory.
Two’s-complement data format is preserved.
No branching occurs.
No other registers are affected.
NGX Negate Register XOp-code: 1010 XXXXBINARY AXh
MAX1464Low-Power, Low-Noise Multichannel
Sensor Signal Processor
