MAX1458CAE ,1%-Accurate / Digitally Trimmed Sensor Signal ConditionerApplicationsI.C. 3 14 INPPiezoresistive Pressure and AccelerationTEMP 4 MAX1458 13 BDRIVETransducer ..
MAX1459AAP ,2-Wire, 4-20mA Smart Signal ConditionerFeaturesThe MAX1459 highly integrated analog-sensor signal Highly Integrated Sensor Signal Conditi ..
MAX1459AAP+ ,2-Wire, 4-20mA Smart Signal ConditionerFeaturesThe MAX1459 highly integrated analog-sensor signal♦ Highly Integrated Sensor Signal Conditi ..
MAX145ACUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXApplications MAX144ACPA 0°C to +70°C 8 Plastic DIP ±0.5MAX144BCPA 0°C to +70°C 8 Plastic DI ..
MAX145ACUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXapplications, or for other circuits withINLdemanding power-consumption and space require-PART TEMP. ..
MAX145AEUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXFeaturesThe MAX144/MAX145 low-power, 12-bit analog-to-' Single-Supply Operation (+2.7V to +5.25V)di ..
MAX4052ACPE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 0; 1/96Low-Voltage, CMOS AnalogMultiplexers/Switches___ ..
MAX4052ACSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesMAX4051/A, MAX4052/A, MAX4053/A19-0463; Rev 0; 1/96Low-Voltage, CMOS AnalogMultiplexers/Switches___ ..
MAX4052ACSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX4052ACSE ,Low-Voltage / CMOS Analog Multiplexers/SwitchesApplications' Low Distortion: < 0.04% (600Ω)Battery-Operated Equipment' Low Crosstalk: < -90dB (50Ω ..
MAX4052ACSE+ ,Low-Voltage, CMOS Analog Multiplexers/SwitchesGeneral Description ________
MAX4052ACSE+T ,Low-Voltage, CMOS Analog Multiplexers/SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T to T , unl ..
MAX1458AAE-MAX1458CAE
1%-Accurate / Digitally Trimmed Sensor Signal Conditioner
General DescriptionThe MAX1458 highly integrated analog-sensor signal
processor is optimized for piezoresistive sensor calibra-
tion and compensation without any external compo-
nents. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit
DACs. Achieving a total error factor within 1% of the
sensor’s repeatability errors, the MAX1458 compen-
sates offset, offset temperature coefficient, full-span
output (FSO), FSO temperature coefficient (FSOTC),
and FSO nonlinearity of silicon piezoresistive sensors.
The MAX1458 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via digital-to-analog converters (DACs),
thereby eliminating quantization noise. Built-in testabili-
ty features on the MAX1458 result in the integration of
three traditional sensor-manufacturing operations into
one automated process:
Pretest:Data acquisition of sensor performance
under the control of a host test computer.
Calibration and compensation:Computation and
storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1458.
Final test operation:Verification of transducer cali-
bration and compensation without removal from the
pretest socket.
Although optimized for use with piezoresistive sensors,
the MAX1458 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.
______________________CustomizationMaxim can customize the MAX1458 for unique require-
ments. With a dedicated cell library consisting of more
than 90 sensor-specific functional blocks, Maxim can
quickly provide customized MAX1458 solutions. Please
contact Maxim for further information.
________________________ApplicationsPiezoresistive Pressure and Acceleration
Transducers and Transmitters
MAP (Manifold Absolute Pressure) Sensors
Automotive Systems
Hydraulic Systems
Industrial Pressure Sensors
FeaturesMedium Accuracy (±1%), Single-Chip Sensor
Signal ConditioningSensor Errors Trimmed Using Correction
Coefficients Stored in Internal EEPROM—
Eliminates the Need for Laser Trimming and
PotentiometersCompensates Offset, Offset-TC, FSO, FSOTC,
FSO LinearityProgrammable Current Source (0.1mA to 2.0mA)
for Sensor ExcitationFast Signal-Path Settling Time (<1ms)Accepts Sensor Outputs from 10mV/V to 40mV/V Fully Analog Signal Path
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner19-1373; Rev 0; 5/98
Ordering Information
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VDDto VSS......................................-0.3V to +6V
All Other Pins...................................(VSS- 0.3V) to (VDD+ 0.3V)
Short-Circuit Duration, FSOTC, OUT, BDRIVE...........Continuous
Continuous Power Dissipation (TA= +70°C)
SSOP (derate 8.00mW/°C above +70°C).....................640mW
Operating Temperature Ranges
MAX1458CAE......................................................0°C to +70°C
MAX1458AAE.................................................-40°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS (continued)(VDD= +5V, VSS= 0, TA= +25°C, unless otherwise noted.)
Note 1:Excludes the sensor or load current.
Note 2:All electronics temperature errors are compensated together with sensor errors.
Note 3:The sensor and the MAX1458 must always be at the same temperature during calibration and use.
Note 4:This is the maximum allowable sensor offset.
Note 5:This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge
voltage of 2.5V.
Note 6:Bit weight is ratiometric to VDD.
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
_______________Detailed DescriptionThe MAX1458 provides an analog amplification path for
the sensor signal. Calibration and temperature com-
pensation are achieved by varying the offset and gain
of a programmable-gain amplifier (PGA) and by varying
the sensor bridge current. The PGA uses a switched-
capacitor CMOS technology, with an input-referred
coarse offset trimming range of approximately ±63mV
(9mV steps). An additional output-referred fine offset
trim is provided by the Offset DAC (approximately
2.8mV steps). The PGA provides eight gain values from
+41V/V to +230V/V. The bridge current source is pro-
grammable from 0.1mA to 2mA.
The MAX1458 uses four 12-bit DACs and one 3-bit
DAC, with calibration coefficients stored by the user in
an internal 128-bit EEPROM. This memory contains the
following information as 12-bit-wide words:Configuration registerOffset calibration coefficientOffset temperature error compensation coefficientFSO (full-span output) calibration coefficientFSO temperature error compensation coefficient24 user-defined bits for customer programming of
manufacturing data (e.g., serial number and date)
Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and full-span output values
as a function of voltage.
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Pin Description
FSOTC CompensationSilicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(VBDRIVE) increases with temperature. This depen-
dence of VBDRIVEon the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensi-
tivity tempco (TCS) so that, with constant voltage exci-
tation, full-span output (FSO) will decrease with
temperature, causing a full-span output temperature
coefficient (FSOTC) error. However, if the bridge volt-
age can be made to increase with temperature at the
same rate that TCS decreases with temperature, the
FSO will remain constant.
FSOTC compensation is accomplished by resistor
RFTCand the FSOTC DAC, which modulate the excita-
tion reference current at ISRC as a function of tempera-
ture (Figure 3). FSO DAC sets VISRCand remains
constant with temperature while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
VBDRIVE, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSOTC errors are
compensated and FSO will be constant with tempera-
ture.
OFFSET TC CompensationCompensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
VBDRIVEthat must be added to the output summing
junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).
Analog Signal PathThe fully differential analog signal path consists of four
stages:Front-end summing junction for coarse offset correction3-bit PGA with eight selectable gains ranging from
41 through 230Three-input-channel summing junctionDifferential to single-ended output buffer (Figure 2)
Coarse Offset CorrectionThe sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR > 90dB, an input impedance of approxi-
mately 1MΩ, and a common-mode input voltage range
from VSSto VDD. At this summing junction, a coarse off-
set-correction voltage is added, and the resultant volt-
age is fed into the PGA. The 3-bit (plus sign)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage ref-
erence is 1.25% of VDD; thus, a VDDof 5V results in a
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal ConditionerFigure 1. Typical Pressure-Sensor Output
Figure 2. Signal-Path Block Diagram
MAX1458
Table 1. Input-Referred Offset DAC
Correction Values
Programmable-Gain AmplifierThe programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junc-
tion. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing JunctionThe third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the off-
set TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configu-
ration register. The offset sign bit determines if the off-
set correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.
Output BufferOUT can drive 0.1µF of capacitance. If CS is brought
low, OUT becomes high impedance (resulting in typical
output impedance of 1MΩ). The output is current limit-
ed and can be shorted to either VDDor VSSindefinitely.
The maximum output voltage can be limited using the
LIMIT pin. Output limiting can be performed for sensor
diagnostic purposes. Connect LIMIT to VDDto disable
the voltage-limiting feature.
Bridge DriveFine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor RISRCand by the voltage at node ISRC (con-
trolled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA @
14) and then made available at BDRIVE for sensor exci-
tation. Modulation of this current with respect to tem-
perature can be used to correct FSOTC errors, while
modulation with respect to the output voltage (VOUT)
can be used to correct FSO linearity errors.
Digital-to-Analog ConvertersThe four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from VDDand controls VISRC
which, in conjunction with RISRC, sets the baseline sen-
sor excitation current. The Offset DAC also takes its ref-
erence from VDDand provides a 1.22mV resolution with
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
a VDDof 5V. The output of the Offset DAC is fed into
the output summing junction where it is gained by
approximately 2.3, which increases the resulting out-
put-referred offset correction resolution to 2.8mV.
Both the Offset TC and FSOTC DACs take their refer-
ence from BDRIVE, a temperature-dependent voltage. A
nominal VBDRIVEof 2.5V results in a step size of 0.6mV.
The Offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the Offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via RFTCto correct FSOTC errors.
Internal ResistorsThe MAX1458 contains three internal resistors (RISRC,
RFTC, and RTEMP) optimized for common silicon PRTs.
RISRC(in conjunction with the FSO DAC) programs the
nominal sensor excitation current. RFTC(in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both RISRCand RFTChave a nominal value of 75kΩ. If
external resistors are used, RISRCand RFTCcan be dis-
abled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
RTEMPis a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100kΩat
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.
Internal EEPROMThe MAX1458 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal ConditionerFigure 3. Bridge Excitation Circuit
MAX1458Configuration register (Table 3) 12-bit calibration coefficients for the Offset and FSO
DACs12-bit compensation coefficients for the Offset TC
and FSOTC DACsTwo general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
Configuration RegisterThe configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (RFTCand
RISRC).
DAC RegistersThe Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 4. EEPROM Memory Map
Detailed Description of the Digital Lines
Chip-Select (CS) and Write-Enable (WE)CS is used to enable OUT, control serial communica-
tion, and force an update of the configuration and DAC
registers.A low on CS disables serial communication and
places OUT in a high-impedance state.A transition from low to high on CS forces an update
of the configuration and DAC registers from the
EEPROM when the “U” bit is zero.A transition from high to low on CS terminates pro-
gramming mode.A logic high on CS enables OUT and serial commu-
nication (seeCommunication Protocol section).
WE controls the refresh rate for the internal configura-
tion and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.A low on WE disables the erase/write operations and
also disables register refreshing from the EEPROM.A high on WE selects a refresh rate of approximately
400 times per second and enables EEPROM
erase/write operations.It is recommended that WE be connected to VSS
after the MAX1458 EEPROM has been programmed.
SCLK (Serial Clock)SCLK must be driven externally and is used to input
commands to the MAX1458 and read EEPROM con-
tents. Input data on DIO is latched on the rising edge of
SCLK. Noise on SCLK may disrupt communication. In
noisy environments, place a capacitor (0.01µF)
between SCLK and VSS.
Data Input/Output (DIO)The DIO line is an input/output pin used to issue com-
mands to the MAX1458 (input mode) or read the
EEPROM contents (output mode).
In input mode (the default mode), data on DIO is
latched on each rising edge of SCLK. Therefore, data
on DIO must be stable at the rising edge of SCLK and
should transition on the falling edge of SCLK.
DIO will switch to output mode after receiving a “READ
EEPROM” command, and will return the data bit
addressed by the digital value in the “READ EEPROM”
command. After a low-to-high transition or CS, DIO
returns to input mode and is ready to accept more
commands.
Communication ProtocolTo initiate communication, the first six bits on DIO after
CS transitions from low to high mustbe 1010U0
(defined as the INIT SEQUENCE). The MAX1458 will
then begin accepting 16-bit control words (Figure 4).
If the INIT SEQUENCE is not detected, all subsequent
data on DIO is ignored until CS again transitions from
low to high and the correct INIT SEQUENCE is received.
The “U” bit of the INIT SEQUENCE controls the updat-
ing of the DACs and configuration register from the
internal EEPROM. If this bit is low (U = 0), all four inter-
nal DACs and the configuration register will be updated
from the EEPROM on the next rising edge of CS (this is
also the default on power-up). If the “U” bit is high, the
DACs and configuration register will not be updated
from the internal EEPROM; they will retain their current
value on any subsequent CS rising edge. The
MAX1458 continues to accept control words until CS is
brought low.
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
MAX1458
Control WordsAfter receiving the INIT SEQUENCE on DIO, the MAX1458
begins latching in 16-bit control words, LSB first (Figure 5).
The first 12 bits (D0–D11) represent the data field. The
last four bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1458 supports the
commands listed in Table 5.
ERASE EEPROM CommandWhen an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic “0.” The data field of the 16-bit word is ignored.
Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.
BEGIN EEPROM WRITE CommandThe BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower
seven bits of the data field (A0–A6). The higher bits of
the data field (A7–A11) are ignored (Figure 6). Note that
to write to the internal EEPROM, WE and CS must be
1%-Accurate, Digitally Trimmed
Sensor Signal ConditionerFigure 5. Control-Word Timing Diagram
Figure 6. Timing Diagram for WRITE EEPROM Operation
