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MAX14550EETB+T
USB Host Charger Identification Analog Switch
USB Host Charger Identification Analog Switch
General Description
The MAX14550E is a USB Hi-Speed analog switch with USB host charger (dedicated charger) identification
circuit. The MAX14550E supports both the USB Battery
Charging Specification Revision 1.0 and a set resistor
bias for AppleM-compliant devices.
The MAX14550E features a high-performance Hi-Speed
USB switch with low 4pF (typ) on-capacitance and low
4I (typ) on-resistance. In addition, the MAX14550E
features two digital inputs (CB0 and CB1) to switch
between pass-through and charger modes. The USB
host charger identification circuit allows a host USB port
to support USB chargers with shorted D+/D- detection
and to provide support for Apple-compliant devices
using a resistor bias. When an Apple-compliant device
is attached to the port, the MAX14550E provides the
voltage from the resistor-divider. The MAX14550E uses
the internal or external resistor based on the voltage at
RDP. If a USB Revision 1.0-compliant device is attached,
the MAX14550E connects a short across DP and DM to
allow correct charger detection. The MAX14550E auto-
detection circuit can be disabled and either a DP/DM
short or resistor network is chosen as the default.
The MAX14550E has enhanced high electrostatic dis-
charge (ESD) protection on the DP and DM inputs up to
Q15kV Human Body Model (HBM).
The MAX14550E is available in a 10-pin (3mm x 3mm)
TDFN package and is specified over the -40NC to +85NC
extended temperature range.
FeaturesUSB 2.0 Hi-Speed SwitchingLow 4.0pF On-CapacitanceLow 4.0ω On-ResistanceUltra-Low 0.1ω On-Resistance Flatness+2.8V to +5.5V Supply RangeUltra-Low 7µA Supply CurrentAutomatic USB Charger Identification CircuitOptional External Resistor-Divider with Auto
Selection±15kV High ESD HBM Protection on DP/DM3mm x 3mm, 10-Pin TDFN Package
Applications
Laptops
Netbooks
Cell Phones
Ordering Information
19-4745; Rev 2; 1/10
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit appears at end of data sheet.
Apple is a registered trademark of Apple, Inc.
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
TOP
MARK
MAX14550EETB+-40NC to +85NC10 TDFN-EP*AWG
USB Host Charger Identification Analog Switch
MAX14550E
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VCC, DP, DM, TDP, TDM, RDP,
RDM, CB_ to GND ...............................................-0.3V to +6V
Continuous Current Into Any Terminal ...........................Q30mA
Continuous Power Dissipation (TA = +70NC)
10-Pin TDFN (derate 24.4mW/NC above +70NC) .......1951mW
Thermal Resistance (Note 1)
Junction-to-Ambient Thermal Resistance (BJA) ...........41NC/W
Junction-to-Case Thermal Resistance (BJC) ..................9NC/W
Operating Temperature Range ..........................-40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................-65NC to +150NC
Soldering Temperature (Reflow) .......................................260NC
ELECTRICAL CHARACTERISTICS
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to /thermal-tutorial.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Power-Supply VoltageVCC2.85.5V
Supply CurrentICC
VCC = 3.3V
VCB0 = VCB = VCC0.72
VCB0 = 0V, VCB = VCC6.510
External resistors used,
VCB0 = VCB = 0V or
VCB0 = VCC, VCB = 0V12
Internal resistors used,
VCB0 = VCB = 0V or
VCB0 = VCC, VCB = 0V120
VCC = 5.5V
VCB0 = VCB = VCC2.57
VCB0 = 0V, VCB = VCC8.515
External resistors used,
VCB0 = VCB = 0V or
VCB0 = VCC, VCB = 0V16
Internal resistors used,
VCB0 = VCB = 0V or
VCB0 = VCC, VCB = 0V
Supply Current IncreaseDICC0V P VCB_ P VIL or VIH P VCB_ P VCC2FA
Analog Signal RangeVDP, VDM0VCCV
ANALOG SWITCH
On-Resistance TDP/TDM
SwitchRONT0V P VDP/DM P VCC, IDP or IDM = 10mA46.5I
On-Resistance Match
Between Channels TDP/TDM
Switch
DRONTVDP = VDM = 400mV, IDP or IDM = 10mA0.1I
USB Host Charger Identification Analog Switch
MAX14550E
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
On-Resistance Flatness TDP/
TDM SwitchRFLATTVDP = VDM, 0V P VDP P VCC,
IDP = IDM = 10mA0.1I
On-Resistance RDP/RDM
SwitchRONR0.4V P VRDP/RDM P VCC, IRDP = IRDM =
10mA47.5I
On-Resistance Flatness RDP/
RDM SwitchRFLATRVRDP = VRDM, 0.4V P VRDP P VCC,
IRDP = IRDM = 10mA0.1I
On-Resistance of DP/DM
ShortRSHORTVCB0 = 0V, VCB = VCC, VDP = VDM,
0V P VDP P VCC, IDP = IDM = 1mA5070I
TDP/TDM Off-Leakage
Current
ITDPOFF,
ITDMOFF
VCC = 5.5V, VCB0 = VCC, VCB = 0V, VDP =
VDM = 5.5V to 0V, VTDP = VTDM = 0V to 5.5V-250+250nA
DP/DM On-Leakage CurrentIDPON,
IDMON
VCC = 5.5V, VCB0 = VCB = VCC,
VDP = VDM = 5.5V to 0V-250+250nA
DYNAMIC PERFORMANCE
Turn-On TimetONVTDP or VTDM = 1.5V, RL = 300I,
CL = 35pF, VIH = VCC, VIL = 0V, Figure 120100Fs
Turn-Off TimetOFFVTDP or VTDM = 1.5V, RL = 300I,
CL = 35pF, VIH = VCC, VIL = 0V, Figure 12.55Fs
TDP/TDM Switch Propagation
DelaytPLH, tPHLRL = RS = 50I 60ps
Output Skew Between
SwitchestSK(O)Skew between DP and DM when connected
to TDP and TDM, RL = RS = 50I, Figure 240ps
TDP/TDM Off-CapacitanceCOFFf = 1MHz, VBIAS = 0V, VSIGNAL = 500mVP-P
(Note 3)2.0pF
DP/DM On-Capacitance
(Connected to TD_ )CONf = 240MHz, VBIAS = 0V,
VSIGNAL = 500mVP-P4.05.5pF
-3dB BandwidthBWRL = RS = 50I1000MHz
Off-IsolationVISOVTDP, VDP = 0dBm, RL = RS = 50I,
f = 250MHz, Figure 3-20dB
CrosstalkVCTVTDP, VDP = 0dBm, RL = RS = 50I,
f = 250MHz, Figure 3-25dB
INTERNAL RESISTORS
DP/DM Short PulldownRPD350500700kI
RP1/RP2 RatioRTRP1.4851.51.515Ratio
RP1 + RP2 ResistanceRRP93.75125156.25kI
RM1/RM2 RatioRTRM0.8540.8630.872Ratio
RM1 + RM2 ResistanceRRM69.7593116.25kI
USB Host Charger Identification Analog Switch
MAX14550E
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.8V to +5.5V, TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25NC, unless
otherwise noted.) (Note 2)
Note 2: All devices are 100% production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Guaranteed by design.
Test Circuits/Timing Diagrams
tR < 5ns
tF < 5ns50%
VIL
LOGIC
INPUT
GND
CB0
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VIN ( RL ) RL + RON
VIN
VIH
tOFF
TD_
CB1
0.9 x V0UT0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
VCC
VCC
VOUT
MAX14550E
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
COMPARATORS
DM Comparator ThresholdVDMFVRDP > 0.4V, DM falling1.92.12.3V
VRDP < 0.3V, DM falling444546%VCC
DP and RDP Comparator
ThresholdVDPRDP or RDP falling0.30.350.4V
DM Comparator Hysteresis1%VDMF
DP and RDP Comparator
Hysteresis1%VDPR
DM Comparator Debounce
TimetDMVDM from 2.8V to 1.5V30100200Fs
DP Comparator Debounce
TimetDPVDP from 0.7V to 0V30100200Fs
DIGITAL I/O (CB0, CB1)
Input Logic Voltage HighVIH1.4V
Input Logic Voltage LowVIL0.4V
Input Logic HysteresisVHYST100mV
Input Leakage CurrentIINVCC = 5.5V, 0V P VCB_ P VIL or
VIH P VCB_ P VCC-250+250nA
ESD PROTECTION
All PinsHuman Body ModelQ2kV
ESD Protection Level (DP and
DM Only)Human Body ModelQ15kV
USB Host Charger Identification Analog Switch
MAX14550E
Test Circuits/Timing Diagrams (continued)
Figure 2. Output Signal Skew
IN+
IN-
CB0CB1
OUT+
OUT-
VIN+
VIN-
VOUT+
VOUT-
TDP
TDM
VCC
VCC
VCC
VCC
tSK(0)
tINFALLtINRISE
tOUTFALLtOUTRISE
RISE TIME DELAY = |tINRISE - tOUTRISE|
FALL TIME DELAY = |tINFALL - tOUTFALL|
RISE TIME TO FALL TIME MISMATCH = |tOUTFALL - tOUTRISE|
50%
50%
50%
50%
90%
10%
90%
10%
90%
10%
90%
10%
VCC
VCC
MAX14550E
USB Host Charger Identification Analog Switch
MAX14550E
Test Circuits/Timing Diagrams (continued)
Figure 3. Off-Isolation and Crosstalk
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
TDP/TDM ON-RESISTANCE
vs. SUPPLY VOLTAGE
MAX14550E toc01
VTDP (V)
VCC = 2.8V
VCC = 5.5V
TDP/TDM ON-RESISTANCE vs. VTDP/TDM
MAX14550E toc02
VTDP/TDM (V)
VCC = 3.3V
TA = +85°C
TA = +25°C
TA = -40°C
RDP/RDM ON-RESISTANCE
vs. SUPPLY VOLTAGE
MAX14550E toc03
VRDP (V)
VCC = 2.8V
VCC = 5.5V
SWITCH IS ENABLED.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
VOUT
CB1
CB0VCC
VCC
TDP
DP*
VIN
OFF-ISOLATION = 20log VOUT
VIN
CROSSTALK = 20log VOUT
VIN
NETWORK
ANALYZER
50I
50I50I
50I
MEASREF
0V OR VCC
*FOR CROSSTALK, THIS PIN IS DM.
TDM AND DP ARE OPEN.
MAX14550E
USB Host Charger Identification Analog Switch
MAX14550E
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
MAX14550E toc09
VCC (V)
LOGIC-INPUT THRESHOLD (V)
CB_ RISING
CB_ FALLING
TURN-ON/TURN-OFF TIME
vs. SUPPLY VOLTAGE
MAX14550E toc08
VCC (V)
TURN-ON/TURN-OFF TIME (µs)
tON
tOFF
SUPPLY CURRENT
vs. LOGIC LEVEL
MAX14550E toc07
LOGIC LEVEL (V)
ICC
(µA)
INTERNAL RESISTOR-
DIVIDER
EXTERNAL RESISTOR-
DIVIDER
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX14550E toc06
VCC (V)
ICC
(µA)
TA = -40°C
TA = +85°C
TA = +25°C
VCB0 = VCC
VCB1 = 0V
VRDP = VCC
TDP/DP LEAKAGE CURRENT
vs. TEMPERATURE
MAX14550E toc05
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)603045-15015-30
ON-LEAKAGE
OFF-LEAKAGE
RDP/RDM ON-RESISTANCE vs. VRDP/RDM
MAX14550E toc04
VRDP/RDM (V)
VCC = 3.3V
TA = +85°C
TA = +25°C
TA = -40°C
EYE DIAGRAM
DIFFERENTIAL SIGNAL (V)
MAX14550E toc11FREQUENCY RESPONSE
MAX14550E toc10
MAGNITUDE (dB)
ON-LOSS
CROSSTALK
OFF-ISOLATION
USB Host Charger Identification Analog Switch
MAX14550E
Pin Description
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Pin Configuration
AUTODETECTION MODE
MAX14550E toc12
100µs/div
500mV/div
500mV/divINTERNAL RESISTOR-
DIVIDERS ENABLED
DP RISING
MAX14550E toc13
4µs/div
VCC = 2.8V, RL = 300I, CL = 35pF
DP RISING
MAX14550E toc14
4µs/div
VCC = 4V, RL = 300I, CL = 35pF
PINNAMEFUNCTIONCB0Switch Control Bit 0. See the Switch Control section.DPUSB Connector D+ ConnectionDMUSB Connector D- ConnectionGNDGroundRDPExternal Resistor Bias Input for D+ and Selection for External Resistors in RDP and RDMRDMExternal Resistor Bias Input for D- VCCPower Supply. Bypass VCC to GND through a 0.1FF capacitor. Place the capacitor as close as possible to the device.TDMUSB Transceiver D- ConnectionTDPUSB Transceiver D+ ConnectionCB1Switch Control Bit 1. See the Switch Control section.+
CB1
TDM
VCC
CB0
GND
MAX14550E9TDPDP6RDMRDP
TDFN
(3mm × 3mm)
TOP VIEW
*EP
*CONNECT EP TO GND.
USB Host Charger Identification Analog Switch
MAX14550E
Functional Diagram
Detailed Description
The MAX14550E is a combination of a Hi-Speed USB
analog switch and a charger host identification detec-
tion analog switch, which allows USB hosts to identify
the USB port as a charger port when the USB host is in
a low-power mode and cannot enumerate USB devices.
The MAX14550E features a high-performance, Hi-Speed
USB switch with low 4pF on-capacitance and low 4I on-
resistance. DP and DM can survive signals between 0V
and 6V with any supply voltage.
Resistor-Dividers
The MAX14550E features an internal resistor-divider for
biasing or can operate with external resistors. Connect
RDP to ground to use the internal resistor-divider (see
the Typical Operating Circuit). The user must provide 5V
supply voltage to VCC when the internal resistor-divider
is used. When the MAX14550E is not operated with the
internal resistor-dividers, the device disconnects the
internal resistor-dividers’ pullup voltage (VCC_SW) to
minimize supply current requirements.
Connect RDP to a voltage above 0.4V (max) to use
external resistors (Figure 4). Internal resistor-dividers are
always disconnected from the supply voltage when exter-
nal resistor-dividers are detected at RDP (VRDP > 0.4V).
Switch Control
The MAX14550E features two digital inputs, CB0 and
CB1, for mode selection (Table 1). Connect CB0 and
CB1 to a logic-level low voltage for autodetection mode
(see the Autodetection section).
Connect CB0 and CB1 to a logic-level high voltage for
normal Hi-Speed USB bypass functionality.
Connect CB0 to a logic-level low and CB1 to a logic-level
high voltage to select charger mode. Optionally, CB0
and CB1 can be forced to set the detection to a par-
ticular state. The USB Implementers Forum (USB-IF) has
defined that dedicated chargers have D+ and D- shorted
together. In USB charger mode, DP and DM are shorted
together for dedicated charging functionality. Connect
CB0 to a logic-level high and CB1 to a logic-level low
voltage to force the resistor network to be connected to
DP and DM.
RDP
RDM
TDPTDM
CBOCB1GND
0.4V
2.1V
VCC_SWVCC
RP2
RP1
VCC_SW
RM2
RM1
MAX14550EQCONTROL
LOGIC
0.4V500kI
ESD
PROTECTION
