MAX1449EHJ+ ,10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal ReferenceELECTRICAL CHARACTERISTICS(V = 3.3V, OV = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to ..
MAX144ACPA+ ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAXELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V, V = 2.5V, 0.1μF capacitor at REF, f = 2.17MHz, 16 c ..
MAX144AEUA+ ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAXFeaturesThe MAX144/MAX145 low-power, 12-bit analog-to-♦ Single-Supply Operation (+2.7V to +5.25V) ® ..
MAX144AEUA+T ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin µMAXApplications0°C toMAX144BCUA 8 µMAX ±1 U8-1+70°CBattery-Powered Systems Instrumentation 0°C toMAX14 ..
MAX144BCPA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXMAX144/MAX14519-1387; Rev 0; 11/98+2.7V, Low-Power, 2-Channel, 108ksps,Serial 12-Bit ADCs in 8-Pin ..
MAX144BCUA ,+2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAXApplications MAX144ACPA 0°C to +70°C 8 Plastic DIP ±0.5MAX144BCPA 0°C to +70°C 8 Plastic DI ..
MAX4042ESA ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsFeaturesThe MAX4040–MAX4044 family of micropower op amps' Single-Supply Operation Down to +2.4Voper ..
MAX4042ESA ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS—T = +25°CA(V = +5.0V, V = 0, V = 0, V = V / 2, SHDN = V , R = 100kΩ tied ..
MAX4042ESA+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsELECTRICAL CHARACTERISTICS—T = +25°CA(V = +5.0V, V = 0V, V = 0V, V = V / 2, SHDN = V , R = 100kΩ ti ..
MAX4042EUA ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsGeneral Description ________
MAX4042EUA+ ,Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op AmpsFeaturesThe MAX4040–MAX4044 family of micropower op amps♦ Single-Supply Operation Down to +2.4Voper ..
MAX4043ESD ,Single/Dual/Quad / Low-Cost / SOT23 / Micropower Rail-to-Rail I/O Op AmpsMAX4040–MAX404419-1377; Rev 0; 5/98Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O O ..
MAX1449EHJ+
10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference
General DescriptionThe MAX1449 3.3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10-
stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully dif-
ferential signal path. The ADC is optimized for low-
power, high-dynamic performance in imaging and digital
communications applications. The converter operates
from a single 2.7V to 3.6V supply, consuming only
186mW while delivering a 58.5dB (typ) signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differ-
ential input stage has a -3dB 400MHz bandwidth and
may be operated with single-ended inputs. In addition to
low operating power, the MAX1449 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is
used to set the ADC’s full-scale range. A flexible refer-
ence structure allow’s the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Lower speed, pin-compatible versions of the MAX1449
are also available. Refer to the MAX1444 data sheet for
a 40Msps version, the MAX1446 data sheet for a
60Msps version, and the MAX1448 data sheet for 80Msps.
The MAX1449 has parallel, offset binary, CMOS-com-
patible, three-state outputs that can be operated from
1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5mm x 5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
________________________ApplicationsUltrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
FeaturesSingle 3.3V OperationExcellent Dynamic Performance
58.5dB SNR at fIN= 20MHz
72dBc SFDR at fIN= 20MHz Low Power
62mA (Normal Operation)
5μA (Shutdown Mode)Fully Differential Analog InputWide 2Vp-p Differential Input Voltage Range400MHz -3dB Input BandwidthOn-Chip 2.048V Precision Bandgap ReferenceCMOS-Compatible Three-State Outputs32-Pin TQFP PackageEvaluation Kit Available (MAX1448 EV Kit)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal ReferenceCLK
IN+
CONTROL
PIPELINE ADC
REF SYSTEM +
BIAS
OUTPUT
DRIVERS
REF
REFINREFOUTREFPCOMREFNOE
VDD
GND
OVDD
OGND
D9–D0
IN-
T/H
MAX1449
Functional Diagram19-4802; Rev 2; 9/04
EVALUATION KIT
AVAILABLE
Ordering Information
Pin Configuration appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGEMAX1449EHJ-40°C to +85°C32 TQFP
PARTSAMPLING SPEED (Msps)MAX144440
MAX144660
MAX144880
Pin-Compatible, Lower Speed
Selection Table
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN= 2.048V, REFOUT connected to
REFIN through a 10kΩresistor, VIN= 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK= 105MHz, TA= TMIN
to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to VDD
REFIN, REFOUT, REFP,
REFN, and COM to GND........................-0.3V to (VDD+ 0.3V)
OE, PD, CLK to GND..................................-0.3V to (VDD+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C).....1495.3mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACYResolution10Bits
Integral NonlinearityINLfIN = 7.5MHz, TA ≥ +25°C–0.75±2.4LSB
Differential NonlinearityDNLfIN = 7.5MHz, no missing codes
guaranteed, TA ≥ +25°C–0.5–1.0LSB
Offset Error< –1–1.7% FS
Gain ErrorTA ≥ +25°C, TA ≥ +25°C0–2% FS
ANALOG INPUTInput Differential RangeVDIFFDifferential or single-ended inputs–1.0V
Common-Mode
Voltage RangeVCOMVDD/2 0.5V
Input ResistanceRINSwitched capacitor load20kΩ
Input CapacitanceCIN5pF
CONVERSION RATEMaximum Clock FrequencyfCLK105MHz
Data Latency5.5Cycles
DYNAMIC CHARACTERISTICS (fCLK = 105.26MHz, 4096-point FFT)fIN = 7.5MHz55.958.5
fIN = 20MHz55.558.5Signal-to-Noise Ratio
(Note 1)SNR
fIN = 50MHz58
fIN = 7.5MHz55.358.2
fIN = 20MHz54.558.1Signal-to-Noise + Distortion (Up
to 5th Harmonic) (Note 1)SINAD
fIN = 50MHz57.6
fIN = 7.5MHz6272
fIN = 20MHz6172Spurious-Free Dynamic
Range (Note 1)SFDR
fIN = 50MHz70
dBc
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfIN = 7.5MHz-72
fIN = 20MHz-72Third-Harmonic Distortion
(Note 1)HD3
fIN = 50MHz-70
dBc
Intermodulation Distortion (First 5
Odd-Order IMDs)
(Note 2)
IMDf1 = 38MHz at -6.5dB FS
f2 = 42MHz at -6.5dB FS-76dBc
Third-Order Intermodulation
Distortion (Note 2)IM3f1 = 38MHz at -6.5dB FS
f2 = 42MHz at -6.5dB FS-76dBc
fIN = 7.5MHz-70-62
fIN = 20MHz-70-60
Total Harmonic Distortion
(First 5 Harmonics)
(Note 1)
THD
fIN = 50MHz-70
dBc
Small-Signal BandwidthInput at -20dB FS, differential inputs500MHz
Full-Power BandwidthFPBWInput at -0.5dB FS, differential inputs400MHz
Aperture DelaytAD1ns
Aperture JittertAJ2psRMS
Overdrive Recovery TimeFor 1.5 x full-scale input2ns
Differential Gain–1%
Differential Phase–0.25Degrees
Output NoiseIN+ = IN- = COM0.2LS BRM S
INTERNAL REFERENCEReference Output VoltageREFOUT2.0481%V
Reference Temperature
CoefficientTCREF60ppm/°C
Load Regulation1.25mV/mA
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)REFIN Input Voltage2.048
Positive Reference Output
Voltage2.012V
Negative Reference Output
Voltage0.988V
Common-Mode LevelVDD / 2V
Differential Reference Output
Voltage RangeVREFINΔVREF = VREFP - VREFN, TA ≥ +25°C0.981.0241.07V
REFIN ResistanceVREFP>50MΩ
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN= 2.048V, REFOUT connected to
REFIN through a 10kΩresistor, VIN= 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK= 105MHz, TA= TMIN
to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at TA= +25°C.)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMaximum REFP, COM Source
CurrentVREFN5mA
Maximum REFP, COM Sink
CurrentVCOM-250µA
Maximum REFN Source CurrentISOURCE250µA
Maximum REFN Sink CurrentISINK-5mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)REFP, REFN Input ResistanceRREFP,
RREFN
Measured between REFP and COM and
REFN and COM4kΩ
REFP, REFN, COM Input
CapacitanceCIN15pF
Differential Reference Input
Voltage RangeΔVREFΔVREF = VREFP - VREFN1.02410%V
COM Input Voltage RangeVCOMVDD / 210%V
REFP Input VoltageVREFPVCOM+
ΔVREF / 2V
REFN Input VoltageVREFNVCOM-
ΔVREF / 2V
DIGITAL INPUTS (CLK, PD, OE)CLK0.8 x
VDD
Input High ThresholdVIH
PD, OE0.8 x
VDD
CLK0.2 x
VDD
Input Low ThresholdVIL
PD, OE0.2 x
VDD
Input HysteresisVHYST0.1V
IIHVIH = VDD = OVDD–5µAInput LeakageIILVIL = 0–5
Input CapacitanceCIN5pF
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN= 2.048V, REFOUT connected to
REFIN through a 10kΩresistor, VIN= 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK= 105MHz, TA= TMIN
to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at TA= +25°C.)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
Note 1:SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2:Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3:Digital outputs settle to VIH,VIL.
Note 4:With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL OUTPUTS (D9–D0)Output Voltage LowVOLISINK = 200µA0.2V
Output Voltage HighVOHISOURCE = 200µAOVDD
- 0.2V
Three-State Leakage CurrentILEAKOE = OVDD–10µA
Three-State Output CapacitanceCOUTOE = OVDD5pF
POWER REQUIREMENTSAnalog Supply VoltageVDD2.73.33.6V
Output Supply VoltageOVDD1.73.33.6V
Operating, fIN = 20MHz at -0.5dB FS5874mAAnalog Supply CurrentIVDDShutdown, clock idle, PD = OE = OVDD415µA
Operating, CL = 15pF , fIN = 20MHz at
-0.5dB FS10mAOutput Supply CurrentIOVDD
Shutdown, clock idle, PD = OE = OVDD120µA
Offset–0.1mV/VPower Supply RejectionPSRRGain–0.1%/V
TIMING CHARACTERISTICSCLK Rise-to-Output Data ValidtDOFigure 6 (Note 3)58ns
OE Fall-to-Output EnabletENABLEFigure 510ns
OE Rise-to-Output DisabletDISABLEFigure 515ns
CLK Pulse Width HightCHFigure 6, clock period 9.52ns4.76
±0.47ns
CLK Pulse Width LowtCLFigure 6, clock period 9.52ns4.76
±0.47ns
Wake-Up TimetWAKE(Note 4)1.5µs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.3V, OVDD= 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN= 2.048V, REFOUT connected to
REFIN through a 10kΩresistor, VIN= 2VP-P (differential with respect to COM), CL= 10pF at digital outputs, fCLK= 105MHz, TA= TMIN
to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at TA= +25°C.)
Typical Operating Characteristics(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
FFT PLOT (fIN = 7.5MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1449 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SNR = 58.6dB
SINAD = 58.4dB
THD = -72.7dBc
SFDR = 73.6dBc
2ND HARMONIC
3RD HARMONIC
MAX1449 toc02
FFT PLOT (fIN = 19.99MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SNR = 58.5dB
SINAD = 58.4dB
THD = -73.7dBc
SFDR = 75.9dBc
2ND HARMONIC
3RD HARMONIC
MAX1449 toc03
FFT PLOT (fIN = 50.12MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SNR = 57.9dB
SINAD = 56.7dB
THD = -71.3dBc
SFDR = 71.1dBc
2ND HARMONIC
3RD HARMONIC
MAX1449 toc04
FFT PLOT (fIN = 7.5MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SNR = 57.7dB
SINAD = 57.5dB
THD = -71.8dBc
SFDR = 74.4dBc
2ND HARMONIC
3RD HARMONIC
MAX1449 toc05
FFT PLOT (fIN = 19.99MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SNR = 57.7dB
SINAD = 57.2dB
THD = -67dBc
SFDR = 67.7dBc
2ND HARMONIC
3RD HARMONIC
MAX1449 toc06
TWO-TONE INTERMODULATION
(8192-POINT IMD, DIFFERENTIAL INPUT)ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
f1 = 38MHz AT -6.5dB FS
f2 = 42MHz AT -6.5dB FS
2ND-ORDER IMD
3RD-ORDER IMD
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1449 toc07
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)62
DIFFERENTIAL
SINGLE ENDED
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1449 toc08
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)54DIFFERENTIAL
SINGLE ENDED
THD (dBc)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1449 toc09
ANALOG INPUT FREQUENCY (MHz)
DIFFERENTIAL
SINGLE ENDED
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
SINAD (dB)
SIGNAL-T0-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1449 toc10
ANALOG INPUT FREQUENCY (MHz)DIFFERENTIAL
SINGLE-ENDED100010010
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE ENDEDMAX1449 toc11
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY, SINGLE ENDED
MAX1449 toc12
ANALOG INPUT FREQUENCY (MHz)
VIN = 100mVp-p
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (fIN = 19MHz)
MAX1449 toc13
ANALOG INPUT POWER (dB FS)
SFDR (dBc)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (fIN = 19MHz)MAX1449 toc14
ANALOG INPUT POWER (dB FS)
SNR (dB)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (fIN = 19MHz)
MAX1449 toc15
ANALOG INPUT POWER (dB FS)
THD (dBc)
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT POWER (fIN = 19MHz)
MAX1449 toc16
ANALOG INPUT POWER (dB FS)
SINAD (dB)
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
MAX1449 toc17
TEMPERATURE (°C)
SFDR (dBc)
fIN = 26.1696MHz
SIGNAL-TO-NOISE vs. TEMPERATURE
MAX1449 toc18
TEMPERATURE (°C)
SNR (dB)
fIN = 26.1696MHz
ypical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
MAX1449 toc19
TEMPERATURE (°C)
THD (dBc)
fIN = 26.1696MHz
SIGNAL-TO-NOISE + DISTORTION
vs. TEMPERATURE
MAX1449 toc20
TEMPERATURE (°C)
SINAD (dB)
fIN = 26.1696MHz
INTEGRAL NONLINEARITY vs.
DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)
MAX1449 toc21
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1449 toc22
DIGITAL OUTPUT CODE
DNL (LSB)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE, VREFIN = +2.048V
MAX1449 toc23
TEMPERATURE (°C)
GAIN ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE, VREFIN = +2.048V
MAX1449 toc24
TEMPERATURE (°C)
OFFSET ERROR (LSB)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1449 toc26
TEMPERATURE (°C)
VDD
(mA)
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1449 toc27
TEMPERATURE (°C)
IOVDD
(mA)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1449 toc25
VDD (V)
IVDD
(mA)
Typical Operating Characteristics (continued)(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1449 toc28
TEMPERATURE (°C)
IOVDD
(mA)
ANALOG POWER-DOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1449 toc29
VDD (V)
IVDD
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1449 toc30
OVDD (V)
OVDD
(
SNR/SINAD, THD/SFDR
vs. CLOCK FREQUENCY
MAX1449 toc31
CLOCK FREQUENCY (MHz)
SNR/SINAD, THD/SFDR (dB, dBc)
fIN = 50.123MHz
SFDR
SNR
SINAD
THD
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1449 toc32
VDD (V)
REFOUT
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1449 toc33
TEMPERATURE (°C)
REFOUT
(V)
20,000
10,000
40,000
30,000
60,000
50,000
70,000
N-2NN-1N+1N+2
OUTPUT NOISE HISTOGRAM (DC INPUT)MAX1449 toc34
DIGITAL OUTPUT CODE
COUNTS607
Typical Operating Characteristics (continued)
(VDD= 3.3V, OVDD= 2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL≈10pF, TA= +25°C, unless
otherwise noted.)
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
Pin Description
PINNAMEFUNCTIONREFNLower Reference. Conversion range is –(VREFP - VREFN).
Bypass to GND with a > 0.1µF capacitor.COMCommon-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor.
3, 9, 10VDDAnalog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF.
4, 5, 8, 11,
14, 30GNDAnalog GroundIN+Positive Analog Input. For single-ended operation connect signal source to IN+.IN-Negative Analog Input. For single-ended operation connect IN- to COM.CLKConversion Clock InputPD
Power Down Input.
High: Power-down mode
Low: Normal operationOE
Output Enable Input.
High: Digital outputs disabled
Low: Digital outputs enabled
16–20D9–D5Three-State Digital Outputs D9–D5. D9 is the MSB.OVDDOutput Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.T.P.Test Point. Do not connect.OGNDOutput Driver Ground
24–28D4–D0Three-State Digital Outputs D4–D0. D0 is the LSB.REFOUTInternal Reference Voltage Output. May be connected to REFIN through a resistor or a resistor-
divider.REFINReference Input. VREFIN = 2 x (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor.REFPUpper Reference. Conversion range is –(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor.
MAX1449
10-Bit, 105Msps, Single 3.3V, Low-Power
ADC with Internal Reference
Detailed DescriptionThe MAX1449 uses a 10-stage, fully differential,
pipelined architecture (Figure 1), that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a 1-
bit resolution. Digital error-correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes.
Input Track-and-Hold (T/H) CircuitFigure 2displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors C2a
and C2b through switches S4a and S4b. Switches S2a
and S2b set the common mode for the amplifier input,
and open simultaneously with S1, sampling the input
waveform. Switches S4a and S4b are then opened
before switches S3a and S3b connect capacitors C1a
and C1b to the output of the amplifier and switch S4c is
closed. The resulting differential voltage is held on
capacitors C2a and C2b. The amplifier is used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. This value is then pre-
sented to the first stage quantizer and isolates the
pipeline from the fast-changing input. The wide input
bandwidth T/H amplifier allows the MAX1449 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs IN+ and IN- can be
driven either differentially or single-ended. It is recom-
mended to match the impedance of IN+ and IN- and
set the common-mode voltage to mid-supply (VDD/2)
for optimum performance.
Analog Input and Reference ConfigurationThe full-scale range of the MAX1449 is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered low-impedance outputs.
T/HVOUTx2Σ
FLASH
ADCDAC
1.5 BITS
MDAC
VIN
VIN
STAGE 1STAGE 2
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
DIGITAL CORRECTION LOGIC
STAGE 10
Figure 1. Pipelined Architecture—Stage Blocks
S3b
S3a
COM
S5bS2b
S5a
IN+
IN-
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
INTERNAL
BIAS
COM
TRACKTRACKCLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLDHOLD
S2a
Figure 2. Internal T/H Circuit
