MAX1402EAI+ ,+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADCfeatures matched♦ 16-Bit Accuracy with No Missing Codes to 480sps200µA current sources for sensor e ..
MAX1402EAI+ ,+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADCMAX140219-1423; Rev 2; 1/07+5V, 18-Bit, Low-Power, Multichannel,Oversampling (Sigma-Delta) ADC
MAX1402EAI+ ,+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADCFeaturesThe MAX1402 low-power, multichannel, serial-output♦ 18-Bit Resolution, Sigma-Delta ADCanalo ..
MAX1403CAI ,+3V / 18-Bit / Low-Power / Multichannel / Oversampling Sigma-Delta ADCfeatures' 16-Bit Accuracy with No Missing Codes to 480spsmatched 200µA current sources for sensor e ..
MAX1403CAI+ ,+3V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADCfeatures♦ 16-Bit Accuracy with No Missing Codes to 480spsmatched 200µA current sources for sensor e ..
MAX1403EAI ,+3V / 18-Bit / Low-Power / Multichannel / Oversampling Sigma-Delta ADCApplicationsCS 3 26 DOUTPortable Industrial InstrumentsRESET 4 25 INTPortable Weigh ScalesDS1 5 24 ..
MAX4020EEE ,Low-Cost / High-Speed / SOT23 / Single-Supply Op Amps with Rail-to-Rail OutputsFeaturesThe MAX4012 single, MAX4016 dual, MAX4018 triple,' Low-Costand MAX4020 quad op amps are uni ..
MAX4020ESD ,Low-Cost / High-Speed / SOT23 / Single-Supply Op Amps with Rail-to-Rail OutputsMAX4012/MAX4016/MAX4018/MAX402019-1246; Rev 0; 7/97Low-Cost, High-Speed, SOT23, Single-SupplyOp Amp ..
MAX4020ESD ,Low-Cost / High-Speed / SOT23 / Single-Supply Op Amps with Rail-to-Rail OutputsFeaturesThe MAX4012 single, MAX4016 dual, MAX4018 triple,' Low-Costand MAX4020 quad op amps are uni ..
MAX4020ESD+T ,Low-Cost, High-Speed, Single-Supply Op Amps with Rail-to-Rail OutputsFeaturesThe MAX4012 single, MAX4016 dual, MAX4018 triple,♦ Low-Costand MAX4020 quad op amps are uni ..
MAX4022EEE ,Low-Cost / High-Speed / Single-Supply / Gain of +2 Buffers with Rail-to-Rail Outputs in SOT23Applications__________Typical Operating CircuitPortable/Battery-Powered InstrumentsVideo Line Drive ..
MAX4023EEE ,Triple and Quad / 2:1 Video Multiplexer- Amplifiers with Fixed and Settable GainELECTRICAL CHARACTERISTICS—Dual Supply(V = +5V, V = -5V, R = ∞, EN = +5V, V = REF = OUT_ = 0V, T = ..
MAX1402CAI+-MAX1402EAI+
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) ADC
General DescriptionThe MAX1402 low-power, multichannel, serial-output
analog-to-digital converter (ADC) features matched
200µA current sources for sensor excitation. This ADC
uses a sigma-delta modulator with a digital decimation
filter to achieve 16-bit accuracy. The digital filter’s user-
selectable decimation factor allows the conversion res-
olution to be reduced in exchange for a higher output
data rate. True 16-bit performance is achieved at an
output data rate of up to 480sps. In addition, the modu-
lator sampling frequency may be optimized for either
lowest power dissipation or highest throughput rate.
The MAX1402 operates from a +5V supply.
This device offers three fully differential input channels
that may be independently programmed with a gain
between +1V/V and +128V/V. Furthermore, it can com-
pensate an input-referred DC offset up to 117% of the
selected full-scale range. These three differential chan-
nels may also be configured to operate as five pseudo-
differential input channels. Two additional, fully
differential system-calibration channels are provided for
gain and offset error correction.
The MAX1402 may be configured to sequentially scan all
signal inputs and provide the results via the serial inter-
face with minimum communications overhead. When
used with a 2.4576MHz or 1.024MHz master clock, the
digital decimation filter can be programmed to produce
zeros in its frequency response at the line frequency and
associated harmonics, ensuring excellent line rejection
without the need for further post-filtering.
The MAX1402 is available in a 28-pin SSOP package.
ApplicationsPortable Industrial Instruments
Portable Weigh Scales
Loop-Powered Systems
Pressure Transducers
Features18-Bit Resolution, Sigma-Delta ADC16-Bit Accuracy with No Missing Codes to 480spsLow Quiescent Current
250µA (operating mode)
2µA (power-down mode)Matched On-Board Current Sources (200µA) for
Sensor Excitation3 Fully Differential or 5 Pseudo-Differential Signal
Input Channels2 Additional, Fully Differential Calibration
Channels/Auxiliary Input ChannelsProgrammable Gain and OffsetFully Differential Reference InputsConverts Continuously or On CommandAutomatic Channel Scanning and Continuous
Data Output ModeOperates with +5V Analog Supply and +3V or +5V
Digital Supply3-Wire Serial Interface—SPI™/QSPI™Compatible28-Pin SSOP Package
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCSCLK
DIN
DOUT
INT
VDD
DGND
AIN5
CALOFF+
CALOFF-
REFIN+
REFIN-
CALGAIN+
CALGAIN-
AIN6
AIN4
AIN3
AIN2
AIN1
AGND
OUT1
OUT2
MUXOUT-
MUXOUT+
RESET
CLKOUT
CLKIN
SSOPTOP VIEW
MAX1402
Pin Configuration
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
19-1423; Rev 2; 1/07
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE
PKG
CODEMAX1402CAI0°C to +70°C28 SSOPA28-2
MAX1402EAI-40°C to +85°C28 SSOPA28-2
%FSR
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(V+ = +5V ±5%, VDD= +2.7V to +5.25V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to AGND, DGND.................................................-0.3V to +6V
VDDto AGND, DGND...............................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
Analog Inputs to AGND................................-0.3V to (V+ + 0.3V)
Analog Outputs to AGND.............................-0.3V to (V+ + 0.3V)
Reference Inputs to AGND...........................-0.3V to (V+ + 0.3V)
CLKIN and CLKOUT to DGND...................-0.3V to (VDD+ 0.3V)
All Other Digital Inputs to DGND..............................-0.3V to +6V
All Digital Outputs to DGND.......................-0.3V to (VDD+ 0.3V)
Maximum Current Input into Any Pin..................................50mA
Continuous Power Dissipation (TA= +70°C)
28-Pin SSOP (derate 9.52mW/°C above +70°C)........524mW
Operating Temperature Ranges
MAX1402CAI.....................................................0°C to +70°C
MAX1402EAI...................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
µV/°C
For gains of 1, 2, 4
No missing codes guaranteed by design;
for filter settings with FS1 = 0
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4, 8, 16, 32, 64
For gain of 128
For gains of 1, 2, 4
For gains of 1, 2, 4, 8, 16, 32, 64
For gains of 8, 16, 32, 64, 128
For gains of 1, 2, 4
Depends on filter setting and selected gain
Bipolar mode, filter settings with FS1 = 0
Relative to nominal of 1% FSR
For gains of 8, 16, 32, 64, 128
CONDITIONS%FSR-2.52.5Bipolar Negative Full-Scale Error
ppm/°C5Gain-Error Drift (Note 5)1
%FSR-33Gain Error (Note 4)-22
%FSR-3.53.5
-2.52.5Positive Full-Scale Error
(Note 2)
0.3Bipolar Zero Drift
Bits16Noise-Free Resolution
%FSR-2.02.0Bipolar Zero Error
µV/°C0.3Unipolar Offset Drift0.5
Table 16Output Noise
%FSR-0.00150.0015INLIntegral Nonlinearity
0.98Nominal Gain (Note 1)
%FSR-12Unipolar Offset Error
UNITSMINTYPMAXSYMBOLPARAMETERFor gains of 8, 16, 32, 64, 128µV/°C0.3Bipolar Negative Full-Scale Drift
For gains of 8, 16, 32, 64, 128
For gains of 1, 2, 4µV/°C0.3
0.8Full-Scale Drift (Note 3)
For gain of 128-3.53.5
STATIC PERFORMANCE
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
ELECTRICAL CHARACTERISTICS (continued)(V+ = +5V ±5%, VDD= +2.7V to +5.25V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C.)
Unipolar mode
CONDITIONSBipolar mode
UNITSMINTYPMAXSYMBOLPARAMETER%FSR
%FSR-58.3558.35Offset DAC Range (Note 6)Offset DAC Zero-Scale Error
Gain = 1, 2, 4, 8, 16, 32, 64
BUFF = 110
Gain = 128
AIN Input Current (Note 10)nA
For filter notch 50Hz, ±0.02 ·fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN= 2.4576MHz (Note 8)
DAC code = 0000
For filter notch 50Hz, ±0.02 ·fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN= 2.4576MHz
150100NMRNormal-Mode 50Hz Rejection
(Note 8)
At DC
µVRMS0Additional Noise from Offset
DAC (Note 7)
REFIN and AIN for BUFF = 0VVAGNDV+Common-Mode Voltage Range
(Note 9)
BUFF = 1
Input referred%FSR-3.53.5Offset DAC Full-Scale ErrorVAGNDV+
+ 200mV- 1.5
Absolute and Common-Mode
AIN Voltage Range40DC Input Leakage Current
(Note 10)
Unipolar mode16.7
Bipolar mode%FSR8.35Offset DAC Resolution
For filter notch 60Hz, ±0.02 ·fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN= 2.4576MHz (Note 8)
CMRCommon-Mode Rejection
For filter notch 60Hz, ±0.02 ·fNOTCH,
MF1 = 0, MF0 = 0, fCLKIN= 2.4576MHzdB100NMRNormal-Mode 60Hz Rejection
(Note 8)
REFIN and AIN for BUFF = 0VVAGNDV+
- 30mV+ 30mVAbsoluteInput Voltage Range
REFIN and AIN for
BUFF = 0= +25°C= TMINto TMAX10nABUFF = 0
BUFF = 1, all gains30
AIN Input Capacitance
(Note 11)pF
Bipolar input range (U/Bbit = 0)±VREF/ gain
AIN Differential Voltage Range
(Note 12)V
Gain = 1
Gain = 2
Gain = 4
Gain =8, 16, 32, 64, 128
Unipolar input range (U/Bbit = 1)0 to VREF/ gain
OFFSET DAC
ANALOG INPUTS/REFERENCE INPUTS (Specifications for AIN and REFIN, unless otherwise noted.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
CONDITIONS(Table 15)fSAIN and REFIN Input Sampling
Frequency
UNITSMINTYPMAXSYMBOLPARAMETERAll inputs except
CLKIN0.4-10+10IINInput Current
CLKIN only
All inputs except
CLKINmV200VHYSInput HysteresisVOLOutput Low Voltage (Note 14)9
DOUT
and INTFloating-State Output
Capacitance -1010ILFloating-State Leakage Current
VILInput Low Voltage
±5% for specified performance; functional
with lower VREFV2.50REFIN+ - REFIN- Voltage
(Note 13)
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
VDD= 5V
VDD= 3.3V
All inputs except
CLKIN2
CLKIN only
VIHInput High Voltage
VDD= 5V
VDD= 3.3V0.1IBOCurrent±10Initial Tolerance
%/°C±0.05Drift
VDD= 5V, ISINK= 800µA
VDD= 3.3V, ISINK= 100µA
VDD= 5V, ISINK= 10µA
VDD= 3.3V, ISINK= 10µACLKOUT0.4
VDD= 5V, ISOURCE= 200µA
VDD= 3.3V, ISOURCE= 100µAVVOHOutput High Voltage (Note 14)
DOUT
and INT
VDD- 0.3200IEXCCurrent15Initial Tolerance
ppm/°C100Drift
OUT1 to OUT2%±1Match
ppm/°C5Drift MatchVAGNDV+-1.0Compliance Voltage Range
ELECTRICAL CHARACTERISTICS (continued)(V+ = +5V ±5%, VDD= +2.7V to +5.25V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C.)
VDD= 5V, ISOURCE= 10µA
VDD= 3.3V, ISOURCE= 10µACLKOUT4
VDD- 0.3
TRANSDUCER BURN-OUT(Note 15)
LOGIC OUTPUTS
LOGIC INPUTS
TRANSDUCER EXCITATION CURRENTS
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC2.4576MHz
1.024MHzBuffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
Normal mode,
MF1 = 0,
MF0 = 0
Buffers on610
Buffers on
2X mode,
MF1 = 0,
MF0 = 1
CONDITIONS
PD bit = 1, external clock stopped
2.4576MHz
1.024MHzBuffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
4X mode,
MF1 = 1,
MF0 = 0
Buffers on4.8
Buffers on
8X mode,
MF1 = 1,
MF0 = 1
IV+V+ Current
V+ Standby Current (Note 18)
2X mode,
MF1 = 0, MF0 = 10.170.35
Normal mode,
MF1 = 0, MF0 = 0
PD bit = 1, external clock stopped110
150300VDDStandby Current (Note 18)
2X mode,
MF1 = 0, MF0 = 1
1.024MHz
2.4576MHz
Normal mode,
MF1 = 0, MF0 = 0
1.024MHz
2.4576MHz
8X mode,
MF1 = 1, MF0 = 10.320.454X mode,
MF1 = 1, MF0 = 00.220.40
235450µA1.024MHz
1.024MHz
2.4576MHz
IDD3.3V Digital Supply Current
1.024MHz
2.4576MHz
2.4576MHz
1.024MHz
2.4576MHzmA
IDD5V Digital Supply Current
UNITSMINTYPMAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)(V+ = +5V ±5%, VDD= +2.7V to +5.25V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C.)
For specified performanceV4.755.25V+V+Voltage2.75.25VDDVDDVoltage(Note 17)PSRPower-Supply Rejection V+
(Note 16)
ANALOG POWER-SUPPLY CURRENT(Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxil-
iary currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
DIGITAL POWER-SUPPLY CURRENT(Measured with digital inputs at either DGND or VDD, external CLKIN, burn-out and auxiliary
currents disabled, X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
POWER REQUIREMENTS
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Note 1:Nominal gain is 0.98. This ensures a full-scale input voltage may be applied to the part under all conditions without caus-
ing saturation of the digital output data.
Note 2:Positive Full-Scale Error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges. This error does not include the nominal gain of 0.98.
Note 3:Full-Scale Drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar
input ranges.
Note 4:Gain Error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges
and as (full-scale error - bipolar zero error) for bipolar ranges. This error does not include the nominal gain of 0.98.
Note 5:Gain-Error Drift does not include unipolar offset drift or bipolar zero drift. It is effectively the drift of the part if zero-scale
error is removed.
Note 6:Use of the offset DAC does not imply that any input may be taken below AGND.
Note 7:Additional noise added by the offset DAC is dependent on the filter cutoff, gain, and DAC setting. No noise is added for a
DAC code of 0000.
Note 8:Guaranteed by design or characterization; not production tested.
Note 9:The absolute input voltage must be within the input-voltage range specification.
Note 10:All AIN and REFIN pins have identical input structures. Leakage is production tested only for the AIN3, AIN4, AIN5,
CALGAIN and CALOFF inputs.
Note 11:The dynamic load presented by the MAX1402 analog inputs for each gain setting is discussed in detail in the Switching
Network Section.Values are provided for the maximum allowable external series resistance.
2.4576MHz
1.024MHzBuffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
Normal mode,
MF1 = 0,
MF0 = 0
Buffers on3.7
Buffers on
2X mode,
MF1 = 0,
MF0 = 1
CONDITIONS
2.4576MHz
1.024MHzBuffers off
Buffers off
Buffers on
2.4576MHz
1.024MHz
Buffers off
Buffers off
Buffers on
4X mode,
MF1 = 1,
MF0 = 0
Buffers on25.2
Buffers on
8X mode,
MF1 = 1,
MF0 = 1
26.734Power Dissipation
(Note 18)10100µWStandby Power Dissipation
UNITSMINTYPMAXSYMBOLPARAMETER
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±5%, VDD= +2.7V to +5.25V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C.)
4X mode,
MF1 = 1, MF0 = 0
IDD5VDigital Supply Current
1.024MHz
2.4576MHz0.360.6
8X mode,
MF1 = 1, MF0 = 1
0.241.024MHz
2.4576MHz0.530.8
5V POWER DISSIPATION(V+ = VDD= +5V, digital inputs = 0 or VDD, external CLKIN, burn-out and auxiliary currents disabled,
X2CLK = 0, CLK = 0 for 1.024MHz, CLK = 1 for 2.4576MHz.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
TIMING CHARACTERISTICS(V+ = +5V ±5%, VDD= +2.7V to +5.25V, AGND = DGND, fCLKIN= 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA= TMINto TMAX,
unless otherwise noted.) (Notes 19, 20, 21)100VDD= 3.3V
VDD= 5V
Bus Relinquish Time After SCLK
Rising Edge (Note 26)t1010100nsVDD= 5V
SCLK Falling Edge to Data Valid
Delay (Notes 24, 25)t6080ns
INTHigh Time tINT560 / N
tCLKIN
X2CLK = 1, N = 2(2 · MF1 + MF0)
Crystal oscillator or clock exter-
nally supplied for specified perfor-
mance (Notes 22, 23)
SCLK Setup to Falling Edge CSt430ns
SCLK Low Pulse Widtht8100ns70
SCLK Rising Edge to INTHigh
(Note 27)t11
100VDD= 5VRising Edge to SCLK Rising
Edge Hold Time (Note 21)t90ns
SCLK High Pulse Widtht7100nsFalling Edge to SCLK Falling
Edge Setup Timet530ns
280 / N
· tCLKININTto CSSetup Time (Note 8)t3
X2CLK = 0, N = 2(2 · MF1 + MF0)ns
RESETPulse Width Lowt2100ns
Master Clock Input Low TimefCLKIN LO0.4 ·
tCLKINnstCLKIN= 1 / fCLKIN, X2CLK = 0
Master Clock Input High TimefCLKIN HI0.4 ·
tCLKINnstCLKIN= 1 / fCLKIN, X2CLK = 0
Master Clock FrequencyfCLKIN
MHz
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
200ns
X2CLK = 0
X2CLK = 1
VDD= 3.3V
VDD= 3.3V
Note 12:The input voltage range for the analog inputs is with respect to the voltage on the negative input of its respective differen-
tial or pseudo-differential pair. Table 5 shows which inputs form differential pairs.
Note 13:VREF= VREFIN+- VREFIN-.
Note 14:These specifications apply to CLKOUT only when driving a single CMOS load.
Note 15:The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate cor-
rectly.
Note 16:Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
Note 17:PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
Note 18:Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.nst12SCLK Setup to Falling Edge CS
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Note 19:All input signals are specified with tr= tf= 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 20:See Figure 4.
Note 21:Timings shown in tables are for the case where SCLK idles high between accesses. The part may also be used with the
SCLK idling low between accesses, provided CSis toggled. In this case SCLK in the timing diagrams should be inverted
and the terms “SCLK Falling Edge” and “SCLK Rising Edge” exchanged in the specification tables. If CSis permanently
tied low, the part should only be operated with SCLK idling high between accesses.
Note 22:CLKIN duty cycle range is 45% to 55%. CLKIN must be supplied whenever the MAX1402 is not in standby mode. If no
clock is present, the device can draw higher current than specified.
Note 23:The MAX1402 is production tested with fCLKINat 2.5MHz (1MHz for some IDDtests).
Note 24:Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOLor VOHlimits.
Note 25:For read operations, SCLK active edge is falling edge of SCLK.
Note 26:Derived from the time taken by the data output to change 0.5V when loaded with the circuit of Figure 1. The number is then
extrapolated back to remove effects of charging or discharging the 50pF capacitor. This ensures that the times quoted in
the timing characteristics are true bus-relinquish times and are independent of external bus loading capacitances.
Note 27:INTreturns high after the first read after an output update. The same data can be read again while INTis high, but be
careful not to allow subsequent reads to occur close to the next output update.
Note 28:Auxiliary inputs DS0 and DS1 are latched on the first falling edge of SCLK during a data-read cycle.
SCLK High Pulse Widtht16100ns
SCLK Low Pulse Widtht17100ns
Data Valid to SCLK Rising Edge
Hold Timet150ns
PARAMETERSYMBOLMINTYPMAXUNITSFalling Edge to SCLK Falling
Edge Setup Timet1330ns
Data Valid to SCLK Rising Edge
Setup Timet1430ns
CONDITIONS
TIMING CHARACTERISTICS (continued)(V+ = +5V ±5%, VDD= +2.7V to +5.25V, AGND = DGND, fCLKIN= 2.4576MHz; input logic 0 = 0V; logic 1 = VDD, TA= TMINto TMAX,
unless otherwise noted.) (Notes 19, 20, 21)Rising Edge to SCLK Rising
Edge Hold Timet180ns
DS0/DS1 to SCLKFalling Edge
Hold Time (Notes 21 & 28)t200ns
DS0/DS1 to SCLKFalling Edge
Setup Time (Notes 21 & 28)t1940ns
800μA
at VDD = +5V
100μA
at VDD = +3.3V
OUTPUT
PIN
50pF200μA
at VDD = +5V
100μA
at VDD = +3.3V
Figure 1. Load Circuit for Bus-Relinquish Time and VOLand
AUXILIARY DIGITAL INPUTS (DS0 and DS1)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCOUT1 AND OUT2 COMPLIANCE
MAX1402 toc01
COMPLIANCE VOLTAGE (V)
OUTPUT CURRENT (
INTEGRAL NONLINEARITY AT 480sps,
GAIN = 1 (262, 144 pts)
MAX1402 toc12
DIFFERENTIAL INPUT VOLTAGE (V)
INL (ppm)
MAX1402 toc13
CODE (x105)
DNL (ppm)
DIFFERENTIAL NONLINEARITY AT 480sps,
GAIN = 1 (262, 144 pts)VDD SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
V+ SUPPLY CURRENT vs. TEMPERATURE
(20sps OUTPUT DATA RATE)
MAX1402 toc07
TEMPERATURE (°C)
V+ SUPPLY CURRENT (BUFFERED
UNBUFFERED
VDD SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
VDD SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (VDD = +5.25V
VDD = +3.6V
(NOTE 29)
V+ SUPPLY CURRENT vs. TEMPERATURE
(60sps OUTPUT DATA RATE)
MAX1402 toc08
TEMPERATURE (°C)
V+ SUPPLY CURRENT (BUFFERED
UNBUFFERED
V+ SUPPLY CURRENT vs. TEMPERATURE
(120sps OUTPUT DATA RATE)
MAX1402 toc09
TEMPERATURE (°C)
V+ SUPPLY CURRENT (BUFFERED
UNBUFFERED
Typical Operating Characteristics(V+ = +5V, VDD= +5V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= +25°C, unless otherwise noted.)
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCVDD SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc05
TEMPERATURE (°C)
SUPPLY CURRENT (
VDD = +5.25V
VDD = +3.6V
(NOTE 29)0
VDD SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (
VDD = +5.25V
VDD = +3.6V
(NOTE 29)
V+ SUPPLY CURRENT vs. TEMPERATURE
(240sps OUTPUT DATA RATE)
MAX1402 toc10
TEMPERATURE (°C)
V+ SUPPLY CURRENT (BUFFERED
UNBUFFERED
V+ SUPPLY CURRENT vs. TEMPERATURE
(480sps OUTPUT DATA RATE)
MAX1402 toc11
TEMPERATURE (°C)
V+ SUPPLY CURRENT (BUFFERED
UNBUFFERED
Typical Operating Characteristics (continued)(V+ = +5V, VDD= +5V, VREFIN+= +2.50V, REFIN- = AGND, fCLKIN= 2.4576MHz, TA= +25°C, unless otherwise noted.)
Note 29:Minimize capacitive loading at CLKOUT for lowest VDDsupply current. Typical Operating Characteristicsshow VDD
supply current with CLKOUT loaded by 120pF.
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Pin DescriptionAIN5Analog Input Channel 5. Used as a differential or pseudo-differential input with AIN6
(see Communications Registersection).
NAMEFUNCTIONCLKIN
Clock Input. A crystal can be connected across CLKIN and CLKOUT. Alternatively, drive CLKIN with a
CMOS-compatible clock at a nominal frequency of 2.4576MHz or 1.024MHz, and leave CLKOUT uncon-
nected. Frequencies of 4.9152MHz and 2.048MHz may be used if the X2CLK control bit is set to 1.
PINCLKOUT
Clock Output. When deriving the master clock from a crystal, connect the crystal between CLKIN and
CLKOUT. In this mode, the on-chip clock signal is not available at CLKOUT. Leave CLKOUT unconnected
when CLKIN is driven with an external clock.CS
Chip-Select Input. Active-low logic input used to enable the digital interface. With CShard-wired low, the
MAX1402 operates in its 3-wire interface mode with SCLK, DIN and DOUT used to interface to the device.is used either to select the device in systems with more than one device on the serial bus, or as a
frame-synchronization signal for the MAX1402 when a continuous SCLK is used.RESETActive-Low Reset Input. Drive low to reset the control logic, interface logic, digital filter and analog modu-
lator to power-on status. RESETmust be high and CLKIN must be toggling in order to exit reset. DS1Digital Input for Auxiliary Data Input Bit 1. The status of this bit is reflected in the output data by bit D4.
Used to communicate the status of DS1 via the serial interface.DS0Digital Input for Auxiliary Data Input Bit 0. The status of this bit is reflected in the output data by bit D3.
Used to communicate the status of DS0 via the serial interface.OUT2Transducer Excitation Current Source 2OUT1Transducer Excitation Current Source 1AGNDAnalog Ground. Reference point for the analog circuitry. AGND connects to the IC substrate.V+Analog Positive Supply Voltage (+4.75V to +5.25V).AIN1Analog Input Channel 1. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN1/AIN2 differential analog input pair (see Communications Registersection).AIN2Analog Input Channel 2. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN1/AIN2 differential analog input pair (see Communications Registersection).AIN3Analog Input Channel 3. May be used as a pseudo-differential input with AIN6 as common, or as the posi-
tive input of the AIN3/AIN4 differential analog input pair (see Communications Registersection).AIN4Analog Input Channel 4. May be used as a pseudo-differential input with AIN6 as common, or as the neg-
ative input of the AIN3/AIN4 differential analog input pair (see Communications Registersection).AIN6Analog Input 6. May be used as a common point for AIN1 through AIN5 in pseudo-differential mode, or as
the negative input of the AIN5/AIN6 differential analog input pair (see Communications Registersection).
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Pin Description (continued)
NAMEFUNCTIONPINCALGAIN-
Negative Gain Calibration Input. Used for system-gain calibration. It forms the negative input of a fully
differential input pair with CALGAIN+. Normally these inputs are connected to reference voltages in the
system. When system gain calibration is not required and the auto-sequence mode is used, the
CALGAIN+/CALGAIN- input pair provides an additional fully differential input channel.CALGAIN+
Positive Gain Calibration Input. Used for system gain calibration. It forms the positive input of a fully differ-
ential input pair with CALGAIN-. Normally these inputs are connected to reference voltages in the system.
When system gain calibration is not required and the auto-sequence mode is used, the CALGAIN+/
CALGAIN- input pair provides an additional fully differential input channel.REFIN-Negative Differential Reference Input. Bias REFIN- between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.REFIN+Positive Differential Reference Input. Bias REFIN+ between V+ and AGND, provided that REFIN+ is more
positive than REFIN-.CALOFF-
Negative Offset Calibration Input. Used for system offset calibration. It forms the negative input of a fully
differential input pair with CALOFF+. Normally these inputs are connected to zero-reference voltages in
the system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.CALOFF+
Positive Offset Calibration Input. Used for system offset calibration. It forms the positive input of a fully
differential input pair with CALOFF-. Normally these inputs are connected to zero-reference voltages in the
system. When system offset calibration is not required and the auto-sequence mode is used, the
CALOFF+/CALOFF- input pair provides an additional fully differential input channel.DGNDDigital Ground. Reference point for digital circuitry.VDDDigital Supply Voltage (+2.7V to +5.25V)INT
Interrupt Output. A logic low indicates that a new output word is available from the data register. INT
returns high upon completion of a full output word read operation. INTalso returns high for short periods
(determined by the filter and clock control bits) if no data read has taken place. A logic high indicates
internal activity, and a read operation should not be attempted under this condition. INTcan also provide
a strobe to indicate valid data at DOUT (MDOUT = 1).DOUT
Serial Data Output. DOUT outputs data from the internal shift register containing information from the
Communications Register, Global Setup Registers, Transfer Function Registers, or Data Register. DOUT
can also provide the digital bit stream directly from the Σ-∆modulator (MDOUT = 1).DIN
Serial Data Input. Data on DIN is written to the input shift register and later transferred to the
Communications Register, Global Setup Registers, Special Function Register, or Transfer Function
Registers, depending on the register selection bits in the Communications Register.SCLK
Serial Clock Input. Apply an external serial clock to transfer data to and from the MAX1402. This serial
clock can be continuous, with data transmitted in a train of pulses, or intermittent. If CSis used to frame
the data transfer, then SCLK may idle high or low between conversions and CSdetermines the desired
active clock edge (see Selecting Clock Polarity). If CSis tied permanently low, SCLK must idle high
between data transfers.
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
_______________Detailed Description
Circuit DescriptionThe MAX1402 is a low-power, multichannel, serial-output,
sigma-delta ADC designed for applications with a wide
dynamic range, such as weigh scales and pressure
transducers. The functional block diagram in Figure 2
contains a switching network, a modulator, a PGA, two
buffers, an oscillator, an on-chip digital filter, and a
bidirectional serial communications port.
Three fully-differential input channels feed into the
switching network. Each channel may be independent-
ly programmed with a gain between +1V/V and
+128V/V. These three differential channels may also be
configured to operate as five pseudo-differential input
channels. Two additional, fully differential system-cali-
bration channels allow system gain and offset error to
be measured. These system-calibration channels can
be used as additional differential signal channels when
dedicated gain and offset error correction channels are
not required.
Two chopper-stabilized buffers are available to isolate
the selected inputs from the capacitive loading of the
PGA and modulator. Three independent DACs provide
compensation for the DC component of the input signal
on each of the differential input channels.
The sigma-delta modulator converts the input signal into
a digital pulse train whose average duty cycle represents
the digitized signal information. The pulse train is then
processed by a digital decimation filter, resulting in a
conversion accuracy exceeding 16 bits. The digital filter’s
decimation factor is user-selectable, which allows the
conversion result’s resolution to be reduced to achieve a
higher output data rate. When used with 2.4576MHz or
1.024MHz master clocks, the decimation filter can be
programmed to produce zeros in its frequency response
at the line frequency and associated harmonics. This
ensures excellent line rejection without the need for fur-
ther post-filtering. In addition, the modulator sampling
frequency can be optimized for either lowest power dis-
sipation or highest output data rate.
AGND
DGND
VDD
CALOFF+
OUT2
OUT1
CALGAIN+
CALOFF-
CALGAIN-
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
SWITCHING
NETWORKMODULATOR
DAC
PGAV+
BUFFER
BUFFER
AGND
DIGITAL
FILTER
SCLK
DIN
DOUT
INT
DS0
DS1
RESET
CLKIN
CLKOUT
REFIN+
REFIN-
DIVIDER
MAX1402
INTERFACE
AND CONTROL
CLOCK
GEN
Figure 2. Functional Diagram
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCThe MAX1402 can be configured to sequentially scan
all signal inputs and to transmit the results through the
serial interface with minimum communications over-
head. The output word contains a result identification
tag to indicate the source of each conversion result.
Serial Digital InterfaceThe serial digital interface provides access to eight on-
chip registers (Figure 3). All serial-interface commands
begin with a write to the communications register
(COMM). On power-up, system reset, or interface reset,
the part expects a write to its communications register.
The COMM register access begins with a 0 start bit.
The COMM register R/Wbit selects a read or write
operation, and the register select bits (RS2, RS1, RS0)
select the register to be addressed. Hold DIN high
when not writing to COMM or another register (Table 1).
The serial interface consists of five signals: CS, SCLK,
DIN, DOUT, and INT. Clock pulses on SCLK shift bits
into DIN and out of DOUT. INTprovides an indication
that data is available. CSis a device chip-select input
as well as a clock polarity select input (Figure 4). Usingallows the SCLK, DIN, and DOUT signals to be
shared among several SPI-compatible devices. When
short on I/O pins, connect CSlow and operate the seri-
al digital interface in CPOL = 1, CPHA = 1 mode using
SCLK, DIN, and DOUT. This 3-wire interface mode is
ideal for opto-isolated applications. Furthermore, a
microcontroller (such as a PIC16C54 or 80C51) can
use a single bidirectional I/O pin for both sending to
DIN and receiving from DOUT (see Applications
Information), because the MAX1402 drives DOUT only
during a read cycle.
Additionally, connecting the INTsignal to a hardware
interrupt allows faster throughput and reliable, collision-
free data flow.
The MAX1402 features a mode where the raw modula-
tor data output is accessible. In this mode the DOUT
and INTfunctions are reassigned (see the Modulator
Data Outputsection).
DATA REGISTER D1–D0/CID
RS0
GLOBAL SETUP REGISTER 1
GLOBAL SETUP REGISTER 2
SPECIAL FUNCTION REGISTER
XFER FUNCTION REGISTER 1
XFER FUNCTION REGISTER 2
XFER FUNCTION REGISTER 3
DATA REGISTER D17–D10
DATA REGISTER D9–D2
COMMUNICATIONS REGISTER
RS1RS2DIN
DOUT
REGISTER
SELECT
DECODER
Figure 3. Register Summary
DIN
(DURING
WRITE)*
DOUT
(DURING
READ)*
DS1, DS0
MSBD6D5D4D3D2D1D0
MSBD6D5D4D3D2D1D0
INT
t10t6
t20t19
t17
t16
t13
t12
t18
t11
t15
t14
SCLK
(CPOL = 1)
SCLK
(CPOL = 0)
*DOUT IS HIGH IMPEDANCE DURING THE WRITE CYCLE; DIN IS IGNORED
DURING THE READ CYCLE.
Figure 4. Serial-Interface Timing
Table 1. Control Register Addressing
RS1
RS01Global Setup Register 1001Special Function Register0
Global Setup Register 2
Communications Register01Transfer Function Register 2101Data Register1
Transfer Function Register 3
Transfer Function Register 1
RS2TARGET REGISTER
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Selecting Clock PolarityThe serial interface can be operated with the clock idling
either high or low. This is compatible with Motorola’s SPI
interface operated in CPOL = 1, CPHA = 1 or CPOL = 0,
CPHA = 1 mode. Select the clock polarity by sampling
the state of SCLK at the falling edge of CS. Ensure that
the setup times t4/t12and t5/t13are not violated. If CSis
connected to ground, resulting in no falling edge on CS,
SCLK must idle high (CPOL = 1, CPHA = 1).
Data-Ready Signal (DRDY bit true or IINNTT
= low)The data-ready signal indicates that new data may be
read from the 24-bit data register. After the end of a suc-
cessful data register read, the data-ready signal
becomes false. If a new measurement completes before
the data is read, the data-ready signal becomes false.
The data-ready signal becomes true again when new
data is available in the data register.
The MAX1402 provides two methods of monitoring the
data-ready signal. INTprovides a hardware solution
(active low when data is ready to be accessed), while
the DRDY bit in the COMM register provides a software
solution (active high).
Read data as soon as possible once data-ready
becomes true. This becomes increasingly important for
faster measurement rates. If the data-read is delayed
significantly, a collision may result. A collision occurs
when a new measurement completes during a data-
register read operation. After a collision, information in
the data register is invalid. The failed read operation
must be completed even though the data is invalid.
Resetting the InterfaceReset the serial interface by clocking in 32 1s.
Resetting the interface does not affect the internal reg-
isters.
If continuous data output mode is in use, clock in eight
0s followed by 32 1s. More than 32 1s may be clocked
in, since a leading 0 is used as the start bit for all oper-
ations.
Continuous Data Output ModeWhen scanning the input channels (SCAN = 1), the ser-
ial interface allows the data register to be read repeat-
edly without requiring a write to the COMM register.
The initial COMM write (01111000) is followed by 24
clocks (DIN = high) to read the 24-bit data register.
Once the data register has been read, it can be read
again after the next conversion by writing another 24
clocks (DIN = high). Terminate the continuous data out-
put mode by writing to the COMM register with any
valid access.
Modulator Data Output (MDOUT = 1)Single-bit, raw modulator data is available at DOUT for
custom filtering when MDOUT = 1. INTprovides a mod-
ulator clock for data synchronization. Data is valid on
the falling edge of INT. Write operations can still be
performed, however, read operations are disabled.
After MDOUT is returned to 0, valid data is accessed
by the normal serial-interface read operation.
On-Chip Registers
Communications Register
0/DRDY: (Default = 0) Data Ready Bit. On a write, this
bit must be reset to 0 to signal the start of the Com-
munications Register data word. On a read, a 1 in this
location (0/DRDY) signifies that valid data is available in
the data register. This bit is reset after the data register
is read or, if data is not read, 0/DRDY will go low at the
end of the next measurement.
RS2, RS1, RS0:(Default = 0, 0, 0) Register Select
Bits. These bits select the register to be accessed
(Table 1).
R/W:(Default = 0) Read/Write Bit. When set high, the
selected register is read; when R/W= 0, the selected
register is written.
RESET:(Default = 0) Software Reset Bit. Setting this
bit high causes the part to be reset to its default power-
up condition (RESET = 0).
STDBY:(Default = 0) Standby Power-Down Bit. Setting
the STDBY bit places the part in “standby” condition,
shutting down everything except the serial interface
and the CLK oscillator.
FSYNC:(Default = 0) Filter Sync Bit. When FSYNC = 0,
conversions are automatically performed at a data rate
determined by CLK, FS1, FS0, MF1, and MF0 bits.
When FSYNC = 1, the digital filter and analog modulator
First Bit (MSB)(LSB)
FUNCTIONSTDBY
RESET
NameFSYNC
REGISTER SELECT BITSRS0
RS1
DATA
RDYDefaults
RS20
R/W0/DRDY
Communications Register
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCare held in reset, inhibiting normal self-timed operation.
This bit may be used to convert on command to mini-
mize the settling time to valid output data, or to synchro-
nize operation of a number of MAX1402s. FSYNC does
not reset the serial interface or the 0/DRDY flag. To clear
the 0/DRDY flag while FSYNC is active, simply read the
data register.
Global Setup Register 1
A1, A0:(Default = 0, 0) Channel-Selection Control Bits.
These bits (combined with the state of the DIFF, M1,
and M0 bits) determine the channel selected for con-
version according to Tables 8, 9, and 10. These bits
are ignored if the SCAN bit is set.
MF1, MF0: (Default = 0, 0) Modulator Frequency Bits.
MF1 and MF0 determine the ratio of CLKIN oscillator fre-
quency to modulator operating frequency. They affect
the output data rate, the position of the digital filter notch
frequencies, and the power dissipation of the device.
Achieve lowest power dissipation with MF1 = 0 and MF0
= 0. Highest power dissipation and fastest output data
rate occur with these bits set to 1, 1 (Table 2).
CLK:(Default = 1) CLK Bit. The CLK bit is used in con-
junction with X2CLK to tell the MAX1402 the frequency
of the CLKIN input signal. If CLK = 0, a CLKIN input fre-
quency of 1.024MHz (2.048MHz for X2CLK = 1) is
expected. If CLK = 1, a CLKIN input frequency of
2.4576MHz (4.1952MHz for X2CLK = 1) is expected.
This bit affects the decimation factor in the digital filter
and thus the output data rate (Table 2).
FS1, FS0:(Default = 0, 1) Filter Selection Bits. These
bits (in conjunction with the CLK bit) control the deci-
mation ratio of the digital filter. They determine the out-
put data rate, the position of the digital filter-frequency
response notches, and the noise present in the output
result. (Table 2).
FAST:(Default 0) FAST Bit. FAST = 0 causes the digi-
tal filter to perform a SINC3filter function on the modu-
lator data stream. The output data rate will be deter-
mined by the values in the CLK, FS1, FS0, MF1, and
MF0 bits (Table 2). The settling time for SINC3 function
is 3 ·[1 / (output data rate)]. In SINC3mode, the
MAX1402 automatically holds the DRDY signal false
(after any significant configuration change) until settled
data is available. FAST = 1 causes the digital filter to
perform a SINC1filter function on the modulator data
stream. The signal-to-noise ratio achieved with this filter
function is less than that of the SINC3filter; however
SINC1settles in a single output sample period, rather
than a minimum of three output sample periods for
SINC3. When switching from SINC1to SINC3mode, the
DRDY flag will be deasserted and reasserted after the
filter has fully settled. This mode change requires a
minimum of three samples.
Global Setup Register 2
SCAN:(Default = 0) Scan Bit. Setting this bit to a 1
causes sequential scanning of the input channels as
determined by DIFF, M1, and M0 (see Scanning(Scan-
Mode)). When SCAN = 0, the MAX1402 repeatedly
measures the unique channel selected by A1, A0,
DIFF, M1, and M0 (Table 4).
M1, M0:(Default 0, 0) Mode Control Bits. These bits
control access to the calibration channels CALOFF and
CALGAIN. When SCAN = 0, setting M1 = 0 and M0 = 1
selects the CALOFF input, and M1 = 1 and M0 = 0
selects the CALGAIN input (Table 3). When SCAN = 1
and M1 ≠M0, the scanning sequence includes both
CALOFF and CALGAIN inputs (Table 4). When SCAN is
set to 1 and the device is scanning the available input
channels, selection of either calibration mode (01 or 10)
will cause the scanning sequence to be extended to
include a conversion on both the CALGAIN+
/CALGAIN- input pair and the CALOFF+/CALOFF- input
First Bit (MSB)(LSB)
First Bit (MSB)(LSB)CLK1
Defaults
CHANNEL SELECTIONMF1
MF0
MODULATOR
FREQUENCYFASTName
FS1
FS0
FILTER SELECTION
FUNCTIONSCANDIFF0
Defaults0
BUFF
MODE CONTROLX2CLKName
BOUT
IOUT
FUNCTION
Global Setup Register 2
Global Setup Register 1
CLK
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADCpair. The exact sequence depends on the state of the
DIFF bit (Table 4). When scanning, the calibration
channels use the PGA gain, format, and DAC settings
defined by the contents of Transfer Function Register 3.
BUFF:(Default = 0) The BUFF bit controls operation of
the input buffer amplifiers. When this bit is 0, the inter-
nal buffers are bypassed and powered down. When
this bit is set high, the buffers drive the input sampling
capacitors and minimize the dynamic input load.
DIFF:(Default = 0) Differential/Pseudo-Differential Bit.
When DIFF = 0, the part is in pseudo-differential mode,
and AIN1–AIN5 are measured respective to AIN6, the
analog common. When DIFF = 1, the part is in differen-
tial mode with the analog inputs defined as AIN1/AIN2,
AIN3/AIN4, and AIN5/AIN6. The available input chan-
nels for each mode are tabulated in Table 5. Note that
DIFF also affects the scanning sequence when the part
is placed in SCAN mode (Table 4).
BOUT:(Default = 0) Burn-out Current Bit. Setting BOUT
= 1 connects 100nA current sources to the selected ana-
log input channel. This mode is used to check that a
transducer has not burned out or opened circuit. The
burn-out current source must be turned off (BOUT = 0)
before measurement to ensure best linearity.
IOUT: (Default = 0) The IOUT bit controls the
Transducer Excitation Currents. A ‘0’ in this bit disables
OUT1 and OUT2 effectively making these pins high-
impedance. A ‘1’ in this location activates both IOUT1
and IOUT2 causing each pin to source 200µA.
X2CLK:(Default = 0) Times-Two Clock Bit. Setting this
bit to 1 selects a divide-by-2 prescaler in the clock sig-
nal path. This allows use of a higher frequency crystal
or clock source and improves immunity to asymmetric
clock sources.
Table 2. Data Output Rate vs. CLK, Filter Select, and Modulator Frequency Bits* Data rates offering noise-free 16-bit resolution.
Note: When FAST = 0, f-3dB = 0.262 ·Data Rate. When FAST = 1, f-3dB = 0.443 ·Data Rate.
Default condition is in bold print.
Table 3. Special Modes Controlled by M1, M0 (SCAN = 0)
DESCRIPTIONM1
Normal Mode:The device operates normally.
Calibrate Gain:In this mode the MAX1402 converts the voltage applied across CALGAIN+
and CALGAIN-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
Reserved:Do not use.1
Calibrate Offset:In this mode the MAX1402 converts the voltage applied across CALOFF+
and CALOFF-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
30060050
60014.9152
02.4576CLKMF1X2CLK = 0
fCLKIN
(MHz)
MF000
CLKIN
FREQ.
X2CLK = 1
fCLKIN
(MHz)CLKIN
FREQ.
FS1, FS0
(0, 0)
(sps)*
FS1, FS0
(0, 1)
(sps)*
FS1, FS0
(1, 0)
(sps)
FS1, FS0
(1, 1)
(sps)
AVAILABLE OUTPUT DATA RATES
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Special Function Register (Write-Only)
MDOUT:(Default = 0) Modulator Out Bit. MDOUT = 0
enables data readout on the DOUT pin, the normal con-
dition for the serial interface. MDOUT = 1 changes the
function of the DOUT and INTpins, providing raw, sin-
gle-bit modulator output instead of the normal serial-
data interface output. This allows custom filtering
directly on the modulator output, without going through
the on-chip digital filter. The INTpin provides a clock to
indicate when the modulator data at DOUT should be
sampled (falling edge of INT). Note that in this mode,
the on-chip digital filter continues to operate normally.
When MDOUT is returned to 0, valid data may be
accessed through the normal serial-interface read
operation.
FULLPD:(Default = 0) Complete Power-Down Bit.
FULLPD = 1 forces the part into a complete power-down
condition, which includes the clock oscillator. The serial
interface continues to operate. The part requires a hard-
ware reset to recover correctly from this condition.
Note:Changing the reserved bits in the special-func-
tion register from the default status of all 0s will select
one of the reserved modes and the part will not operate
as expected. This register is a write-only register.
However, in the event that this register is mistakenly
read, clock 24 bits of data out of the part to restore it to
the normal interface-idle state.
Transfer-Function RegistersThe three transfer-function registers control the method
used to map the input voltage to the output codes. All
of the registers have the same format. The mapping of
control registers to associated channels depends on
the mode of operation and is affected by the state of
M1, M0, DIFF, and SCAN (Tables 8, 9, and 10).
Table 4. SCAN Mode Scanning
Sequences (SCAN = 1)
Table 5. Available Input Channels
(SCAN = 0)
Note:All other combinations reserved.
Special Function Register (Write-Only)
Transfer-Function Register D30Defaults
PGA GAIN CONTROLName
OFFSET CORRECTION0G00
U/B
FUNCTION1
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN00AIN1–AIN2, AIN3–AIN4, AIN5–AIN61
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN6, CALOFF,
CALGAIN
AIN1–AIN6, AIN2–AIN6, AIN3–AIN6,
AIN4–AIN6, AIN5–AIN610AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN1
AIN1–AIN2, AIN3–AIN4, AIN5–AIN6,
CALOFF, CALGAIN1
DIFFSEQUENCE
First Bit (MSB)(LSB)00
Defaults
RESERVED BITSMDOUT
FULLPDName
RESERVED BITS
FUNCTION
First Bit (MSB)(LSB)1CALOFF000AIN1–AIN2, AIN3–AIN4, AIN5–AIN61
CALGAIN
AIN1–AIN6, AIN2–AIN6,
AIN3–AIN6, AIN4–AIN610CALGAIN1
CALOFF1
DIFFAVAILABLE CHANNELS
MAX1402
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
Analog Inputs AIN1 to AIN6Inputs AIN1 and AIN2 map to transfer-function register
1, regardless of scanning mode (SCAN = 1) or single-
ended vs. differential (DIFF) modes. Likewise, AIN3 and
AIN4 inputs always map to transfer-function register 2.
Finally, AIN5 always maps to transfer-function register 3
(input AIN6 is analog common).
CALGAIN and CALOFFWhen not in scan mode (SCAN = 0), A1 and A0 select
which transfer function applies to CALGAIN and
CALOFF. In scan mode (SCAN = 1), CALGAIN and
CALOFF are always mapped to transfer-function regis-
ter 3. Note that when scanning while M1 ≠M0, the scan
sequence includes both CALGAIN and CALOFF chan-
nels (Table 4). CALOFF always precedes CALGAIN,
even though both channels share the same channel ID
tag (Table 11).
Note that changing the status of any
activechannel
control bits will cause INTto immediately transition high
and the modulator/filter to be reset. INTwill reassert
after the appropriate digital-filter settling time. The con-
trol settings of the inactive channels may be changed
freely without affecting the status of INTor causing the
filter/modulator to be reset.
PGA GainBits G2–G0 control the PGA gain according to Table 6.
Unipolar/Bipolar ModeThe U/Bbit places the channel in either bipolar or
unipolar mode. A 0 selects bipolar mode, and a 1
selects unipolar mode. This bit does not affect the ana-
log-signal conditioning. The modulator always accepts
bipolar inputs and produces a bitstream with 50%
ones-density when the selected inputs are at the same
potential. This bit controls the processing of the digital-
filter output, such that the available output bits are
mapped to the correct output range. Note U/Bmust be
set before a conversion is performed; it will not affect
any data already held in the output register.
Selecting bipolar mode does not imply that any input
may be taken below AGND. It simply changes the gain
and offset of the part. All inputs must remain within their
specified operating voltage range.
Offset-Correction DACsBits D3–D0 control the offset-correction DAC. The DAC
range depends on the PGA gain setting and is
expressed as a percentage of the available full-scale
input range (Table 7).
D3 is a sign bit, and D2–D0 represent the DAC magni-
tude. Note that when a DAC value of 0000 is pro-
grammed (the default), the DAC is disconnected from
the modulator inputs. This prevents the DAC from
degrading noise performance when offset correction is
not required.
Transfer-Function Register MappingTables 8, 9, and 10 show the channel-control register
mapping in the various operating modes.
Table 6. PGA Gain Codes
Table 7. DAC Code vs. DAC Value1x2001x8001x32101x1281
x64
x16
PGA GAIN+66.7
+100
+116.7
UNIPOLAR
DAC VALUE
(% of FSR)+83.3
DAC not connected
DAC not connected
+33.3
+50
+16.7
+33.3
+50+58.3111+41.6011
BIPOLAR
DAC VALUE
(% of FSR)-16.7-25100-8.3000+16.7+25100+8.300
