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MAX1359BETL-MAX1359BETL+-MAX1359BETL+T
16-Bit, Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor
General DescriptionThe MAX1359B smart data-acquisition systems (DAS) is
based on a 16-bit, sigma-delta analog-to-digital converter
(ADC) and system-support functionality for a micro-
processor (µP)-based system. This device integrates
an ADC, DAC, two operational amplifiers, internal
1.25V/2.048V/2.5V selectable reference, temperature
sensors, analog switches, a 32kHz oscillator, a real-
time clock (RTC) with alarm, a high-frequency-locked
loop (FLL) clock, four user-programmable I/Os, an
interrupt generator, and 1.8V and 2.7V voltage monitors
in a single chip.
The MAX1359B has dual 10:1 differential input multi-
plexers (muxes) that accept signal levels from 0 to
AVDD. An on-chip 1x to 8x programmable-gain amplifi-
er (PGA) measures low-level signals and reduces exter-
nal circuitry required.
The MAX1359B operates from a single +1.8V to +3.6V
supply and consumes only 1.4mA in normal mode and
only 6.1µA in sleep mode.
The serial interface is compatible with either SPI™/QSPI™
or MICROWIRE™, and is used to power up, configure,
and check the status of all functional blocks.
The MAX1359B is available in a space-saving 40-pin
TQFN package and is specified over the commercial
(0°C to +70°C) and the extended (-40°C to +85°C) tem-
perature ranges.
ApplicationsBattery-Powered and Portable Devices
Electrochemical and Optical Sensors
Medical Instruments
Industrial Control
Data-Acquisition Systems
Features+1.8V to +3.6V Single-Supply OperationMultichannel 16-Bit Sigma-Delta ADC10sps to 512sps Programmable Conversion Rate
Self and System Offset and Gain Calibration
PGA with Gains of 1, 2, 4, or 8Unipolar and Bipolar Modes
10-Input Differential Multiplexer10-Bit Force-Sense DACUncommitted Op AmpsDual SPDT Analog Switches1.25V, 2.048V, or 2.5V Selectable VoltageReferenceInternal Charge PumpSystem SupportReal Time Clock and Alarm Register
Internal/External Temperature SensorInternal Oscillator with Clock Output
User-Programmable I/O and Interrupt Generator
VDDMonitorsSPI/QSPI/MICROWIRE, 4-Wire Serial InterfaceSpace-Saving (6mm x 6mm x 0.8mm) 40-Pin TQFN
Package
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Ordering Information19-3710; Rev 2; 8/10
PARTTEMP RANGEPIN-PACKAGEMAX1359BETL+-40°C to +85°C40 TQFN-EP**
MAX1359BCTL+0°C to +70°C40 TQFN-EP**
SPI/QSPI are trademarks of Motorola, Inc.
**EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration40
39
38
37
36
35
34
33
32
31
21 22 23 24 25 26 27 28 29 30
CPOUT
IN1+ IN1- OUT2IN2+SW
FBA OUT
AGND IN2-
AIN2
AIN1
REF
REG
DD
CF-
CF+
DVDD
DGND
UPIO1 11
12
13
14
15
16
17
18
19
20
10 9 8 7 6 5 4 3 2 1
CLK
UPIO2 UPIO3 UPIO4
DOUT
SCLK
DIN INT
CLK32K
32KOUT
32KIN
SNO1
SCM1
SNC1
OUT1
SNC2
SCM2
SNO2
MAX1359B
CS
RESET
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +4V
DVDD to DGND.........................................................-0.3V to +4V
AVDDto DVDD ............................................................-4V to +4V
AGND to DGND.....................................................-0.3V to +0.3V
CLK32K to DGND....................................-0.3V to (DVDD+ 0.3V)
UPIO_ to DGND........................................................-0.3V to +4V
Digital Inputs to DGND ............................................-0.3V to +4V
Analog Inputs to AGND...........................-0.3V to (AVDD+ 0.3V)
Digital Output to DGND…........................-0.3V to (DVDD+ 0.3V)
Analog Outputs to AGND.........................-0.3V to (AVDD+ 0.3V)
CPOUT........................................................(DVDD- 0.3V) to +4V
Continuous Current Into Any Pin.........................................50mA
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 25.6mW/°C above +70°C)....2051.3mW
Operating Temperature Range
MAX1359BETL.................................................-40°C to +85°C
MAX1359BCTL...................................................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC DC ACCURACYNoise-Free Resolution
Data rate = 10sps, PGA gain = 2;
data rate = 10sps to 60sps, PGA gain = 1;
no missing codes, Table 1 (Note 2)Bits
Conversion RateNo missing codes, Table 110512sps
Output NoiseNo missing codesTable 1µVRMS
Integral NonlinearityINL
Unipolar mode, AVDD = 3V,
data rate = 40sps, PGA gain = 1,
TA = +25°C
±0.004%FSR
Uncalibrated±1.0Unipolar Offset Error or Bipolar
Zero Error (Note 3)Data rate = 10sps, PGA gain = 1, calibrated±0.003%FSR
Bipolar±2.0Unipolar Offset-Error or Bipolar
Zero-Error Temperature Drift
(Note 4)Unipolar±10
µV/°C
Uncalibrated±0.6Gain Error (Notes 3, 5)Data rate = 10sps, PGA = 1, calibrated±0.003% FSR
Gain-Error Temperature
Coefficient(Notes 4, 6)±1.0ppm/ °C
DC Positive Power-Supply
Rejection RatioPSRRPGA gain = 1, unipolar mode, measured by
full-scale error with AVDD = 1.8V to 3.6V73dB
ADC ANALOG INPUTS (AIN1, AIN2)DC Input Common-Mode
Rejection RatioCMRRPGA gain = 1, unipolar mode85dB
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNormal-Mode 60Hz Rejection
Ratio
Data rate = 10sps or 60sps, PGA gain = 1,
unipolar mode (Note 2)100dB
Normal-Mode 50Hz Rejection
Ratio
Data rate = 10sps or 50sps, PGA gain = 1,
unipolar mode (Note 2)100dB
Absolute Input RangeAGNDAVDDV
Unipolar mode-0.05 /
Gain
VREF /
Gain
Differential Input Range
Bipolar mode-VREF /
Gain
VREF /
Gain
ADC not in measurement mode, mux
enabled, TA ≤ +55°C, inputs = +0.1V to
(AVDD - 0.1V)DC Input Current (Note 7)
TA = +85°C±5
Input Sampling CapacitanceCIN5pF
Input Sampling RatefSAMPLE21.84kHz
External Source Impedance at
InputSee Table 3Table 3kΩ
FORCE-SENSE DAC (RL = 10kΩ and CL = 200pF, FBA = OUTA, unless otherwise noted)ResolutionGuaranteed monotonic10Bits
Differential NonlinearityDNLCode 3D hex to 3FF hex±1LSB
Integral NonlinearityINLCode 3D hex to 3FF hex±4LSB
Offset ErrorReference to code 52 hex±20mV
Offset-Error Tempco±4.4µV/°C
Gain ErrorExcludes offset and voltage reference error±5LSB
Gain-Error TempcoExcludes offset and reference drift±1ppm/°C
Input Leakage Current at SWA/BSWA/B switches open (Notes 7, 8)±1nA
TA = -40°C to +85°C±1nA
TA = 0°C to +70°C±600Input Leakage Current at FBA/B
VFBA/B = +0.3V to
(AVDD - 0.3V)
(Note 7)TA = 0°C to +50°C±400pA
DAC Output Buffer Leakage
CurrentDAC buffer disabled (Note 7)±75nA
Input Common-Mode VoltageAt FBA0AVDD -
0.35V
Line RegulationAVDD = +1.8V to +3.6V40175µV/V
Load RegulationIOUT = ±2mA, CL = 1000pF (Note 2)0.5µV/µA
Output Voltage RangeAGNDAVDDV
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Slew Rate52 hex to 3FF hex code swing rising or
falling, RL = 10kΩ, CL = 100pF40V/ms
Output-Voltage Settling Time10% to 90% rising or falling to ±0.5 LSB65µs
f = 0.1Hz to
10Hz80
Input Voltage NoiseReferred to FBA excludes
reference noisef = 10Hz to
10kHz200
µVP-P
OUTA/B shorted to AGND20Output Short-Circuit CurrentOUTA/B shorted to AVDD15mA
Input-Output SWA Switch
ResistanceBetween SWA and OUTA, HFCK enabled150Ω
SWA Switch Turn-On/Off TimeHFCK enabled100ns
Power-On TimeExcluding reference18µs
EXTERNAL REFERENCE (REF)Input Voltage RangeAGNDAVDDV
Input ResistanceDAC on, internal REF and ADC off2.5MΩ
DC Input Leakage CurrentInternal REF, DAC, and ADC off (Note 7)100nA
INTERNAL VOLTAGE REFERENCE (CREF = 4.7µF)AVDD ≥ +1.8V, TA = +25°C1.2131.251.288
AVDD ≥ +2.2V, TA = +25°C1.9872.0482.109Reference Output VoltageVREF
AVDD ≥ +2.7V, TA = +25°C2.4252.52.575
Output-Voltage Temperature
CoefficientTC(Note 7)15ppm/oC
REF shorted to AGND18mAOutput Short-Circuit CurrentIRSCREF shorted to AVDD90µA
Line RegulationTA = +25°C25µV/V
ISOURCE = 0
to 500µA1.2
Load RegulationTA = +25°C, VREF = 1.25V
ISINK = 0 to
50µA1.7
µV/µA
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLong-Term Stability(Note 9)35ppm/
1000hrs
f = 0.1Hz to 10Hz, AVDD = 3V50Output Noise Voltagef = 10Hz to 10kHz, AVDD = 3V400µVP-P
Turn-On Settling TimeBuffer only, settle to 0.1% of final value100µs
TEMPERATURE SENSORTemperature Measurement
ResolutionADC resolution is 16-bit, 10sps0.11°C/LSB
TA = 0°C to +70°C±0.5Internal Temperature-Sensor
Measurement ErrorTA = -40°C to +85°C±1°C
TA = +32°C to +43°C±0.50
TA = +10°C to +50°C±0.5
TA = 0°C to +70°C±0.5
External Temperature-Sensor
Measurement Error (Note 10)
TA = -40°C to +85°C±1
Temperature Measurement Noise0.18°CRMS
Temperature Measurement
Power-Supply Rejection Ratio0.2°C/V
OP AMP (RL = 10kΩ connected to AVDD / 2)Input Offset VoltageVOSVCM = 0.5V±15mV
Offset-Error Tempco3µV/oC
TA = -40°C to +85°C0.006±1nA
TA = 0°C to +70°C4±300IN1+, IN2+
TA = 0°C to +50°C2±200pA
TA = -40°C to +85°C0.025±1nA
TA = 0°C to +70°C20±600
Input Bias Current (Note 7)IBIAS
IN1-, IN2-
TA = 0°C to +50°C±400pA
Input Offset CurrentIOSV I N 1 _, I N 2 _ = + 0.3V to ( AV D D - 0.3V ) ( N ote 7) ±1nA
Input Common-Mode Voltage
RangeCMVR0AVDD -
0.35V
0 ≤ VCM ≤ 75mV60Common-Mode Rejection RatioCMRR75mV < VCM ≤ AVDD - 0.35V6075dB
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-Supply Rejection RatioPSRRAVDD = +1.8V to +3.6V76.5100dB
Large-Signal Voltage GainAVOL100mV ≤ VOUT_ ≤ AVDD - 100mV (Note 11)90116dB
ISOURCE = 10µA0.005
ISOURCE = 50µA0.025
ISOURCE = 100µA0.05
ISOURCE = 500µA0.25
Sourcing
ISOURCE = 2m A0.5
ISINK = 10µA0.005
ISINK = 50µA0.025
ISINK = 100µA0.05
ISINK = 500µA0.25
Maximum Current DriveΔVOUT
Sinking
ISINK = 2m A0.5
Gain Bandwidth ProductGBWUnity-gain configuration, CL = 1nF80kHz
Phase MarginUnity-gain configuration, CL = 1nF (Note 11)60Degrees
Output Slew RateSRCL = 200pF0.04V/µs
f = 0.1Hz to 10Hz80Input Voltage NoiseUnity-gain
configurationf = 10Hz to 10kHz200µVP-P
VOUT_ shorted to AGND20Output Short-Circuit CurrentVOUT_ shorted to AVDD15mA
Power-On Time15µs
SPDT SWITCHES (SNO_, SNC_, SCM_, HFCK enabled)VSCM_ = 0VTA = 0°C to +50°C45
VSCM_ = 0.5VTA = 0°C to +50°C50On-ResistanceRON
VSCM_ = 0.5V to AVDD150
TA = -40°C to +85°C±1nA
TA = 0°C to +70°C±600SNO_, SNC_ Off-Leakage
Current (Note 7)
ISNO_(OFF)
ISNC_(OFF)
SNO_, SNC_ = +0.5V,
+1.5V; SCM_ = +1.5V,
+0.5VTA = 0°C to +50°C±400pA
TA = -40°C to +85°C±2
TA = 0°C to +70°C±1.2SCM_ Off-Leakage Current
(Note 7)ISCM_(OFF)
SNO_, SNC_ = +0.5V,
+1.5V; SCM_ = +1.5V,
+0.5VTA = 0°C to +50°C±0.8
TA = -40°C to +85°C±2
TA = 0°C to +70°C±1.2SCM_ On-Leakage Current
(Note 7)ISCM_(ON)
SNO_, SNC_ = +0.5V,
+1.5V, or open; SCM_
= +1.5V, +0.5VTA = 0°C to +50°C±0.8
Input Voltage RangeAGNDAVDDV
Turn-On/Off TimetON/tOFFBreak-before-make100ns
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput CapacitanceSNO_, SNC_, or SCM_ = AVDD or AGND;
switch connected to enabled mux input5pF
CHARGE PUMP (10µF at REG and 10µF external capacitor between CF+ and CF-)Maximum Output CurrentIOUT10mA
No load3.23.33.6Output VoltageIOUT = 10mA3.0V
Output Voltage Ripple
10µF external capacitor between CPOUT
and DGND, IOUT = 10mA, excluding ESR of
external capacitormV
Load RegulationIOUT = 10mA, excluding ESR of external
capacitor1520mV/mA
REG Input Voltage RangeInternal linear regulator disabled1.61.8V
REG Input CurrentLinear regulator off, charge pump off3nA
CPOUT Input Voltage RangeCharge pump disabled1.83.6V
CPOUT Input Leakage CurrentCharge pump disabled2nA
SIGNAL-DETECT COMPARATORTSEL[2:0] = 0 hex0
TSEL[2:0] = 4 hex50
TSEL[2:0] = 5 hex100
TSEL[2:0] = 6 hex150
Differential Input-Detection
Threshold Voltage
TSEL[2:0] = 7 hex200
Differential Input-Detection
Threshold Error±10mV
Common-Mode Input Voltage
RangeAGNDAVDDV
Turn-On Time50µs
VOLTAGE MONITORSDVDD Monitor Supply Voltage
RangeFor valid reset1.03.6V
Trip Threshold (DVDD Falling)1.801.851.95V
DVDD Monitor Timeout Reset
Period1.5s
HYSE bit set to logic 1200DVDD Monitor HysteresisHYSE bit set to logic 035mV
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDVDD Monitor Turn-On Time5ms
CPOUT Monitor Supply Voltage
Range1.03.6V
CPOUT Monitor Trip Threshold2.72.82.9V
CPOUT Monitor Hysteresis35mV
CPOUT Monitor Turn-On Time5ms
Internal Power-On Reset Voltage1.7V
32kHz Oscillator (32KIN, 32KOUT)Clock FrequencyDVDD = 2.7V32.768kHz
StabilityDVDD = 1.8V to 3.6V, excluding crystal25ppm
Oscillator Startup Time1500ms
Crystal Load Capacitance6pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)Output Clock Frequency32.768kHz
Absolute Input to Output Clock
JitterCycle to cycle5ns
Input to Output Rise/Fall Time10% to 90%, 30pF load5ns
Input/Output Duty Cycle4060%
HIGH-FREQUENCY CLOCK OUTPUT (CLK)fOUT = fFLL4.86604.91524.9644
fOUT = fFLL / 2, power-up default2.43302.45762.4822
fOUT = fFLL / 41.21651.22881.2411
MHzFLL Output Clock Frequency
fOUT = fFLL / 8608.25614.4620.54kHz
Cycle to cycle, FLL off0.15Absolute Clock JitterCycle to cycle, FLL on1ns
Rise and Fall TimetR/tF10% to 90%, 30pF load10ns
fOUT = 4.9152MHz4060Duty CyclefOUT = 2.4576MHz, 1.2288MHz, 614.4kHz4555%
Uncalibrated CLK Frequency
ErrorFLL calibration not performed±35%
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)Input High VoltageVIH0.7 x
DVDDV
Input Low VoltageVIL0.3 x
DVDDV
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDVDD supply voltage0.7 x
DVDD
UPIO_ Input High Voltage
CPOUT supply voltage0.7 x
CPOUT
DVDD supply voltage0.3 x
DVDD
UPIO_ Input Low Voltage
CPOUT supply voltage0.3 x
CPOUT
Input HysteresisVHYSDVDD = 3.0V200mV
Input CurrentIINVIN = DGND or DVDD (Note 7)±0.01±100nA
Input CapacitanceVIN = DGND or DVDD10pF
VIN = DVDD or CPOUT, pullup enabled±0.011
UPIO_ Input CurrentVIN = DVDD or CPOUT or 0V,
pullup disabled1µA
UPIO_ Pullup Current
VIN = 0V, pullup enabled, UPIO inputs are
pulled up to DVDD or CPOUT with pullup
enabled
0.525µA
DIGITAL OUTPUTS (DOUT, RESET, UPIO_, CLK32K, INT, CLK)Output Low VoltageVOLISINK = 1mA0.4V
Output High VoltageVOHISOURCE = 500µA0.8 x
DVDDV
DOUT Tri-State Leakage CurrentIL±0.01±1µA
DOUT Tri-State Output
CapacitanceCOUT15pF
RESET Output Low VoltageVOLISINK = 1mA0.4V
RESET Output Leakage CurrentOpen-drain output, RESET deasserted0.1µA
ISINK = 1mA, UPIO_ referenced to DVDD0.4UPIO_ Output Low VoltageVOLISINK = 4mA, UPIO_ referenced to CPOUT0.4V
ISOURCE = 500µA, UPIO_ referenced to
DVDD
0.8 x
DVDD
UPIO_ Output High VoltageVOH
ISOURCE = 4mA, UPIO_ referenced to
CPOUTC P OU T
- 0.4
POWER REQUIREMENTAnalog Supply Voltage RangeAVDD1.83.6V
Digital Supply Voltage RangeDVDD1.83.6V
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAVDD = DVDD = 3.6V1.362.0
IMAX
Everything on,
charge pump
unloaded, max
internal temp-sensor
current, clock output
buffers unloaded,
ADC at 512sps
AVDD = DVDD = 3.3V1.151.7Total Supply Current
INORMAL
All on except charge pump and temp
sensor, ADC at 512sps, CLK output buffer
enabled, clock output buffers unloaded
AVDD = DVDD = 3.0V5.186.5TA = -45°C to +85°CAVDD = DVDD = 3.6V6.159
AVDD = DVDD = 3.0V4.425.19Sleep-Mode Supply CurrentISLEEP
TA = +25°CAVDD = DVDD = 3.6V5.568.3
TA = -40°C to +85°C4Shutdown Supply CurrentISHDNAll offTA = +25°C1.6µA
Note 1:Devices are production tested at TA= +25°C and TA= +85°C. Specifications to TA= -40°C are guaranteed by design.
Note 2:Guaranteed by design or characterization.
Note 3:The offset and gain errors are corrected by self-calibration. The calibration process requires measurement to be made at
the selected data rate. The calibration error is therefore in the order of peak-to-peak noise for the selected rate.
Note 4:Eliminate drift errors by recalibration at the new temperature.
Note 5:The gain error excludes reference error, offset error (unipolar), and zero error (bipolar).
Note 6:Gain-error drift does not include unipolar offset drift or bipolar zero-error drift. It is effectively the drift of the part if zero-
scale error is removed.
Note 7:These specs are obtained from characterization during design or from initial product evaluation. Not production tested or
guaranteed.
Note 8:OUTA/B = +0.5V or +1.5V, SWA/B = +1.5V or +0.5V, TA = 0°C to +50°C.
Note 9:Long-term stability is characterized using five to six parts. The bandgaps are turned on for 1000hrs at room temperature
with the parts running continuously. Daily measurements are taken and any obvious outlying data points are discarded.
Note 10:All of the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal)
and 2) the ADC reference voltage is exactly equal to 1.25V. Any variations to this known reference characteristic and volt-
age caused by temperature, loading, or power supply results in errors in the temperature measurement. The actual tem-
perature calculation is performed externally by the microcontroller (µC).
Note 11:Values based on simulation results and are not production tested or guaranteed.
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
OUTPUT NOISE (µVRMS)RATE (sps)GAIN = 1GAIN = 2GAIN = 4GAIN = 81.8203.2861.3450.6603.8453.2571.9280.6303.0652.3171.6310.6252.8732.6621.5190.728
Table 1. Output Noise (Notes 12, 13, and 14)
Note 12:VREF= ±1.25V, bipolar mode, VIN= 1.24912, PGA gain = 1, TA= +85°C.
Note 13:CIN= 5pF, op-amp noise is considered to be the same as the switching noise. The increase of the op amp’s noise contri-
bution is due to large input swing (0 to 3.6V).
Note 14:Assume ±3 sigma peak-to-peak variation; noise-free resolution means no code flicker at given bits’ LSB.
PEAK-TO-PEAK RESOLUTION (Bits)RATE (sps)GAIN = 1GAIN = 2GAIN = 4GAIN = 816.714.815.115.115.614.814.615.215.915.314.815.216.015.114.915.0
Table 2. Peak-to-Peak Resolution
EXTERNAL CAPACITANCE (pF)PARAMETER0 (Note 15)5010050010005000
Resistance (kΩ)35060301041
Table 3. Maximum External Source Impedance Without 16-Bit Gain Error
Note 15:2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance.
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 19)(AVDD = DVDD= +1.8V to +3.6V, external VREF= +1.25V, CLK32K = 32.768kHz (external clock), CREG= 10µF, CCPOUT= 10µF,
10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK Operating FrequencyfSCLK010MHz
SCLK Cycle TimetCYC100ns
SCLK Pulse-Width HightCH40ns
SCLK Pulse-Width LowtCL40ns
DIN to SCLK SetuptDS30ns
DIN to SCLK HoldtDH0ns
SCLK Fall to DOUT ValidtDOCL = 50pF, Figure 240ns
CS Fall to Output EnabletDVCL = 50pF, Figure 248ns
CS Rise to DOUT DisabletTRCL = 50pF, Figure 248ns
CS to SCLK Rise SetuptCSS20ns
CS to SCLK Rise HoldtCSH0ns
DVDD Monitor Timeout PeriodtDSLP(Note 16)1.5s
Wake-Up (WU) Pulse WidthtWUMinimum pulse width required to detect a
wake-up event1µs
Shutdown DelaytDPUThe delay for SHDN to go high after a valid
wake-up event1µs
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)10ms
HFCK Turn-On TimetDFONIf FLLE = 0, the turn-on time for the high-
frequency clock (Notes 7, 18)10µs
CRDY to INT DelaytDFI
The delay for CRDY to go low after the
HFCK clock output has been enabled
(Note 19)
7.82ms
HFCK Disable DelaytDFOF
The delay after a shutdown command has
asserted and before HFCK is disabled
(Note 20)
1.95ms
SHDN Assertion DelaytDPD(Note 21)2.93ms
Note 16:The delay for the sleep voltage monitor output, RESET, to go high after VDDrises above the reset threshold. This is largely
driven by the startup of the 32kHz oscillator.
Note 17:It is gated by an AND function with three inputs—the external RESETsignal, the internal DVDDmonitor output, and the
external SHDNsignal. The time delay is timed from the internal LOVDDgoing high or the external RESETgoing high,
whichever happens later. HFCK always starts in the low state.
Note 18:If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INTor INT are deasserted.
Note 19:CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20:tDFOFgives the µC time to clean up and go into sleep-override mode properly.
Note 21:tDPDis greater than the HFCK delay for the MAX1359B chip to clean up before losing power.
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensortDS
tCSS
tDH
tDVtDOtTR
SCLK
DIN
DOUT
tCSHtCYCtCH
tCL
tCSH
Figure 1. Detailed Serial-Interface Timing
DVDD
CLOAD = 50pF6kΩ
DOUT
a) FOR ENABLE, HIGH IMPEDANCE
TO VOH AND VOL TO VOH
FOR DISABLE, VOH TO HIGH IMPEDANCE
b) FOR ENABLE, HIGH IMPEDANCE
TO VOL AND VOH TO VOL
FOR DISABLE, VOL TO HIGH IMPEDANCE
DOUT
6kΩ
CLOAD = 50pF
Figure 2. DOUT Enable and Disable Time Load Circuits
Typical Operating Characteristics(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
MAX1359B toc01
DVDD (V)
SUPPLY CURRENT (
NORMAL MODE
CLK BUFFER DISABLED
MAX1359B toc02
DVDD (V)
SUPPLY CURRENT (
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGESLEEP MODE, CLK BUFFER DISABLED
32kHz OSC, RTC, DVDD MONITOR ENABLED
MAX1359B toc03
DVDD (V)
SUPPLY CURRENT (
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGESLEEP MODE,
ALL FUNCTIONS DISABLED
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
DVDD SUPPLY CURRENT
vs. TEMPERATUREMAX1359B toc04
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
DVDD = 3.0V
NORMAL MODE
CLK BUFFER DISABLED
DVDD = 1.8V
MAX1359B toc05
TEMPERATURE (°C)
SUPPLY CURRENT (
DVDD SUPPLY CURRENT
vs. TEMPERATURESLEEP MODE, CLK BUFFER DISABLED
32kHz OSC, RTC, DVDD MONITOR ENABLED
DVDD = 3.0V
DVDD = 1.8V
DVDD SUPPLY CURRENT
vs. TEMPERATUREMAX1359B toc06
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
DVDD = 3.0V
SLEEP MODE, ALL
FUNCTIONS DISABLED
DVDD = 1.8V
MAX1359B toc07
AVDD (V)
SUPPLY CURRENT (
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGENORMAL MODE
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAX1359B toc08
AVDD (V)
SUPPLY CURRENT (
SLEEP MODE,
32kHz OSC, RTC, DVDD MONITOR ENABLED
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAX1359B toc09
AVDD (V)
SUPPLY CURRENT (
SLEEP MODE,
ALL FUNCTIONS DISABLED
MAX1359B toc10
TEMPERATURE (°C)
SUPPLY CURRENT (
NORMAL MODE
AVDD SUPPLY CURRENT
vs. TEMPERATUREAVDD = 3.0V
AVDD = 1.8V
MAX1359B toc11
TEMPERATURE (°C)
SUPPLY CURRENT (
AVDD SUPPLY CURRENT
vs. TEMPERATUREAVDD = 3.0V
AVDD = 1.8V
SLEEP MODE,
32kHz OSC, RTC, DVDD MONITOR ENABLED
AVDD SUPPLY CURRENT
vs. TEMPERATUREMAX1359B toc12
TEMPERATURE (°C)
SUPPLY CURRENT (3510-15
AVDD = 3.0V
SLEEP MODE, ALL
FUNCTIONS DISABLED
AVDD = 1.8V
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
MAX1359B toc13
TEMPERATURE (°C)
INTERNAL OSCILLATOR FREQUENCY (MHz)
A: FLL DISABLED; AVDD, DVDD = 1.8V
B: FLL ENABLED
C: FLL DISABLED; AVDD, DVDD = 3.0V
CLK = 2.4576MHz
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX1359B toc14
AVDD, DVDD (V)
INTERNAL OSCILLATOR FREQUENCY (MHz)
FLL ENABLED
CLK = 2.4576MHz
FLL DISABLED
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX1359B toc15
AVDD (V)
REFERENCE OUTPUT VOLTAGE (V)
A: VREF = 1.25V
B: VREF = 2.048V
C: VREF = 2.5V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1359B toc16
OUTPUT CURRENT (μA)
REF
(V)
AVDD = 1.8V
VREF = 1.25V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1359B toc17
REF
(V)
AVDD = 2.5V
VREF = 2.048V
OUTPUT CURRENT (μA)
MAX1359B toc18
REF
(V)
OUTPUT CURRENT (μA)
AVDD = 3.0V
VREF = 2.5V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENTNORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
MAX1359B toc19
NORMALIZED REFERENCE VOLTAGE (V)
VREF = 1.25V
NORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
MAX1359B toc20
NORMALIZED REFERENCE VOLTAGE (V)
VREF = 2.048V
NORMALIZED REFERENCE OUTPUT
VOLTAGE vs. TEMPERATURE
MAX1359B toc21
NORMALIZED REFERENCE VOLTAGE (V)
VREF = 2.5V
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
1s/div
REFERENCE VOLTAGE OUTPUT NOISE
(0.1Hz TO 10Hz)50μV/div
MAX1359B toc22
VREF = +1.25V
AVDD = +1.8V
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCYMAX1359B toc23
FREQUENCY (Hz)10010
100010k
10,000
VREF = 1.25V
NOISE (nV/
Hz)
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCYMAX1359B toc24
FREQUENCY (Hz)10010
100010k
10,000
VREF = 2.048V
NOISE (nV/
Hz)
REFERENCE VOLTAGE OUTPUT
NOISE vs. FREQUENCYMAX1359B toc25
FREQUENCY (Hz)10010
100010k
10,000
VREF = 2.5V
NOISE (nV/
Hz)
ADC MUX INPUT DC CURRENT
vs. TEMPERATURE
MAX1359B toc26
TEMPERATURE (°C)
INPUT CURRENT (
AVDD = 1.8V
VAIN = 0.5V
DAC INL vs. OUTPUT CODE
MAX1359B toc27
OUTPUT CODE
INL (LSB)
AVDD = 1.8V
VREF = 1.25V
DAC INL vs. OUTPUT CODE
MAX1359B toc28
INL (LSB)
AVDD = 2.5V
VREF = 2.048V
DAC INL vs. OUTPUT CODE
MAX1359B toc29
INL (LSB)
AVDD = 3.0V
VREF = 2.5V
DAC DNL vs. OUTPUT CODE
MAX1359B toc30
DNL (LSB)
AVDD = 1.8V
VREF = 1.25V
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
DAC DNL vs. OUTPUT CODE
MAX1359B toc31
OUTPUT CODE
DNL (LSB)
AVDD = 2.5V
VREF = 2.048V
DAC DNL vs. OUTPUT CODE
MAX1359B toc32
OUTPUT CODE
DNL (LSB)
AVDD = 3.0V
VREF = 2.5V
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX1359B toc33
SOURCE CURRENT (mA)
DAC OUTPUT VOLTAGE (V)
CODE = 3FF hex
AVDD = 1.8V, 3.0V
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX1359B toc34
DAC OUTPUT VOLTAGE (V)0.501.001.500.250.751.251.752.00
SOURCE CURRENT (mA)
CODE = 020 hex
AVDD = 1.8V
AVDD = 3.0V
DAC OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1359B toc35
AVDD (V)
DAC OUTPUT VOLTAGE (mV)
CODE = 200 hex
DAC OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1359B toc36
TEMPERATURE (°C)
DAC OUTPUT VOLTAGE (mV)
AVDD = 3.0V
AVDD = 1.8V
VREF = 1.25V
CODE = 200 hex
DAC FBA/B INPUT BIAS CURRENT
vs. TEMPERATURE
MAX1359B toc37
TEMPERATURE (°C)
INPUT BIAS CURRENT (
AVDD = 1.8V
VAIN = 0.5V
1s/div
DAC OUTPUT NOISE
(0.1Hz TO 10Hz)50μV/div
MAX1359B toc38
AVDD = +1.8V
VREF = +1.25V
DAC CODE = 3FF hex
DAC OUTPUT
NOISE vs. FREQUENCYMAX1359B toc39
FREQUENCY (Hz)10010
100010k
10,000
DAC CODE = 3FF hex
VREF = 2.5V
NOISE (nV/
Hz)
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
40μs/div
DAC LARGE-SIGNAL OUTPUT
STEP RESPONSEMAX1359B toc40
VREF = +1.25V
AVDD = +3.0V
2V/div
OUT_
1V/div
OP-AMP INPUT OFFSET VOLTAGE
vs. TEMPERATUREMAX1359B toc41
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (mV)3510-15
AVDD = 1.8V
VCM = 0.5V
AVDD = 3.0V
MAX1359B toc42
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
OP-AMP INPUT BIAS CURRENT
vs. TEMPERATUREAVDD = 1.8V
VCM = 0.5V
MAX1359B toc43
TEMPERATURE (°C)
INPUT BIAS CURRENT (pA)
OP-AMP INPUT BIAS CURRENT
vs. TEMPERATUREAVDD = 3.0V
VCM = 0.5V
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX1359B toc44
SINK CURRENT (mA)
OUTPUT VOLTAGE (mV)
UNITY GAIN, VIN_+ = 0V
AVDD = 1.8V
AVDD = 3.0V
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX1359B toc45
SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
AVDD = 3.0V
UNITY GAIN, VIN_+ = AVDD
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
OP-AMP OUTPUT VOLTAGE
vs. AVDD SUPPLY VOLTAGE
MAX1359B toc48
AVDD (V)
OUTPUT VOLTAGE (mV)
UNITY GAIN, VIN_+ = 0.5V
RL = 10kΩ
MAX1359B toc49
FREQUENCY (Hz)10010
100010k
10,000
NOISE (nV/
Hz)
OP-AMP OUTPUT NOISE
vs. FREQUENCYUNITY GAIN, VIN_+ = 0.5V1.00.51.52.02.53.0
SPDT ON-RESISTANCE
vs. VCOM VOLTAGEMAX1359B toc50
VCOM (V)
AVDD = 3.0V
AVDD = 1.8V
SPST ON-RESISTANCE
vs. VCOM VOLTAGE
MAX1359B toc51
VCOM (V)AVDD = 3.0V
AVDD = 1.8V
OP-AMP OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
MAX1359B toc46
OUTPUT VOLTAGE (V)
UNITY GAIN, VIN_+ = AVDD
AVDD = 1.8V0.500.750.251.001.251.501.752.00
SOURCE CURRENT (mA)
OP-AMP OUTPUT VOLTAGE
vs. TEMPERATUREMAX1359B toc47
TEMPERATURE (°C)
OUTPUT VOLTAGE (mV)3510-15
AVDD = 1.8V
AVDD = 3.0V
UNITY GAIN, VIN_+ = 0.5V
RL = 10kΩ
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
SPDT ON-RESISTANCE
vs. TEMPERATUREMAX1359B toc52
TEMPERATURE (°C)3510-15
AVDD = 3.0V
ICOM = 1mA
AVDD = 1.8V
MAX1359B toc53
TEMPERATURE (°C)
SPST ON-RESISTANCE
vs. TEMPERATUREAVDD = 1.8V, 3.0V
ICOM = 1mA
SPDT/SPST ON/OFF-LEAKAGE
CURRENT vs. TEMPERATUREMAX1359B toc54
TEMPERATURE (°C)
LEAKAGE CURRENT (pA)3510-15
ON-LEAKAGE
OFF-LEAKAGE
AVDD = 1.8V
VCM = 0V
SPDT/SPST SWITCHING TIME
vs. AVDD SUPPLY VOLTAGE
MAX1359B toc55
AVDD (V)
SWITCHING TIMES (ns)
tON
tOFF
SPDT/SPST SWITCHING TIME
vs. TEMPERATUREMAX1359B toc56
TEMPERATURE (°C)
SWITCHING TIMES (ns)3510-15
AVDD = 1.8V
tON
tOFF
SPDT/SPST SWITCHING TIME
vs. TEMPERATUREMAX1359B toc57
TEMPERATURE (°C)
SWITCHING TIMES (ns)3510-15
AVDD = 3.0V
tON
tOFF
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, REF = +1.25V CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
20μs/div
CHARGE-PUMP OUTPUT
VOLTAGE RIPPLEMAX1359B toc63
DVDD = +1.8V
ILOAD = 10mA
CPOUT
20mV/div
AC-COUPLED
MAX1359B toc58
TEMPERATURE (°C)
% DEVIATION
VOLTAGE SUPERVISOR THRESHOLD
vs. TEMPERATUREDVDD SUPERVISOR
CPOUT SUPERVISOR
CHARGE-PUMP OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1359B toc59
OUTPUT CURRENT (mA)
CPOUT VOLTAGE (V)
DVDD = 1.8V
CHARGE-PUMP OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1359B toc60
TEMPERATURE (°C)
CPOUT VOLTAGE (V)
DVDD = 3.0V
DVDD = 1.8V
IOUT = 10mA
CHARGE-PUMP OUTPUT RESISTANCE
vs. CAPACITANCE
MAX1359B toc61
CF (μF)
OUTPUT RESISTANCE (
DVDD = 1.8V
IOUT = 10mA26810
CHARGE-PUMP OUTPUT VOLTAGE
RIPPLE vs. OUTPUT CURRENTMAX1359B toc62
OUTPUT VOLTAGE RIPPLE (mV)
DVDD = 1.8V
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PINNAMEFUNCTIONCLKClock Output. Default is 2.457MHz output clock for µC.UPIO2User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality.UPIO3User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality.UPIO4User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality.
5DOUTSerial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when CS is high, when
UPIO/SPI passthrough mode is enabled, DOUT mirrors the state of UPIO1.SCLKSerial-Clock Input. Clocks data in and out of the serial interface.DINSerial-Data Input. Data is clocked in on SCLK’s rising edge.CS
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high
impedance. High impedance when CS is high, when UPIO/SPI passthrough mode is enabled, DOUT
mirrors the state of UPIO1.INTProgrammable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events.CLK32K
32kHz Clock Input/Output. Outputs 32kHz clock for µC. Can be programmed as an input by enabling the
IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the
internal 32kHz clock derived from the 32kHz crystal.RESET
Active-Low Open-Drain Reset Output. Remains low while DVDD is below the 1.8V voltage threshold and
stays low for a timeout period (tDSLP) after DVDD rises above the 1.8V threshold. RESET also pulses low
when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes.32KOUT32kHz Crystal Output. Connect external 32kHz watch crystal between 32KIN and 32KOUT.32KIN32kHz Crystal Input. Connect external 32kHz watch crystal between 32KIN and 32KOUT.SNO1Analog Switch 1 Normally Open Terminal. Analog input to mux.SCM1Analog Switch 1 Common Terminal. Analog input to mux.SNC1Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).SNO2Analog Switch 2 Normally Open Terminal. Analog input to mux.SCM2Analog Switch 2 Common Terminal. Analog input to mux (open on POR).SNC2Analog Switch 2 Normally Closed Terminal. Analog input to mux.OUT1Amplifier 1 Output. Analog input to mux.IN1-Amplifier 1 Inverting Input. Analog input to mux.IN1+Amplifier 1 Noninverting Input
Pin Description
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PINNAMEFUNCTIONSWADACA SPST Shunt Switch Input. Connects to OUTA through a SPST switch.FBADACA Force-Sense Feedback Input. Analog input to mux.OUTADACA Force-Sense Output. Analog input to mux.AGNDAnalog GroundAVDDAnalog Supply Voltage. Also ADC reference voltage during AVDD measurement. Bypass to AGND with 10µF
and 0.1µF capacitors in parallel as close to the pin as possible.IN2+Amplifier 2 Noninverting InputIN2-Amplifier 2 Inverting Input. Analog input to mux.OUT2Amplifier 2 Output. Analog input to mux.AIN2Analog Input 2. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.AIN1Analog Input 1. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.REFReference Input/Output. Output of the reference buffer amplifier or external reference input. Disabled at
power-up to allow external reference. Reference voltage for ADC and DAC.REGLinear Voltage-Regulator Output. Charge-pump-doubler input voltage. Bypass REG with a 10µF capacitor
to DGND for charge-pump regulation.CF-CF+Charge-Pump Flying Capacitor Terminals. Connect an external 10µF (typ) capacitor between CF+ and CF-.CPOUThar g e- P um p Outp ut. C onnect an exter nal 10µF ( typ ) r eser voi r cap aci tor b etw een C P O U T and D GN D . Ther e i s
a l ow thr eshol d d i od e b etw een D V D D and C P OU T. When the char g e p um p i s d i sab l ed , C P OU T i s p ul l ed up i thi n 300m V ( typ ) of D V D D .DVDDDigital Supply Voltage. Bypass to DGND with 10µF and 0.1µF capacitors in parallel as close to the pin as
possible.DGNDDigital Ground. Also ground for cascaded linear voltage regulator and charge-pump doubler.UPIO1U ser - P r og r am m ab l e Inp ut/O utp ut 1. S ee the U P IO1_C TRL Reg i ster for functionality.
—EPE xp osed P ad . Leave unconnected or connect to AGN D .
Pin Description (continued)
MAX1359B
Detailed DescriptionThe MAX1359B DAS features a multiplexed differential
16-bit ADC, 10-bit force-sense DAC, an RTC with an
alarm, a selectable bandgap voltage reference, a signal-
detect comparator, 1.8V and 2.7V voltage monitors, and
wake-up control circuitry, all controlled by a 4-wire serial
interface. (See Figure 3 for the functional diagram).
The DAS directly interfaces to various sensor outputs
and, once configured, provides the stimulus, signal
conditioning, and data conversion, as well as µP sup-
port. See the Applicationssection for sample
MAX1359B applications.
The 16-bit ADC features programmable continuous con-
version rates as shown in Table 4, and gains of 1, 2, 4,
and 8 (Table 5)to suit applications with different power
and dynamic range constraints. The force-sense DAC
provides 10-bit resolution for precise sensor applica-
tions. The ADCs and DAC utilize a low-drift 1.25V inter-
nal bandgap reference for conversions and full-scale
range setting. The RTC has a 138-year range and pro-
vides an alarm function that can be used to wake up
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorTEMP
SENSOR
REF
AGND
OUTA
OUT2
SCM2
OUT1
AGND
REF
INM1
IN2-
SCM1
FBA
AIN1
SNO1
SNC1
TEMP+
TEMP-
SNO2
SNC2
AIN2
10:1MUX
NEG
10:1MUX
POS
Av = 1, 2, 4, 8 V/VPOLARITY
FLIPPER
PROG. Vos
PGA
Av = 1, 1.6384, 2 V/V
UPIO
DGNDAGND
AVDDDVDD
SERIAL
INTERFACEDIN
DOUT
SCLK
1.25V BANDGAPREF
16-BIT ADC
IN+
IN-
REF
OP1
10-BIT DAC
OUTA
REF
FBA
BUF
SWA
PGA
OUT1
SNO1
SNC1
SCM1
CMP
UPIO1
UPIO2
UPIO3
UPIO4
32.768kHz
OSCILLATOR
32KIN32KOUT
WATCHDOG
TIMER
4.9152MHz HF
OSCILLATOR
AND FLL
CLKCLK32K
AIN2
AIN1
INTERRUPT
INT
PWM
CLK32K
INPUT/OUTPUT
CONTROL
DVDD (1.8V)
VOLTAGE
MONITOR
RTC AND
ALARM
SNO2
SNC2
SCM2
CHARGE-
PUMP
DOUBLER
CF+
CF-
IN1-IN1+
PROG
CURRENT
SOURCE
TEMP+
TEMP-
32K
AIN2
AIN1
CPOUT (2.7V)
VOLTAGE
MONITOR
LINEAR 1.65V
VOLTAGE
REGULATOR
CPOUT
REG
STATUS
RESETLDVD
ALD
CRDY
SDC
ADD
ADOU
UPR<4:1>4
UPF<4:1>
LCPD
CONTROL
LOGIC
HFCLK
M32K
M32K
M32K
HFCLK
WDTO
DVDDMAX1359B
OP2OUT2
IN2-IN2+
SPDT1
SPDT2
the system or cause an interrupt at a predefined time.
The power-supply voltage monitor detects when DVDD
falls below a trip threshold voltage of +1.8V, asserting
RESET. The MAX1359B uses a 4-wire serial interface to
communicate directly between SPI, QSPI, or
MICROWIRE devices for system configuration and
readback functions.
Analog-to-Digital Converter (ADC)The MAX1359B includes a sigma-delta ADC with pro-
grammable conversion rate, a PGA, and a dual 10:1
input mux. When performing continuous conversions at
10sps or single conversions at the 40sps setting (effec-
tively 10sps due to four sample sigma-delta settling),
the ADC has 16-bit noise-free resolution. The noise-free
resolution drops to 10 bits at the maximum sampling
rate of 512sps. Differential inputs support unipolar
(between 0 and VREF) and bipolar (between ±VREF)
modes of operation. Note:Avoid combinations of input
signal and PGA gains that exceed the reference range
at the ADC input. The ADOU bit in the status register
indicates if the ADC has over-ranged or under-ranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
tion, temperature, or AVDDchanges. The ADC-done sta-
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
PGA GainAn integrated PGA provides four selectable gains: +1V/V,
+2V/V, +4V/V, and +8V/V to maximize the dynamic range
of the ADC. Bits GAIN1 and GAIN0 set the gain (see the
ADC Register formore information). The PGA gain is
implemented in the digital filter of the ADC.
ADC ModulatorThe MAX1359B performs analog-to-digital conversions
using a single-bit, 3rd-order, switched-capacitor sigma-
delta modulator. The sigma-delta modulation converts
the input signal into a digital pulse train whose average
duty cycle represents the digitized signal information.
The pulse train is then processed by a digital decimation
filter. The modulator provides 2nd-order frequency shap-
ing of the quantization noise resulting from the single-bit
quantizer. The modulator is fully differential for maximum
signal-to-noise ratio and minimum susceptibility to
power-supply noise.
Signal-Detect ComparatorINT asserts (and remains asserted) within 30µs when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparator’s differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
Analog InputsThe ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
Analog Input ProtectionInternal protection diodes clamp the analog inputs to
AVDDand AGND, and allow the channel input to swing
from (AGND - 0.3V) to (AVDD+ 0.3V). For accurate
conversions near full scale, the inputs must not exceed
AVDDby more than 50mV or be lower than AGND by
50mV. If the inputs exceed (AGND - 0.3V) to (AVDD+
0.3V), limit the current to 50mA.
Analog MuxThe MAX1359B includes a dual 10:1 mux for the positive
and negative inputs of the ADC. Figure 3 illustrates which
signals are present at the inputs of each mux. The
MUXP[3:0] and MUXN[3:0] bits of the mux register select
the input to the ADC and the signal-detect comparator
(Tables 8 and 9). See the mux register description in the
Register Definitions section for multiplexer functionality.
The POL bit of the ADC register swaps the polarity of mux
output signals to the ADC.
Digital FilteringThe MAX1359B contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a SINC4(sinx/x)4response. The SINC4filter has a
settling time of four output data periods (4 x 200ms).
The MAX1359B has 25% overrange capability built into
the modulator and digital filter:
Figure 4 shows the filter frequency response. The
SINC4characteristic -3dB cutoff frequency is 0.228
times the first notch frequency. N
SINNf
SINf
()=⎜⎞⎟⎜⎞⎟⎢⎢⎢⎢⎥⎥⎥⎥π
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1359BThe output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC4filter are
repeated at multiples of the first notch frequency. The
SINC4filter provides an attenuation of better than
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
Force-Sense DAC The MAX1359B incorporates a 10-bit force-sense DAC.
The DAC’s reference voltage sets the full-scale range.
Program the DACA_OP register using the serial inter-
face to set the output voltages of the DAC at OUTA.
Shorting FBA and OUTA configures the DAC in a unity-
gain setting. Connecting resistors in a voltage-divider
configuration between OUTA, FBA, and GND sets a dif-
ferent closed-loop gain for the output amplifier (see the
Applications Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 50µs (unity gain and
loaded with 10kΩin parallel with 200pF). Loads of less
than 1kΩmay degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX1359B features a software-programmable
shutdown mode for the DAC (see the DACA_OP
Register section). DAC output OUTA goes high imped-
ance when powered down. The DAC is normally pow-
ered down at power-on reset.
Charge PumpThe charge pump provides >3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DVDD. See Figures 5 and 6 for block diagrams of
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorFREQUENCY (Hz)
GAIN (dB)
Figure 4. Filter Frequency Response
1.22V
1.65V
LINEAR 1.65V VOLTAGE REGULATOR
DVDD
REG
LDOE
LDOE
Figure 5. Linear-Regulator Block Diagram
CF+
CF-
CPOUT
REG
M32K
CHARGE-PUMP DOUBLER
NONOVERLAP
CLOCK GENERATOR
CPE
Figure 6. Charge-Pump Block Diagram
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (fCLK=
32.768kHz / 2), switch resistances (RSWITCH = 5Ω),
and the external capacitors (10µF) along with their
respective ESRs, as shown below.
Voltage SupervisorsThe MAX1359B provides voltage supervisors to monitor
DVDDand CPOUT. The first supervisor monitors the
DVDDsupply voltage. RESETasserts and sets the corre-
sponding LDVD status bit when DVDDfalls below the
1.8V threshold voltage. When the DVDDsupply voltage
rises above the threshold during power-up, RESET
deasserts after a nominal 1.5s timeout period to give the
crystal oscillator time to stabilize. Set the threshold hys-
teresis using the HYSE bit of the PS_VMONS register.
See the PS_VMONS Registersection for configuring hys-
teresis. There is no separate voltage monitor for AVDD,
but the analog supply is covered by the DVDDmonitor in
many applications where DVDDand AVDDare externally
connected together. Multiple supply applications where
AVDDand DVDDare not connected together require a
separate external voltage monitor for AVDD. See Figure 7
for a block diagram of the DVDD voltage supervisor.
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
AVDDmonitor in applications where the charge pump is
disabled and CPOUT is connected to AVDD. AVDD
must be greater or equal to DVDDwhen CPOUT is used
to monitor AVDD. See Figure 8 for a block diagram of the
CPOUT voltage supervisor.
Interrupt Generator (INT)The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output. RfCRESRESRIIESR
DROOPOUTOUT
OUTCLKFSWITCHCC
RIPPLEOUT
CLKCPOUTOUTCCPOUT
CPOUT ++++24
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorCMP
ANALOG
2:1 MUXCONTROL
LOGIC
RESET
DVDD
1.25V
1.8VTH
2.0VTH
LDVD
LSDE
LSDE
HYSEPORRSTE
DVDD (1.8V) VOLTAGE MONITOR
WDTO
Figure 7. DVDDVoltage-Supervisor Block Diagram
MAX1359B
Crystal OscillatorThe on-chip oscillator requires an external crystal (or
resonator) connected between 32KIN and 32KOUT
with a 32.768kHz operating frequency. This oscillator is
used for the RTC, alarm, PWM, watchdog, charge
pump, and FLL. In any crystal-based oscillator circuit,
the oscillator frequency is sensitive to the capacitive
load (CL). CLis the capacitance that the crystal needs
from the oscillator circuit and not the capacitance of the
crystal. The input capacitance across the 32KIN and
32KOUT is 6pF. Choose a crystal with a 32.768kHz
oscillation frequency and a 6pF capacitive load such
as the C-002RX32-E from Epson Crystal. Using a crys-
tal with a CLthat is larger than the load capacitance of
the oscillator circuit causes the oscillator to run faster
than the specified nominal frequency of the crystal or to
not start up. See Figures 9 and 10 for block diagrams
of the crystal oscillator and the CLK32K I/O.
Real-Time Clock (RTC)The integrated RTC provides the current time information
from a 32-bit counter and subsecond counts from an 8-
bit ripple counter. An internally generated reference
clock of 256Hz (derived from the 32.768kHz crystal) dri-
ves the 8-bit subsecond counter. An overflow of the 8-bit
subsecond counter inputs a 1Hz clock to increment the
32-bit second counter. The RTC 32-bit second counter is
translatable to calendar format with firmware. All 40 bits
(32-bit second counter and 8-bit subsecond counter)
must be clocked in or out for valid data. The RTC and
the 32.768kHz crystal oscillator consume less than 1µA
when the rest of the IC is powered down.
Time-of-Day AlarmProgram the AL_DAY register with a 20-bit value, which
corresponds to a time 1s to 12 days later than the cur-
rent time with a 1s resolution. The alarm status bit, ALD,
asserts when the 20 bits of the AL_DAY register match-
es the 20 LSBs of the 32-bit second counter. The ADE
bit automatically clears when the time-of-day alarm
trips. The time-of-day alarm causes the device to exit
sleep mode.
WatchdogEnable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESETfor 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorCMP
CPOUT
1.25V
2.7VTH
LCPD
CPDE
CPDE
CPOUT (2.7V) VOLTAGE MONITOR
Figure 8. CPOUT Voltage-Supervisor Block Diagram
32KIN
32KOUT
32.768kHz OSCILLATOR
32kHz
OSCILLATOR
OSCE
32K
Figure 9. 32kHz Crystal-Oscillator Block Diagram
IO32E
CLK32K
CK32E
OSCE
CLK32K I/O CONTROL
2:1
MUX
IO32E
IO32E
32K
M32K
Figure 10. CLK32K I/O Block Diagram
High-Frequency ClockAn internal oscillator and a frequency-locked loop (FLL)
are used to generate a 4.9152MHz ±1% high-frequen-
cy clock. This clock and derivatives are used internally
by the ADC, analog switches, and PWM. This clock sig-
nal outputs to CLK. When the FLL is enabled, the high-
frequency clock is locked to the 32.768kHz reference.
If the FLL is disabled, the high-frequency clock is free-
running. At power-up, the CLK pin defaults to a
2.4576MHz clock output, which is compatible with most
µCs. See Figure 12 for a block diagram of the high-fre-
quency clock.
User-Programmable I/OsThe MAX1359B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIO’s are internally pulled
up to DVDD. UPIO_ outputs can be referenced to DVDD
or CPOUT. See the UPIO__CTRL Registerand
UPIO_SPI Registersections for more details on config-
uring the UPIO_ pins.
Program each UPIO1–UPIO4 as one of the following:General-purpose inputPower-mode controlAnalog switch (SPST) and SPDT control inputADC data-ready outputGeneral-purpose outputPWM outputAlarm outputSPI passthrough
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorQQDIVIDE-
BY-8192
32K
WDE
POR
WDWWATCHDOG TIMER
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
4Hz
WDTO
Figure 11. Watchdog Timer Block Diagram
M32KTUNE<8:0>
HFCEFLLE
CRDY
HFCLK
1, 2, 4, 8
DIVIDER
2:1
MUXCLK
CLKE
CKSEL<1:0>
CKSEL2
4.9152MHz HF OSCILLATOR AND FLL
4.9152MHz
32.768kHz
FREQUENCY
COMPARE
FREQ
ERRORDIGITALLY
CONTROLLED
OSCILLATOR
FREQUENCY
INTEGRATOR
Figure 12. High-Frequency Clock and FLL Block Diagram
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Temperature SensorThe internal temperature sensor measures die tempera-
ture and the external temperature sensor measures
remote temperatures. Use the internal temperature sen-
sor or external temperature sensor (remote transistor/
diode) with the ADC and internal current sources to
measure the temperature. For either method, two to four
currents are passed through a p-n junction and sense
resistor, and its temperature is calculated by a µC
using the diode equation and the forward-biased junc-
tion voltage drops measured by the ADC. The tempera-
ture offset between the internal p-n junction and
ambient is negligible. For the four and eight measure-
ment methods, the ratio of currents used in the diode
calculations is precisely known since the ADC mea-
sures the resulting voltage across the same sense
resistor. See Figure 13 for a block diagram of the tem-
perature sensor.
Two-Current MethodFor the two-current method, currents I1and I2are
passed through a p-n junction. This requires two VBE
measurements. Temperature measurements can be
performed using I1and I2.
where k is Boltzman’s constant. A four-measurement
procedure is adopted to improve accuracy by precisely
measuring the ratio of I1and I2: Current I1is driven through the diode and the series
resistor R, and the voltage across the diode is mea-
sured as VBE1. For the same current, the voltage across the diode
and R is measured as V1. Repeat steps 1 and 2 with I2. I1is typically 4µA andis typically 60µA (see Table 21).
Since only four integer numbers are accessible from the
ADC conversions at a certain voltage reference, the previ-
ous equation can be represented in the following manner:
where NV1, NV2, NVBE1, and NVBE2are the measure-
ment results in integer format and VREFis the reference
voltage used in the ADC measurements.
Four-Current Method The four-current method is used to account for the
diode series resistance and trace resistance. The four
currents are defined as follows; I1, I2, M1I1, and M2I2. If
the currents are selected so (M1- 1)I1= (M2- 1)I2, the
effect of the series resistance is eliminated from the
temperature measurements. For the currents I1= 4µA
and I2= 60µA, the factors are selected as M1= 16 and= 2. This results in the currents I3= M1I1= 64µA
and I4= M2I2= 120µA (typ). As in the case of the two-
current method, two measurements per current are
used to improve accuracy by precisely measuring the
values of the currents.Current I1is driven through the diode and the series
resistor R, and the voltage is measured across the
diode using the ADC as NVBE1. For the same current, the voltage across the diode and
the series resistor is measured by the ADC as NV1.qNNNN
MEASVBEVBEVBEVBE
REF ()
ln−⎜⎞⎟212qVVI
MEASBE
ln−()⎜⎞⎟
Figure 13. Temperature-Sensor Measurement Block Diagram
CURRENT
SOURCE
1:3
DEMUX
IVAL<1:0>
IMUX<1:0>
AIN1
AIN2
AIN1
AIN2
TEMP+
TEMP-
PROGRAMMABLE CURRENT SOURCE
TEMP SENSOR
Repeat steps 1 and 2 with I2, I3, and I4.The measured temperature is defined as follows:
where VREFis the reference voltage used and:
External Temperature SensorFor an external temperature sensor, either the two-cur-
rent or four-current method can be used. Connect an
external diode (such as 2N3904 or 2N3906) between
pins AIN1 and AGND (or AIN2 and AGND). Connect a
sense resistor R between AIN1 and AIN2. Maximize R
so the IR drop plus VBEof the p-n junction [(R x
60µA)+VBE] is the smaller of the ADC reference voltage
or (AVDD- 400mV). The same procedure as the internal
temperature sensor can be used for the external tem-
perature sensor, by routing the currents to AIN1 (or
AIN2) (see Table 20).
For the two-current method, if the external diode’s
series resistance (RS) is known, then the temperature
measurement can be corrected as shown below:
Temperature-Sensor CalibrationTo account for various error sources during the temper-
ature measurement, the internal temperature sensor is
calibrated at the factory. The calibrated temperature
equation is shown below:= g x TMEAS+ b
where g and b are the gain and offset calibration val-
ues, respectively. These calibration values are available
for reading from the TEMP_CAL register.
Voltage Reference and BufferAn internal 1.25V bandgap reference has a buffer with
a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, resulting
in a respective 1.25V, 2.048V, or 2.5V reference voltage
at REF. The ADC and DAC use this reference voltage.
The state of the internal voltage reference output buffer at
POR is disabled so it can be driven, at REF, with an exter-
nal reference between AGND and AVDD. The reference
has an initial tolerance of ±3%. Program the reference
buffer through the serial interface. Bypass REF with a
4.7µF capacitor to AGND.
Operational Amplifiers (Op Amps)The MAX1359B includes two op amps. These op amps
feature rail-to-rail outputs, near rail-to-rail inputs, and have
an 80kHz (1nF load) input bandwidth. The DACA_OP
(DACB_OP) register controls the power state of the op
amps. When powered down, the outputs of the op amps
are high impedance.
Single-Pole/Double-Throw (SPDT) SwitchesThe MAX1359B provides two uncommitted SPDT switch-
es. Each switch has a typical on-resistance of 35Ω.
Control the switches through the SW_CTRL register, the
PWM output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
Pulse-Width Modulator (PWM)A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX1359B PWM is more
flexible by allowing the UPIO outputs to be driven to
DVDDor regulated CPOUT logic-high voltage levels.
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is available
independent of µC power state. The FLL is typically dis-
abled in sleep-override mode.
Serial InterfaceThe MAX1359B features a 4-wire serial interface consist-
ing of a chip select (CS), serial clock (SCLK), data in
(DIN), and data out (DOUT). CSmust be low to allow data
to be clocked into or out of the device. DOUT is high
impedance while CSis high. The data is clocked in at
DIN on the rising edge of SCLK. Data is clocked out at
DOUT on the falling edge of SCLK. The serial interface is
compatible with SPI modes CPOL = 0, CPHA = 0 and
CPOL = 1, CPHA = 1. A write operation to the MAX1359B
takes effect on the last rising edge of SCLK. If CSgoes
high before the complete transfer, the write is ignored.
Every data transfer is initiated by the command byte. The
command byte consists of a start bit (MSB), R/Wbit, and
6 address bits. The start bit must be 1 to perform data
transfers to the device. Zeros clocked in are ignored. For
SPI passthrough mode, see the UPIO_SPI register. An
address byte identifies each register. Table 4 shows the
complete register address map for this family of DAS.
Figures 14, 15, and 16 provide timing diagrams for read
and write commands.NNNN
nkInNNACTUALMEASVVBEVVBEVBEVBE
REFS=−−−−⎜⎞⎟×⎜⎜⎜⎟⎟⎟
2211()VBEVBEVBEVBE=−⎜⎞⎟−⎜⎞⎟qNNqNN
nkInM
MEAS
VBEVBEVBEVBEREF=−()−−()⎜⎞⎟31422
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp SensorSCLK
DIN
DOUT
X = DON’T CARE.0A5A4A3A2A1A0DNDN -1DN-2DN-3D2D1D0XX
Figure 14. Serial-Interface Register Write with 8-Bit Control Word, Followed by a Variable Length Data Write
SCLK
DIN
DOUT1A5A4A3A2A1A0XXXXXXXXXDN-1DN-2DN-3D2D1D0
X = DON’T CARE.
Figure 15. Serial-Interface Register Read with 8-Bit Control Word Followed by a Variable Length Data Read
SCLK
DIN
DOUT0A4A3A2A1
DRDYA0D7D6D5D4D3D2D1XD15D14D13D12D11D10D9D8D7D6D5D4D3D2D11A4A3A2A1A0X
ADC
CONV
CHANGES
X = DON’T CARE.
Figure 16. Performing an ADC Conversion (DRDYFunction can be Accessed at UPIO Pins)
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
REGISTER
NAMESTARTCTL
(R/W)
ADR<5:0>
(ADDRESS)
D<39:0>, D<23:0>, D<15:0> OR D<7:0>
(DATA)ADCESTRTBIPPOLCONTADCREFGAIN<1:0>
ADC1R/W00000XRATE<2:0>MODE<2:0>XX
MUX1R/W00001SMUXP<3:0>MUXN<3:0>
DATA1R00010XADC<15:0>
OFFSET CAL1R/W00011XOFFSET<23:0>
GAIN CAL1R/W00100XGAIN<23:0>
RESERVED1R/W00101XReserved. Do not use.
DAE/
OP3E
DBE/
OP2EOP1EXXXDACA<9:8>
DACA_OP1R/W00110X
DACA<7:0>
DAE/
OP3E
DBE/
OP2EOP1EXXXDACB<9:8>
DACB_OP1R/W00111X
DACB<7:0>
REF_SDC1R/W01000XREFV<1:0>AOFFAONSDCETSEL<2:0>
ASEC<19:4>
AL_DAY1R/W01001XASEC<3:0>XXXX
RESERVED1R/W01010XReserved. Do not use.
AWEADEXRWERTCEOSCEFLLEHFCE
CLK_CTRL1R/W01011XCKSEL<2:0>IO32ECK32ECLKEINTPWDE
SEC<31:0>
RTC1R/W01100XSUB<7:0>
PWMEFSEL<2:0>SWAHSWALReser
ved
Reser
ved
PWM_CTRL1R/W01101X
SPD1SPD2XXXXXX
PWMTH<7:0>
PWM_THTP1R/W01110XPWMTP<7:0>
WATCHDOG1W01111XXXXXXXXX
NORM_MD1W10000XXXXXXXXX
SLEEP1W10001XXXXXXXXX
SLEEP_CFG1R/W10010SLPSOSCES C K 32E S P W M E SHDNXXXX
UPIO4_CTRL1R/W10011XUP4MD<3:0>PUP4SV4ALH4LL4
UPIO3_CTRL1R/W10100XUP3MD<3:0>PUP3SV3ALH3LL3
UPIO2_CTRL1R/W10101XUP2MD<3:0>PUP2SV2ALH2LL2
UPIO1_CTRL1R/W10110XUP1MD<3:0>PUP1SV1ALH1LL1
UPIO_SPI1R/W10111XUP4SUP3SUP2SUP1SXXXX
SW_CTRL1R/W11000XSWA—SPDT1<1:0>SPDT2<1:0>XX
TEMP_CTRL1R/W11001XIMUX<1:0>IVAL<1:0>XXXX
TEMP_CAL1R11010XTGAIN<7:0>TOFFS<5:0>XX
MLDVDMLCPDMADOMSDCMCRDYMADDMALDX
IMSK1R/W11011XMUPR<4:1>MUPF<4:1>
RESERVED1R/W11100XReserved. Do not use.
PS_VMONS1R/W11101XLDOECPELSDECPDEHYSERSTEXX
RESERVED1R/W11110XReserved. Do not use.
LDVDLCPDADOUSDCCRDYADDALDX
STATUS1R11111XUPR<4:1>UPF<4:1>
Register Definitions
Table 4. Register Address Map
MAX1359B
16-Bit, Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MSBLSBADCESTRTBIPPOLCONTADCREFGAIN<1:0>
RATE<2:0>MODE<2:0>XX
ADC Register (Power-On State: 0000 0000 0000 00XX)
Register Bit DescriptionsThe ADC register configures the ADC and starts
a conversion.
ADCE: ADC power-enable bit. ADCE = 1 powers up
the ADC, and ADCE = 0 powers down the ADC.
STRT: ADC start bit. STRT = 1 resets the registersinside the ADC filter and initiates a conversion or cali-
bration. The conversion begins immediately after the
16th ADC control bit is clocked by the rising edge of
SCLK. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 when STRT is
asserted, the ADC stops after a single conversion and
holds the result in the DATA register. If CONT = 1 when
STRT is asserted, the ADC performs continuous conver-
sions at the rate specified by the RATE<2:0> bits until
CONT is deasserted or ADCE is deasserted, powering
down the ADC. The STRT bit is automatically deasserted
after the initial conversion is complete (four conversion
cycles, the ADC status bit ADD in the STATUS register
asserts.) The current ADC configurations are not affect-
ed if the ADC register is written with STRT = 0. This
allows the ADC and mux configurations to be updated
simultaneously with the S bit in the MUX register.
BIP: Unipolar/bipolar bit. Set BIP = 0 for unipolar modeand BIP = 1 for bipolar mode. Unipolar-mode data is
unsigned binary format and bipolar is two’s complement.
See the ADC Transfer Functionssection for more details.
POL: Polarity flipper bit. POL = 1 flips the polarity of thedifferential signal to the ADC and the input to the signal-
detect comparator (SDC). POL = 0 sets the positive mux
output to the positive ADC and SDC inputs, and the neg-
ative mux output to the negative ADC and SDC inputs.
POL = 1 sets the positive mux output to the negative
ADC and SDC inputs, and the negative mux output to
the positive ADC and SDC inputs.
CONT: Continuous conversion bit. CONT = 1 enablescontinuous conversions following completion of the first
conversion or calibration(s) initiated by the STRT or S
bit. Set CONT = 0 while asserting the STRT bit, or prior
to asserting the S bit to perform a single conversion or to
prevent conversions following a calibration. Set CONT =
0 to abort continuous conversions already in progress.
When the ADC is stopped in this way, the last complete
conversion result remains in the DATA register and the
internal ADC state information is lost. Asserting the
CONT bit does not restart the ADC, but results in contin-
uous conversions once the ADC is restarted with the
STRT or S bit.
ADCREF: ADC reference source bit. Set ADCREF = 0to select REF as the ADC reference. Set ADCREF = 1
to select AVDDas the ADC reference. To measure the
AVDDvoltage without having to attenuate the supply
voltage, select REF and AGND as the differential inputs
to the ADC, with POL = 0 and while ADCREF = 1.
GAIN<1:0>: ADC gain-setting bits. These two bits
select the gain of the ADC as shown in Table 5.
GAIN SETTING (V/V)GAIN1GAIN00101
Table 5. Setting the Gain of the ADC
