MAX1358BETL+ ,16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp SensorFeatures♦ +1.8V to +3.6V Single-Supply OperationThe MAX1358B smart data-acquisition system (DAS) is ..
MAX1359BETL ,16-Bit, Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp SensorMAX1359B19-3710; Rev 2; 8/1016-Bit, Data-Acquisition System with ADC, DAC,UPIOs, RTC, Voltage Monit ..
MAX1359BETL ,16-Bit, Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp SensorApplications**EP = Exposed pad.Battery-Powered and Portable Devices+Denotes a lead(Pb)-free/RoHS-co ..
MAX1359BETL+ ,16-Bit, Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp SensorFeatures♦ +1.8V to +3.6V Single-Supply OperationThe MAX1359B smart data-acquisition systems (DAS) i ..
MAX1359BETL+T ,16-Bit, Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp SensorELECTRICAL CHARACTERISTICS(AV = DV = +1.8V to +3.6V, V = +1.25V, external reference, f = 32.768kHz ..
MAX135CPI ,15-Bit ADC with Parallel Interface19-4131, Rev o, 9/91
lVI/JXI/I/I
15-Bit ADC with Parallel Interface
MAX4003EUA ,100MHz to 2500MHz, 45dB RF Detector in a UCSPApplicationsA RFIN SHDN GNDSHDN 2 OUT7Cellular Handsets (TDMA, CDMA, GPRS, GSM)MAX4003MAX4003 GND 3 ..
MAX4003EUA ,100MHz to 2500MHz, 45dB RF Detector in a UCSPapplications(-45dBm to 0dBm into 50Ω )including cellular handset PA control, TSSI for wireless Fas ..
MAX4003EUA ,100MHz to 2500MHz, 45dB RF Detector in a UCSPELECTRICAL CHARACTERISTICS(V = 3.0V, V = V , C = 0.1µF, T = -40°C to +85°C. Typical values are at T ..
MAX4003EUA+ ,100MHz to 2500MHz, 45dB RF Detector in a UCSPapplications(-45dBm to 0dBm into 50Ω )including cellular handset PA control, TSSI for wireless♦ Fas ..
MAX4003EUA+T ,100MHz to 2500MHz, 45dB RF Detector in a UCSPApplicationsA RFIN SHDN GNDSHDN 27 OUTCellular Handsets (TDMA, CDMA, GPRS, GSM)MAX4003GND 3 N.C.MAX ..
MAX4004EUT+T ,High-Accuracy, High-Side Current Monitors in SOT23Electrical Characteristics(V = 5V, GND = 0V, REF = Open, V = 0V (MAX4004), CLAMP = Open, T = -40°C ..
MAX1358BETL+
16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor
General DescriptionThe MAX1358Bsmart data-acquisition system (DAS) is
based on a 16-bit, sigma-delta analog-to-digital converter
(ADC) and system-support functionality for a micro-
processor (µP)-based system. This device integrates
an ADC, DACs, operational amplifiers, internal selec-
table-voltage reference, temperature sensors, analog
switches, a 32kHz oscillator, a real-time clock (RTC)
with alarm, a high-frequency-locked loop (FLL) clock,
four user-programmable I/Os, an interrupt generator,
and 1.8V and 2.7V voltage monitors in a single chip.
The MAX1358B has dual 10:1 differential input multiplex-
ers (muxes) that accept signal levels from 0 to AVDD. An
on-chip 1x to 8x programmable-gain amplifier (PGA)
allows measuring low-level signals and reduces external
circuitry required.
The MAX1358B operates from a single +1.8V to +3.6V
supply and consumes only 1.15mA in normal mode and
only 3µA in sleep mode. The MAX1358B has two DACs
with one uncommitted op amp.
The serial interface is compatible with either SPI™/QSPI™
or MICROWIRE™, and is used to power up, configure,
and check the status of all functional blocks.
The MAX1358B is available in a space-saving, 40-pin
TQFN package and is specified over the commercial
(0°C to +70°C) and the extended (-40°C to +85°C) tem-
perature ranges.
ApplicationsBattery-Powered and Portable Devices
Electrochemical and Optical Sensors
Medical Instruments
Industrial Control
Data-Acquisition Systems
Features+1.8V to +3.6V Single-Supply OperationMultichannel, 16-Bit, Sigma-Delta ADC10sps to 477sps Programmable Conversion Rate
Self- and System Offset and Gain Calibration
PGA with Gains of 1, 2, 4, or 8Unipolar and Bipolar Modes
10-Input Differential Multiplexer10-Bit Force-Sense DACsUncommitted Op AmpsDual SPDT and SPST Analog SwitchesSelectable References1.25V, 2.048V, and 2.5VInternal Charge PumpSystem SupportRTC and Alarm Register
Internal/External Temperature SensorInternal Oscillator with Clock Output
User-Programmable I/O and Interrupt Generator
VDDMonitorsSPI/QSPI/MICROWIRE, 4-Wire Serial InterfaceSpace-Saving (6mm x 6mm x 0.8mm), 40-Pin
TQFN Package
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor19-5159; Rev 1; 12/10
SPI/QSPI are trademarks of Motorola, Inc.
40
*EXPOSED PAD.
*EP
39
38
37
36
35
34
33
32
31
21 22 23 24 25 26 27 28 29 30
CPOUT
IN1+ IN1- OUTB SWB SW
FBA OUT
AGND FBB
AIN2
AIN1
REF
REG
DD
CF-
CF+
DVDD
DGND
UPIO1 11
12
13
14
15
16
17
18
19
20
10 9 8 7 6 5 4 3 2 1
CLK
UPIO2 UPIO3 UPIO4
DOUT
SCLK
DIN
INT
CLK32K
32KOUT
32KIN
SNO1
SCM1
SNC1
OUT1
SNC2
SCM2
SNO2
CS
RESET
TQFNTOP VIEW
MAX1358B
Pin Configuration
Ordering Information
PARTTEMP RANGEPIN-PACKAGEMAX1358BCTL+0°C to +70°C40 TQFN-EP*
MAX1358BETL+-40°C to +85°C40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +4V
DVDD to DGND.........................................................-0.3V to +4V
AVDDto DVDD ............................................................-4V to +4V
AGND to DGND.....................................................-0.3V to +0.3V
CLK32K to DGND....................................-0.3V to (DVDD+ 0.3V)
UPIO_ to DGND........................................................-0.3V to +4V
Digital Inputs to DGND ............................................-0.3V to +4V
Analog Inputs to AGND...........................-0.3V to (AVDD+ 0.3V)
Digital Output to DGND…........................-0.3V to (DVDD+ 0.3V)
Analog Outputs to AGND.........................-0.3V to (AVDD+ 0.3V)
CPOUT........................................................(DVDD- 0.3V) to +4V
Continuous Current Into Any Pin.........................................50mA
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 25.6mW/°C above +70°C)....2051.3mW
Operating Temperature Range
MAX1358BCTL+.................................................0°C to +70°C
MAX1358BETL+..............................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC DC ACCURACYNoise-Free Resolution
Data rate = 10sps, PGA gain = 2;
data rate = 10sps to 60sps, PGA gain = 1;
no missing codes, Table 1 (Note 2)Bits
Conversion RateNo missing codes, Table 110477sps
Output NoiseNo missing codesTable 1
Integral NonlinearityINLUnipolar mode, AVDD = 3V,
PGA gain = 1, data rate = 40sps±0.0046%FSR
Uncalibrated±1.0
Unipolar Offset Error (Note 3) or
Bipolar Zero Error (Note 2, 3)PGA gain = 1, calibrated,
TA = +25°C, data rate = 10sps±0.003%FSR
Bipolar1Unipolar Offset-Error or Bipolar
Zero-Error Temperature Drift
(Note 4)Unipolar1
µV/°C
Uncalibrated±0.6Gain Error (Notes 3, 5)PGA = 1, calibrated, data rate = 10sps±0.003%FSR
Gain-Error Temperature
Coefficient(Notes 4, 6)2ppm/ °C
DC Positive Power-Supply
Rejection RatioPSRRPGA gain = 1, unipolar mode, measured by
full-scale error with AVDD = 1.8V to 3.6V85dB
ADC ANALOG INPUTS (AIN1, AIN2)DC Input Common-Mode
Rejection RatioCMRRPGA gain = 1, unipolar mode85dB
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNormal-Mode 60Hz Rejection
Ratio
PGA gain = 1, unipolar mode, data rate =
40sps (Note 2)100dB
Normal-Mode 50Hz Rejection
Ratio
Data rate = 10sps or 40sps, PGA gain = 1,
unipolar mode (Note 2)100dB
Absolute Input RangeVAGNDAVDDV
Unipolar mode-0.05/
Gain
VREF/
Gain
Differential Input Range
Bipolar mode-VREF/
Gain
VREF/
Gain
ADC not in measurement mode, mux
enabled, TA ≤ +55°C, inputs = +0.1V to
(AVDD - 0.1V)DC Input Current (Note 7)
TA = +85°C±5
Input Sampling CapacitanceCIN5pF
Input Sampling RatefSAMPLE21.94kHzxter nal S our ce Im ped ance at Inp utTable 3
FORCE-SENSE DAC (RL = 10kΩ and CL = 200pF, FBA = OUTA, unless otherwise noted)ResolutionGuaranteed monotonic10Bits
Differential NonlinearityDNLCode 3D hex to 3FF hex±1LSB
Integral NonlinearityINLCode 3D hex to 3FF hex±4LSB
Offset ErrorReference to code 52 hex±20mV
Offset-Error Tempco5µV/°C
Gain ErrorExcludes offset and voltage reference error±5LSB
Gain-Error TempcoExcludes offset and reference drift5.6ppm/°C
Input Leakage Current at SWA/BSwitches open (Notes 7, 8)±1nA
TA = -40°C to +85°C±1nA
TA = 0°C to +70°C±600Input Leakage Current at FBA/B
VFBA = +0.3V to
(AVDD - 0.3V)
(Note 7)TA = 0°C to +50°C±400pA
DAC Output Buffer Leakage
CurrentDAC buffer disabled (Note 7)±75nA
Input Common-Mode VoltageAt FBA0AVDD -
0.35V
Line RegulationAVDD = +1.8V to +3.6V, TA = +25°C40175µV/V
Load RegulationIOUT = ±2mA, CL = 1000pF (Note 2)0.5µV/µA
Output Voltage RangeVAGNDAVDDV
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput Slew Rate52 hex to 3FF hex code swing rising or
falling, RL = 10kΩ, CL = 100pF50V/ms
Output-Voltage Settling Time10% to 90% rising or falling to ±0.5 LSB65µs
f = 0.1Hz to
10Hz40
Input-Voltage NoiseReferred to FBA,
excludes reference noisef = 10Hz to
10kHz100
µVP-P
OUTA shorted to AGND20Output Short-Circuit CurrentOUTA shorted to AVDD18mA
Input-Output SWA/SWB
Switch Resistance
Between SW_ and OUT_, HFCLK enabled
(Note 2)150Ω
SWA/SWB Switch Turn-On/Off
TimeHFCLK enabled100ns
Power-On TimeExcluding reference12µs
EXTERNAL REFERENCE (REF)Input Voltage RangeVAGNDAVDDV
Input ResistanceDAC on, internal REF and ADC off2.5MΩ
DC Input Leakage CurrentInternal REF, DAC, and ADC off (Note 7)100nA
INTERNAL VOLTAGE REFERENCE (CREF = 4.7µF)AVDD ≥ +1.8V,
TA = +25°C1.2131.251.288
AVDD ≥ +2.2V,
TA = +25°C1.9872.0482.109Reference Output VoltageVREF
AVDD ≥ +2.7V,
TA = +25°C2.4252.52.575
TA = -40°C to +85°C25Output-Voltage Temperature
Coefficient (Note 7)TC
TA = 0°C to +70°C13
ppm/oC
REF shorted to AGND65mAOutput Short-Circuit CurrentIRSCREF shorted to AVDD90µA
Line Regulation25µV/V
ISOURCE = 0 to 500µA1.2Load RegulationTA = +25°C,
VREF = 1.25VISINK = 0 to 50µA1.7µV/µA
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSLong-Term Stability(Note 9)150ppm/
1000hrs
f = 0.1Hz to 10Hz, AVDD = 3V50Output Noise Voltagef = 10Hz to 10kHz, AVDD = 3V200µVP-P
Turn-On Settling TimeBuffer only, settle to 0.1% of final value100µs
TEMPERATURE SENSORTemperature Measurement
Resolution10sps0.11°C/LSB
TA = 0°C to +50°C±0.5
Internal Temperature-Sensor
Measurement Error (Note 10)
External voltage
reference, two-
current methodTA = -40oC to +85°C±1
TA = +25°C±0.5
TA = 0°C to +50°C±0.5External Temperature-Sensor
Measurement Error (Note 11)
TA = -40°C to +85°C±1.0
Temperature Measurement Noise0.18°CRMS
Temperature Measurement
Power-Supply Rejection Ratio0.2°C/V
OP AMPInput Offset VoltageVOSVCM = 0.5V±1±15mV
Offset-Error Tempco6.2µV/oC
TA = -40°C to +85°C0.006±1nA
TA = 0°C to +70°C4±300IN1+
TA = 0°C to +50°C2±200pA
TA = -40°C to +85°C0.025±1nA
TA = 0°C to +70°C20±600
Input Bias Current (Note 7)IBIAS
IN1-
TA = 0°C to +50°C±400pA
Input Offset CurrentIOSV IN 1 _ = + 0.3V to ( AV D D - 0.3V ) ( N ote 7) ±1nA
Input Common-Mode Voltage
RangeCMVR0AVD D -
0.35V
0 ≤ VC M ≤ 75mV60
75mV < VC M ≤ AVD D - 0.5V, TA = +25°C6075Common-Mode Rejection RatioCMRR
AVD D - 0.5V ≤ VC M ≤ AVD D - 0.35V75
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSPower-Supply Rejection RatioPSRRAVDD = +1.8V to +3.6V, TA = +25°C76.5100dB
Large-Signal Voltage GainAVOL100mV ≤ VOUT_ ≤ AVDD - 100mV (Note 12)90116dB
ISOURCE = 10µA0.005
ISOURCE = 50µA0.025
ISOURCE = 100µA0.05
ISOURCE = 500µA0.25
Sourcing
ISOURCE = 2m A0.5
ISINK = 10µA0.005
ISINK = 50µA0.025
ISINK = 100µA0.05
ISINK = 500µA0.25
Output-Voltage Drop (Note 2)ΔVOUT
Sinking
ISINK = 2m A0.5
Gain Bandwidth ProductGBWUnity-gain configuration, CL = 1nF80kHz
Phase MarginUnity-gain configuration, CL = 1nF (Note 12)60Degrees
Output Slew RateSRCL = 200pF0.05V/µs
f = 0.1Hz to 10Hz50Input-Voltage NoiseUnity-gain
configurationf = 10Hz to 10kHz100µVP-P
VOUT_ shorted to AGND20Output Short-Circuit CurrentVOUT_ shorted to AVDD18mA
Power-On Time12µs
SPDT SWITCHES (SNO_, SNC_, SCM_, HFCLK enabled)VSCM_ = 0VTA = 0°C to +50°C45
VSCM_ = 0.5VTA = 0°C to +50°C50On-Resistance (Note 2)RON
VSCM_ = 0.5V to AVDDTA = -40°C to +85°C150
TA = -40°C to +85°C±1nA
TA = 0°C to +70°C±600SNO_, SNC_ Off-Leakage CurrentISNO_(OFF)
ISNC_(OFF)S N O_ , V S N C _ = + 0.5V ,1.5V ; V S C M _ = + 1.5V ,0.5V ( N ote 7) TA = 0°C to +50°C±400pA
TA = -40°C to +85°C±2
TA = 0°C to +70°C±1.2SCM_ Off-Leakage CurrentISCM_(OFF)S N O_ , V S N C _ = + 0.5V ,1.5V ; V S C M _ = + 1.5V ,0.5V ( N ote 7) TA = 0°C to +50°C±0.8
TA = -40°C to +85°C±2
TA = 0°C to +70°C±1.2SCM_ On-Leakage CurrentISCM_(ON)S N O_ , V S N C _ = + 0.5V ,1.5V , or unconnected ;S C M _ = + 1.5V , + 0.5V N ote 7) TA = 0°C to +50°C±0.8
Input Voltage RangeVAGNDAVDDV
Turn-On/Off TimetON/tOFFBreak-before-make100ns
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput CapacitanceSNO_, SNC_, or SCM_ = AVDD or AGND;
switch connected to enabled mux input2.5pF
CHARGE PUMPMaximum Output CurrentIOUT10mA
No load3.23.33.6Output VoltageIOUT = 10mA3.0V
Output-Voltage RippleIOUT = 10mA, excluding ESR of external
capacitor (Note 2)50mVP-P
Load RegulationIOUT = 10mA, excluding ESR of external
capacitor1520mV/mA
REG Input Voltage RangeInternal linear regulator disabled (Note 2)1.61.8V
REG Input CurrentLinear regulator off, charge pump off3nA
CPOUT Input Voltage RangeCharge pump disabled1.83.6V
CPOUT Input Leakage CurrentCharge pump disabled2nA
SIGNAL-DETECT COMPARATORTSEL[2:0] = 0 hex0
TSEL[2:0] = 4 hex50
TSEL[2:0] = 5 hex100
TSEL[2:0] = 6 hex150
Differential Input-Detection
Threshold Voltage
TSEL[2:0] = 7 hex200
Differential Input-Detection
Threshold Error±10mV
Common-Mode Input Voltage
RangeVAGNDAVDDV
Turn-On Time45µs
VOLTAGE MONITORSDVDD Monitor Supply Voltage
RangeFor valid reset (Note 7)1.43.6V
Trip Threshold (DVDD Falling)1.801.851.95V
DVDD Monitor Timeout Reset
Period1.5s
HYSE bit set to logic 1225DVDD Monitor HysteresisHYSE bit set to logic 040mV
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDVDD Monitor Turn-On Time5ms
CPOUT Monitor Supply Voltage
Range(Note 7)1.43.6V
CPOUT Monitor Trip Threshold2.72.82.9V
CPOUT Monitor Hysteresis35mV
CPOUT Monitor Turn-On Time5ms
Internal Power-On Reset Voltage1.7V
32kHz OSCILLATOR (32KIN, 32KOUT)Clock FrequencyDVDD = 2.7V32.768kHz
StabilityDVDD = 1.8V to 3.6V, excluding crystal25ppm
Oscillator Startup Time1500ms
Crystal Load Capacitance6pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)Output Clock Frequency32.768kHz
Absolute Input to Output Clock
JitterCycle to cycle5ns
Input to Output Rise/Fall Time10% to 90%, 30pF load5ns
Input Duty Cycle4060%
Output Duty Cycle54%
HIGH-FREQUENCY CLOCK OUTPUT (CLK)fOUT = fFLL4.86604.91524.9644
fOUT = fFLL/2, power-up default2.43302.45762.4822
fOUT = fFLL/41.21651.22881.2411
MHzFLL Output Clock Frequency
fOUT = fFLL/8608.25614.4620.54kHz
Cycle to cycle, FLL off0.1Absolute Clock JitterCycle to cycle, FLL on0.5ns
Rise and Fall TimetR/tF10% to 90%, 30pF load10ns
fOUT = 4.9152MHz4060Duty CyclefOUT = 2.4576MHz, 1.2288MHz, 614.4kHz4555%
Uncalibrated CLK Frequency
ErrorFLL calibration not performed±35%
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)Input High VoltageVIH0.7 x
DVDDV
Input Low VoltageVIL0.3 x
DVDDV
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDVDD supply voltage0.7 x
DVDDUPIO_ Input High Voltage
CPOUT supply voltage0.7 x
VCPOUT
DVDD supply voltage0.3 x
DVDD
UPIO_ Input Low Voltage
CPOUT supply voltage0.3 x
VCPOUT
Input HysteresisVHYSDVDD = 3.0V200mV
Input CurrentIINVIN = VDGND or DVDD (Note 7)±0.01±100nA
Input CapacitanceVIN = VDGND or DVDD4pF
VIN = DVDD or VCPOUT, pullup enabled±0.011
UPIO_ Input Current (Note 2)VIN = DVDD or VCPOUT or 0V,
pullup disabled1µA
UPIO_ Pullup Current
VIN = 0V, pullup enabled, unconnected
UPIO_ inputs are pulled up to DVDD or
CPOUT with pullup enabled (Note 2)
0.125µA
DIGITAL OUTPUTS (DOUT, RESET, UPIO_, CLK32K, INT, CLK)Output Low VoltageVOLISINK = 1mA0.4V
Output High VoltageVOHISOURCE = 500µA0.8 x
DVDDV
DOUT Three-State Leakage
CurrentIL±0.01±1µA
DOUT Three-State Output
CapacitanceCOUT4.5pF
RESET Output Low VoltageVOLISINK = 1mA0.4V
RESET Output Leakage CurrentOpen-drain output, RESET deasserted
(Note 7)0.1µA
ISINK = 1mA, UPIO_ referenced to DVDD0.4UPIO_ Output Low VoltageVOLISINK = 4mA, UPIO_ referenced to CPOUT0.4V
ISOURCE = 500µA, UPIO_ referenced to
DVDD
0.8 x
DVDD
UPIO_ Output High VoltageVOH
ISOURCE = 4mA, UPIO_ referenced to
CPOUTC P OU T
- 0.4
POWER REQUIREMENTAnalog Supply Voltage RangeAVDD1.83.6V
Digital Supply Voltage RangeDVDD1.83.6V
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD= +1.8V to +3.6V, VREF= +1.25V, external reference, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT=
10µF, 10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAVDD = DVDD = 3.6V1.22.0
IMAXver ythi ng on,
char g e p um p
unl oad ed , no d i g i tal i ns, si nki ng /sour ci ng
cur r ent, e.g ., RS T ,P IO_, and C LK32K,ax i nter nal tem p -
sensor cur r ent, cl ock
outp ut b uffer s
unl oad ed , AD C at
477sp s
AVDD = DVDD = 2.7V1.151.4
Total Supply Current (Note 2)
INORMAL
All on except charge pump and temp
sensor, ADC at 477sps, CLK output buffer
enabled, clock output buffers unloaded
AVDD = DVDD = 2.7V3.05.2TA = -40°C to +85°CAVDD = DVDD = 3.6V6.7
AVDD = DVDD = 2.7V3.0
Sleep-Mode Supply Current
(IAVDD + IDVDD)ISLEEP
TA = +25°CAVDD = DVDD = 3.6V4.5
TA = -40°C to +85°C2.5Shutdown Supply Current
(IAVDD + IDVDD)ISHDNAll offTA = +25°C1.2µA
Note 1:Devices are production tested at TA= room temperature. Specifications to TA= -40°C and TA= +85°C are guaranteed by design.
Note 2:Guaranteed by design or characterization.
Note 3:The offset and gain errors are corrected by self-calibration or system calibration. For accurate calibrations, perform cali-
bration at the lowest rate. The calibration error is therefore in the order of peak-to-peak noise for the selected rate.
Note 4:Eliminate drift errors by recalibration at the new temperature.
Note 5:The gain error excludes reference error, offset error (unipolar), and zero error (bipolar).
Note 6:Gain-error drift does not include unipolar-offset drift or bipolar zero-error drift. It is effectively the drift of the part if zero-
scale error is removed.
Note 7:These specifications are obtained from characterization during design or from initial product evaluation. Not production
tested or guaranteed.
Note 8:VOUTA= +0.5V or +1.5V, VSWA= +1.5V or +0.5V, TA = 0°C to +50°C.
Note 9:Long-term stability is characterized using five to six parts. The bandgaps are turned on for 1000hrs at room temperature
with the parts running continuously. Daily measurements are taken and any obvious outlying data points are discarded.
Note 10:Temperature error is the difference in the calculated temperature using the internal circuit vs. measurements made using
precision external voltage and current meters. The same diode and diode equation are used for both measurements.
Note 11:All the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal) and
2) the ADC reference voltage is exactly equal to 1.25V. Any variations to this known reference characteristic and voltage
caused by temperature, loading, or power supply results in errors in the temperature measurement. The actual tempera-
ture calculation is performed externally by the µC.
Note 12:Values based on simulation results and are not production tested or guaranteed.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
OUTPUT NOISE (µVRMS)RATE (sps)GAIN = 1GAIN = 2GAIN = 4GAIN = 81.751.751.751.752.922.922.922.923.233.233.233.233.603.603.603.60
Table 1. Output Noise (Notes 13 and 14)
Note 13:VREF= +1.25V, bipolar mode, VIN= 1.24912V, PGA gain = 1, TA= +25°C.
Note 14:Assume ±3 sigma peak-to-peak variation; noise-free resolution means no code flicker at given bits’ LSB.
PEAK-TO-PEAK RESOLUTION (BITS)RATE (sps)
GAIN = 1GAIN = 2GAIN = 4GAIN = 817.5716.5715.5714.5716.8315.8314.8313.8316.6815.6814.6813.6816.5315.5314.5313.53
Table 2. Peak-to-Peak Resolution
EXTERNAL CAPACITANCE (pF)PARAMETER0 (Note 15)5010050010005000
Resistance (kΩ)35060301041
Table 3. Maximum External Source Impedance Without 16-Bit Gain Error
Note 15:2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 19)(AVDD = DVDD= +1.8V to +3.6V, external VREF= +1.25V, fCLK32K= 32.768kHz (external clock), CREG= 10µF, CCPOUT= 10µF,
10µF between CF+ and CF-, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSCLK Operating FrequencyfSCLK010MHz
SCLK Cycle TimetCYC100ns
SCLK Pulse-Width HightCH40ns
SCLK Pulse-Width LowtCL40ns
DIN to SCLK SetuptDS30ns
DIN to SCLK HoldtDH0ns
SCLK Fall to DOUT ValidtDOCL = 50pF, Figure 240ns
CS Fall to DOUT EnabletDVCL = 50pF, Figure 248ns
CS Rise to DOUT DisabletTRCL = 50pF, Figure 248ns
CS to SCLK Rise SetuptCSS20ns
CS to SCLK Rise HoldtCSH0ns
DVDD Monitor Timeout PeriodtDSLP(Note 16)1.5s
Wake-Up (WU) Pulse WidthtWUMinimum pulse width required to detect a
wake-up event1µs
Shutdown DelaytDPUThe delay for SHDN to go high after a valid
wake-up event1µs
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)10ms
HFCLK Turn-On Time (Note 2)tDFON
If FLLE = 0, the turn-on time for the high-
frequency clock (Notes 7, 18)10µs
CRDY to INT DelaytDFI
The delay for CRDY to go low after the
HFCLK clock output has been enabled
(Note 19)
7.82ms
HFCLK Disable DelaytDFOF
The delay after a shutdown command has
asserted and before HFCLK is disabled
(Note 20)
1.95ms
SHDN Assertion DelaytDPD(Note 21)2.93ms
Note 16:The delay for the sleep voltage monitor output, RESET, to go high after VDDrises above the reset threshold. This is largely
driven by the startup of the 32kHz oscillator.
Note 17:FLLE is gated by an AND function with three inputs—the external RESETsignal, the internal DVDDmonitor output, and the
external SHDNsignal. The time delay is timed from the internal LOVDDgoing high or the external RESETgoing high,
whichever happens later. HFCLK always starts in the low state.
Note 18:If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INTor INT is deasserted.
Note 19:CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20:tDFOFgives the µC time to clean up and go into sleep-override mode properly.
Note 21:tDPDis greater than the HFCLK delay to clean up before losing power.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensortDS
tCSS
tDH
tDVtDOtTR
SCLK
DIN
DOUT
tCSHtCYCtCH
tCL
tCSH
Figure 1. Detailed Serial-Interface Timing
DVDD
CLOAD = 50pF6kΩ
DOUT
a) FOR ENABLE, HIGH IMPEDANCE
TO VOH AND VOL TO VOH
FOR DISABLE, VOH TO HIGH IMPEDANCE
b) FOR ENABLE, HIGH IMPEDANCE
TO VOL AND VOH TO VOL
FOR DISABLE, VOL TO HIGH IMPEDANCE
DOUT
6kΩ
CLOAD = 50pF
Figure 2. DOUT Enable and Disable Time Load Circuits
Typical Operating Characteristics(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1358B toc01
AVDD, DVDD (V)
IDVDD
IAVDD
SUPPLY CURRENT (mA)
ALL ON WITH ADC AT 477sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
DVDD SUPPLY CURRENT
vs. DVDD SUPPLY VOLTAGE
MAX1358B toc02
DVDD (V)
SUPPLY CURRENT (µA)
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
SHUTDOWN MODE: ALL OFF
SHUTDOWN MODE
SLEEP MODE
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
AVDD SUPPLY CURRENT
vs. AVDD SUPPLY VOLTAGE
MAX1358B toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
SHUTDOWN MODE: ALL OFF
SLEEP MODE
SHUTDOWN MODE
DVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
ALL ON WITH ADC AT 512sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
DVDD = 3.0V
DVDD = 1.8V
DVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc05
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
DVDD = 3.0V
DVDD = 1.8V
DVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc06
TEMPERATURE (°C)
SUPPLY CURRENT (nA)3510-15
DVDD = 3.0V
DVDD = 1.8V
ALL OFF
AVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
ALL ON WITH ADC AT 512sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
DVDD = 3.0V
DVDD = 1.8V
AVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc08
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
DVDD = 3.0V
DVDD = 1.8V
AVDD SUPPLY CURRENT
vs. TEMPERATURE
MAX1358B toc09
TEMPERATURE (°C)
SUPPLY CURRENT (µA)3510-15
ALL OFF
DVDD = 3.0V
DVDD = 1.8V
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
MAX1358B toc10
OSCILLATOR FREQUENCY (MHz)3510-15
FLL ENABLEDFLL DISABLED
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX1358B toc11
AVDD, DVDD SUPPLY VOLTAGE (V)
INTERNAL OSCILLATOR FREQUENCY (MHz)
FLL ENABLED
FLL DISABLED
CLK = 2.4576MHz
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX1358B toc12
SUPPLY VOLTAGE (V)
REFERENCE OUTPUT VOLTAGE (V)
50kI LOADVREF = 2.50V
VREF = 1.25VVREF = 2.048V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1358B toc13
OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
VREF = 1.25V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1358B toc14
OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
VREF = 2.048V
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1358B toc15
OUTPUT CURRENT (µA)
REFERENCE OUTPUT VOLTAGE (V)
VREF = 2.5V
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc16
TEMPERATURE (°C)
REFERENCE OUTPUT VOLTAGE (V)3510-15
VREF = 1.25V
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc17
REFERENCE OUTPUT VOLTAGE (V)3510-15
VREF = 2.048V
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc18
REFERENCE OUTPUT VOLTAGE (V)3510-15
VREF = 2.5V
REFERENCE DRIFT (0˚C TO 50˚C)
MAX1358B toc18b
OCCURRENCES2116116
VREF = 1.25V
BOX METHOD
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
REFERENCE VOLTAGE OUTPUT NOISE
(0.1Hz TO 10Hz)
MAX1358B toc19
50µV/div
AC-COUPLED
1s/div
REFERENCE NOISE DENSITY vs.
FREQUENCY
MAX1358B toc20
FREQUENCY (Hz)
NOISE (nV/
Hz)
100010,000
VREF = 1.25V
ADC INL vs. OUTPUT CODE
MAX1358B toc21
OUTPUT CODE
INL (LSB)
60k50k40k30k20k10k
-0.01070k
VREF = 2.048V
UNIPOLAR MODE
GAIN = 1
60sps
ADC INL vs. OUTPUT CODE
MAX1358B toc22
OUTPUT CODE
INL (LSB)
60k50k30k40k20k10k
070k
AVDD = DVDD = 1.8V
VREF = 1.25V
BIPOLAR MODE
GAIN = 1
60sps
ADC MAXIMUM INL vs.
SUPPLY VOLTAGE
MAX1358B toc23
SUPPLY VOLTAGE (V)
ADC MAXIMUM INL (%)
VREF = 2.048V
UNIPOLAR MODE
GAIN = 1
60sps
ADC MAXIMUM INL vs.
SUPPLY VOLTAGE
MAX1358B toc24
SUPPLY VOLTAGE (V)
ADC MAXIMUM INL (%)
VREF = 1.25V
BIPOLAR MODE
GAIN = 1
60sps
ADC MAXIMUM INL vs. TEMPERATURE
MAX1358B toc25
ADC MAXIMUM INL (%)3510-15
VREF = 2.048V
UNIPOLAR MODE
GAIN = 1
60sps
ADC MAXIMUM INL vs. TEMPERATURE
MAX1358B toc26
TEMPERATURE (NC)
ADC MAXIMUM INL (%)3510-15
VREF = 1.25V
BIPOLAR MODE
GAIN = 1
60sps
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
ADC MAXIMUM INL vs.
COMMON-MODE INPUT VOLTAGE
MAX1358B toc27
COMMON-MODE VOLTAGE (V)
ADC MAXIMUM INL (%)
VREF = 1.25V
BIPOLAR MODE
GAIN = 1
60sps
MAX1358B toc28
ADC MAXIMUM vs.
OUTPUT DATA RATE
DATA RATE (sps)
ADC MAXIMUM INL (%)
AVDD = DVDD = 1.8V
VREF = 1.25V
BIPOLAR MODE
GAIN = 1
ADC MAXIMUM INL vs. PGA GAIN
MAX1358B toc29
ADC MAXIMUM INL (%)642
PGA GAIN
AVDD = DVDD = 1.8V
VREF = 1.25V
BIPOLAR MODE
60sps
ADC OFFSET ERROR vs.
TEMPERATURE
MAX1358B toc30
TEMPERATURE (NC)
ADC OFFSET ERROR (%)3510-15
VREF = 2.048V
UNIPOLAR MODE
GAIN = 1
60sps
ADC GAIN ERROR vs.
TEMPERATURE
MAX1358B toc31
TEMPERATURE (NC)
ADC GAIN ERROR (%)3510-15
VREF = 2.048V
UNIPOLAR MODE
GAIN = 1
60sps
ADC OFFSET ERROR vs.
SUPPLY VOLTAGE
MAX1358B toc32
SUPPLY VOLTAGE (V)
OFFSER ERROR (%FSR)
VREF = 1.25V
UNIPOLAR MODE
GAIN = 1
60sps
ADC GAIN ERROR vs.
SUPPLY VOLTAGE
MAX1358B toc33
SUPPLY VOLTAGE (V)
GAIN ERROR (%FSR)
VREF = 1.25V
UNIPOLAR MODE
GAIN = 1
60sps
ADC MUX INPUT DC CURRENT vs.
TEMPERATURE
MAX1358B toc34
TEMPERATURE (NC)
INPUT CURRENT (nA)3510-15
AIN1 = AVDD/2
MUX+ = AIN1
MUX- = AGND
ADC CONVERTING
ADC OFF
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
AIN_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc35
VAIN_ (V)
INPUT CURRENT (nA)
TA = +85°C
TA = +25°CTA = +55°C
SW_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc36
VSW_ (V)
INPUT CURRENT (nA)
TA = +85°C
TA = +25°C
TA = +55°C
OUT_ = AVDD/2
FB LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc37
VFB (V)
INPUT CURRENT (nA)
TA = +85°C
TA = +25°C
TA = +55°C
SNO_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc38
VSNO_ (V)
INPUT CURRENT (nA)
SCM_ = AVDD/2
TA = +85°C
TA = +25°C
TA = +55°C
SNC_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc39
VSNC_ (V)
INPUT CURRENT (nA)
SCM_ = AVDD/2
TA = +85°C
TA = +25°C
TA = +55°C
SCM_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc40
VSCM_ (V)
INPUT CURRENT (nA)
SN0_ = SNC_ = AVDD/2
TA = +85°C
TA = +25°C
TA = +55°C
IN1- LEAKAGE CURRENT
vs. INPUT VOLTAGE
MAX1358B toc41
VIN1- (V)
INPUT CURRENT (nA)
TA = +85NC
TA = +55NC
TA = +25NC
DAC INL vs. OUTPUT CODE
MAX1358B toc42
OUTPUT CODE
INL (LSB)
AVDD = 1.8V
VREF = 1.25V
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
DAC INL vs. OUTPUT CODEAX1358B toc43
OUTPUT CODE
INL (LSB)
VREF = 2.048V
DAC DNL vs. OUTPUT CODEAX1358B toc44
OUTPUT CODE
INL (LSB)
AVDD = 1.8V
VREF = 1.25V
DAC DNL vs. OUTPUT CODEAX1358B toc45
OUTPUT CODE
INL (LSB)
VREF = 2.048V
DAC OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
AX1358B toc46
AVDD (V)
DAC OUTPUT VOLTAGE (V)
VREF = 1.25V
CODE = 0x200
RLOAD = 10kI
DAC OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc47
TEMPERATURE (°C)
DAC OUTPUT VOLTAGE (V)3510-15
VREF = 1.25V EXTERNAL
CODE = 0x200
RLOAD = 10kI
AVDD = DVDD = 1.8V3510-15-4085
TEMPERATURE (°C)
INPUT CURRENT (pA)
DAC FB_ INPUT BIAS CURRENT
vs. TEMPERATUREAX1358B toc48
FB_ = AVDD
FB_ = 0
DAC GAIN ERROR vs.TEMPERATURE
MAX1358B toc49
TEMPERATURE (°C)
GAIN ERROR (LSB)35-1510
VREF = 1.25V EXTERNAL
AVDD = DVDD = 1.8V
OFFSET MEASURED AT CODE 0x52
VREF = 2.5V EXTERNAL
AVDD = DVDD = 3.0V
DAC OUTPUT NOISE (0.1Hz TO 10Hz)
MAX1358B toc50
20µV/div
AC-COUPLED
1s/div
REF = 1.25V
AVDD = DVDD = 1.8V
CODE = 0x3FF
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
FREQUENCY (kHz)
DAC OUTPUT-NOISE DENSITY
vs. FREQUENCY
AX1358B toc51
NOISE (nV/
Hz)
VREF = 1.25V
AVDD = DVDD = 1.8V
CODE = 3FF
DAC LARGE-SIGNAL STEP RESPONSE
(0x052 TO 0x3FF)
MAX1358B toc52
500mV/div
2V/div
SCLK
OUTA
10µs/div
OUT_ = FB_
DAC LARGE-SIGNAL STEP RESPONSE
(0x3FF to 0x052)
MAX1358B toc53
500mV/div
SCLK
OUTA
10µs/div
OUT_ = FB_
OP-AMP INPUT OFFSET VOLTAGE
vs. TEMPERATURE
MAX1358B toc54
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)3510-15
VCM = 0.5V
OP-AMP INPUT OFFSET HISTOGRAM
OFFSET (mV)
OCCURRENCES
AX1358B toc55
OP-AMP OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1358B toc56
OP-AMP OUTPUT VOLTAGE (V)
UNITY GAIN
VIN = 0.9V
AVDD = DVDD = 1.8V
OP-AMP OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX1358B toc57
OP-AMP OUTPUT VOLTAGE (V)
UNITY GAIN
VIN = 1.5V
AVDD = DVDD = 3.0V
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
OP-AMP OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc58
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)3510-15
UNITY GAIN
AVDD = DVDD = 1.8V
VIN+ = AVDD/2
RLOAD = 10kI
OP-AMP OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
MAX1358B toc59
SUPPLY VOLTAGE (V)
OP-AMP OUTPUT VOLTAGE (V)
UNITY GAIN
VIN = 0.5V
RLOAD = 10kI
OP-AMP OUTPUT NOISE (0.1Hz TO 10Hz)
MAX1358B toc60
20µV/div
AC-COUPLED
1s/div
UNITY GAIN
VIN1+ = 0.5V
AVDD = DVDD = 1.8V
FREQUENCY (kHz)
OP-AMP OUTPUT-NOISE DENSITY
vs. FREQUENCY
AX1358B toc61
NOISE (nV/
Hz)
VIN+ = 0.5V
AVDD = DVDD = 1.8V
UNITY GAIN
OP-AMP UNITY-GAIN INPUT RANGE
MAX1358B toc62
VIN (V)
OUT
- V
(mV)
AVDD = DVDD = 3.6V
UNITY GAIN
NO LOAD
CLOSED-LOOP OP-AMP GAIN AND PHASE
vs. FREQUENCYMAX1358B toc63
FREQUENCY (Hz)
GAIN (dB)PHASE (°)
100k10k1001k
-180-801M
CLOSED-LOOP GAIN = 1000
RLOAD = 10kI
CLOAD = 200pF
PHASE
GAIN
SPDT ON-RESISTANCE
vs. SCM_ VOLTAGE
MAX1358B toc64
VSCM_ (V)
ISCM_ = 1mA
AVDD = 3V
AVDD = 1.8V
SPST ON-RESISTANCE vs. SW_ VOLTAGE
MAX1358B toc65
VSW_ (V)
ISW_ = 1mA
AVDD = 1.8V
AVDD = 3V
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorSPDT ON-RESISTANCE
vs. TEMPERATURE
MAX1358B toc66
TEMPERATURE (°C)3510-15
VSCM_ = AVDD
ISCM_ = 1mA
AVDD = DVDD = 3.0V
AVDD = DVDD = 1.8V
SPDT ON-RESISTANCE
vs. TEMPERATURE
MAX1358B toc67
TEMPERATURE (°C)3510-15
VSCM_ = AVDD
ISCM_ = 1mA
AVDD = DVDD = 3.0V
AVDD = DVDD = 1.8V
SPST LEAKAGE CURRENT
vs. TEMPERATURE
AX1358B toc68
LEAKA
URRENT
(nA
VIN = AVDD3510-15-4085
TEMPERATURE (°C)
SPDT SWITCHING TIME
vs. SUPPLY VOLTAGE
MAX1358B toc69
AVDD, DVDD (V)
tON
tOFF
TIME (ns)
SPST SWITCHING TIME
vs. SUPPLY VOLTAGE
MAX1358B toc70
AVDD, DVDD (V)
tON
tOFF
TIME (ns)
SPDT/SPST SWITCHING TIME
vs. TEMPERATURE
MAX1358B toc71
TEMPERATURE (°C)
SWITCHING TIME (ns)3510-15
tON
tOFF
RLOAD = 1kI
CLOAD = 35pF
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
INTERNAL TEMPERATURE SENSOR ERROR
vs. AMBIENT TEMPERATURE
AX1358B toc72
TEMPERATURE SENSOR ERROR (°C)-1.5
VREF = 1.250V3510-15-4085
TEMPERATURE (°C)
INTERNAL TEMPERATURE SENSOR ERROR
vs. REFERENCE VOLTAGE
AX1358B toc73
TEMPERATURE SENSOR ERROR (°C)
TA = +85°C
TA = +27°C
TA = -40°C
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorVOLTAGE SUPERVISOR THRESHOLD
vs. TEMPERATURE
MAX1358B toc74
TEMPERATURE (°C)
VOLTAGE THRESHOLD (V)3510-15
CPOUT SUPERVISOR
DVDD SUPERVISOR
FALLING
CHARGE-PUMP OUTPUT VOLTAGE
vs. OUTPUT CURRENT
MAX1358B toc75
OUTPUT CURRENT (mA)
CHARGE-PUMP OUTPUT VOLTAGE (V)642
AVDD = DVDD = 1.8V
CHARGE-PUMP OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1358B toc76
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)3510-15
AVDD = DVDD = 1.8V
ILOAD = 10mA
Typical Operating Characteristics (continued)(DVDD= AVDD = 1.8V, VREF= +1.25V, CCPOUT= 10µF, TA=+25°C, unless otherwise noted.)
CHARGE-PUMP OUTPUT RESISTANCE
vs. CAPACITANCE
AX1358B toc77
CAPACITANCE (µF)
OUTPUT RESISTANCE (15105
AVDD = DVDD = 1.8V
IOUT = 10mA
CHARGE-PUMP OUTPUT-VOLTAGE
RIPPLE vs. OUTPUT CURRENT
MAX1358B toc78
OUTPUT CURRENT (mA)
CHARGE-PUMP OUTPUT-VOLTAGE RIPPLE (mV
P-P642
AVDD = DVDD = 1.8V
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PINNAMEFUNCTIONCLK Clock Output. Default is 2.457MHz output clock for the μC. UPIO2 User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality. UPIO3 User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality. UPIO4 User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality.
5 DOUT Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when CS is high, when
UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1. SCLK Serial-Clock Input. Clocks data in and out of the serial interface. DIN Serial-Data Input. Data is clocked in on SCLK’s rising edge. CS
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high
impedance. High impedance when CS is high; when UPIO/SPI pass-through mode is enabled, DOUT
mirrors the state of UPIO1. INT Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events.
10 CLK32K
32kHz Clock Input/Output. Outputs 32kHz clock for the μC. Can be programmed as an input by enabling
the IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the
internal 32kHz clock derived from the 32kHz crystal. RESET
Active-Low, Open-Drain Reset Output. Remains low while DVDD is below the 1.8V voltage threshold and
stays low for a timeout period (tDSLP) after DVDD rises above the 1.8V threshold. RESET also pulses low
when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes.
12 32KOUT 32kHz Crystal Output. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
13 32KIN 32kHz Crystal Input. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
14 SNO1 Analog Switch 1 Normally Open Terminal. Analog input to mux.
15 SCM1 Analog Switch 1 Common Terminal. Analog input to mux.
16 SNC1 Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).
17 SNO2 Analog Switch 2 Normally Open Terminal. Analog input to mux.
18 SCM2 Analog Switch 2 Common Terminal. Analog input to mux (open on POR).
19 SNC2 Analog Switch 2 Normally Closed Terminal. Analog input to mux.
20 OUT1 Amplifier 1 Output. Analog input to mux.
21 IN1- Amplifier 1 Inverting Input. Analog input to mux.
22 IN1+ Amplifier 1 Noninverting Input
Pin Description
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PINNAMEFUNCTION23 SWA DACA SPST Shunt Switch Input. Connects to OUTA through an SPST switch.
24 FBA DACA Force-Sense Feedback Input. Analog input to mux.
25 OUTA DACA Force-Sense Output. Analog input to mux.
26 AGND Analog Ground
27 AVDDAnalog Supply Voltage. Also ADC reference voltage during AVDD measurement. Bypass to AGND with
10μF and 0.1μF capacitors in parallel as close to the pin as possible.
28 SWB DACB SPST Shunt Switch Input. Connects to OUTB through an SPST switch.
29 FBB DACB Force-Sense Feedback Input. Analog input to mux.
30 OUTB Force-Sense DACB Ouput. Analog input to mux.
31 AIN2 Analog Input 2. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.
32 AIN1 Analog Input 1. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.
33 REF Reference Input/Output. Output of the reference buffer amplifier or external reference input. Disabled at
power-up to allow external reference. Reference voltage for ADC and DACs.
34 REG Linear Voltage-Regulator Output. Charge-pump-doubler input voltage. Bypass REG with a 10μF capacitor
to DGND for charge-pump regulation.
35 CF-
36 CF+ Charge-Pump Flying Capacitor Terminals. Connect an external 10μF (typ) capacitor between CF+ and CF-.
37 CPOUT
Charge-Pump Output. Connect an external 10μF (typ) reservoir capacitor between CPOUT and DGND. There is
a low threshold diode between DVDD and CPOUT. When the charge pump is disabled, CPOUT is pulled up
within 300mV (typ) of DVDD.
38 DVDDDigital Supply Voltage. Bypass to DGND with 10μF and 0.1μF capacitors in parallel as close to the pin as
possible.
39 DGND Digital Ground. Also ground for cascaded linear voltage regulator and charge-pump doubler.
40 UPIO1 User-Programmable Input/Output 1. See the UPIO1_CTRL Register for functionality. EP Exposed Pad. Leave unconnected or connect to AGND.
Pin Description (continued)
MAX1358B
Detailed DescriptionThe MAX1358B DAS features a multiplexed differential
16-bit ADC, 10-bit force-sense DACs, an RTC with an
alarm, a selectable bandgap voltage reference, a signal-
detect comparator, 1.8V and 2.7V voltage monitors, and
wake-up control circuitry, all controlled by a 4-wire serial
interface (see Figure 3 for the functional diagram).
The DAS directly interfaces to various sensor outputs
and, once configured, provides the stimulus, signal con-
ditioning, and data conversion, as well as µP support.
See the Applicationssection for sample MAX1358B
applications.
The 16-bit ADC features programmable continuous con-
version rates as shown in Table 4, and gains of 1, 2, 4,
and 8 (Table 5)to suit applications with different power
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorTEMP
SENSOR
REF
AGND
OUTA
OUTB
SCM2
OUT1
AGND
REF
IN1-
FBB
SCM1
FBA
AIN1
SNO1
SNC1
TEMP+
TEMP-
SNO2
SNC2
AIN2
10:1MUX
NEG
10:1MUX
POS
AV = 1, 2, 4, 8 V/VPOLARITY
FLIPPER
PROG. VOS
PGA
AV = 1, 1.6384, 2 V/V
UPIO
DGNDAGND
AVDDDVDD
SERIAL
INTERFACEDIN
DOUT
SCLK
1.25V BANDGAPREF
16-BIT ADC
IN+
IN-
REF
OP1
10-BIT DAC
OUTA
REF
FBA
BUF
SWA
10-BIT DACOUTB
REF
FBB
BUF
SWB
PGA
OUT1
SNO1
SNC1
SCM1
CMP
UPIO1
UPIO2
UPIO3
UPIO4
32.768kHz
OSCILLATOR
32KIN32KOUT
WATCHDOG
TIMER
4.9152MHz HF
OSCILLATORAND FLL
CLKCLK32K
AIN2
AIN1
INTERRUPT
INT
PWM
CLK32K
INPUT/OUTPUT
CONTROL
DVDD (1.8V)
VOLTAGE
MONITOR
RTC AND
ALARM
SNO2
SNC2
SCM2
CHARGE-
PUMP
DOUBLER
CF+
CF-
IN1-IN1+
PROG
CURRENT
SOURCE
TEMP+
TEMP-
32K
AIN2
AIN1
CPOUT (2.7V)
VOLTAGE
MONITOR
LINEAR 1.65V
VOLTAGE
REGULATOR
CPOUT
REG
STATUS
RESETLDVD
ALD
CRDY
SDC
ADD
ADOU
UPR<4:1>4
UPF<4:1>
LCPD
CONTROL
LOGIC
HFCLK
M32K
M32K
M32K
HFCLK
WDTO
DVDDMAX1358B
SPDT1
SPDT2
Figure 3. Functional Diagram
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensorand dynamic range constraints. The force-sense DAC
provides 10-bit resolution for precise sensor applica-
tions. The ADC and DACs both utilize a low-drift 1.25V
internal bandgap reference for conversions and full-
scale range setting. The RTC has a 138-year range and
provides an alarm function that can be used to wake up
the system or cause an interrupt at a predefined time.
The power-supply voltage monitor detects when DVDD
falls below a trip threshold voltage of +1.8V and asserts
RESET. The MAX1358B uses a 4-wire serial interface to
communicate directly among SPI, QSPI, or
MICROWIRE devices for system configuration and
readback functions.
Analog-to-Digital Converter (ADC)The MAX1358B includes a sigma-delta ADC with pro-
grammable conversion rate, a PGA, and a dual 10:1
input mux. When performing continuous conversions at
10sps or single conversions at the 40sps setting (effec-
tively 10sps due to four sample sigma-delta settling),
the ADC has 16-bit noise-free resolution. The noise-free
resolution drops to 10 bits at the maximum sampling
rate of 477sps. Differential inputs support unipolar
(between 0 and VREF) and bipolar (between ±VREF)
modes of operation. Note:Avoid combinations of input
signal and PGA gains that exceed the reference range
at the ADC input. The ADOU bit in the STATUSregister
indicates if the ADC has overranged or underranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
tion, temperature, or AVDDchanges. The ADC-done sta-
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
PGA GainAn integrated PGA provides four selectable gains (+1V/V,
+2V/V, +4V/V, and +8V/V) to maximize the dynamic
range of the ADC. Bits GAIN1 and GAIN0 set the gain
(see the ADC Register formore information). The PGA
gain is implemented in the digital filter of the ADC.
ADC ModulatorThe MAX1358B performs analog-to-digital conversions
using a single-bit, 3rd-order, switched-capacitor sigma-
delta modulator. The sigma-delta modulation converts
the input signal into a digital pulse train whose average
duty cycle represents the digitized signal information.
The pulse train is then processed by a digital decimation
filter. The modulator provides 2nd-order frequency shap-
ing of the quantization noise resulting from the single-bit
quantizer. The modulator is fully differential for maximum
signal-to-noise ratio and minimum susceptibility to
power-supply noise.
Signal-Detect ComparatorINT asserts (and remains asserted) within 30µs when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparator’s differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
Analog InputsThe ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
Analog Input ProtectionInternal protection diodes clamp the analog inputs to
AVDDand AGND and allow the channel input to swing
from (AGND - 0.3V) to (AVDD+ 0.3V). For accurate
conversions near full scale, the inputs must not exceed
AVDDby more than 50mV or be lower than AGND by
50mV. If the inputs exceed (AGND - 0.3V) to (AVDD+
0.3V), limit the current to 50mA.
Analog MuxThe MAX1358B includes a dual 10:1 mux for the positive
and negative inputs of the ADC. Figure 3 illustrates which
signals are present at the inputs of each mux for the
MAX1358B. The MUXP[3:0] and MUXN[3:0] bits of the
MUXregister select the input to the ADC and the signal-
detect comparator (Tables 8 and 9). See the MUXregister
description in the Register Definitions section for multi-
plexer functionality. The POL bit of the ADC register
swaps the polarity of mux output signals to the ADC.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Digital FilteringThe MAX1358B contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a sinc4(sinx/x)4response. The sinc4filter has a
settling time of four output data periods (4 x 200ms).
The MAX1358B has 25% overrange capability built into
the modulator and digital filter:
Figure 4 shows the filter frequency response. The sinc4
characteristic -3dB cutoff frequency is 0.228 times the
first notch frequency.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the sinc4filter are
repeated at multiples of the first notch frequency. The
sinc4filter provides an attenuation of better than 100dB
at these notches. For example, 50Hz is equal to five
times the first notch frequency and 60Hz is equal to six
times the first notch frequency.
Force-Sense DAC The MAX1358B incorporates two 10-bit force-sensing
DACs. The DACs’ reference voltage sets the full-scale
range. Program the DACA_OP register using the serial
interface to set the output voltages of the DAC at OUTA.
Connecting resistors in a voltage-divider configuration
between OUTA, FBA, and GND sets a different closed-
loop gain for the output amplifier (see the Applications
Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 65µs (unity gain and
loaded with 10kΩin parallel with 200pF). Loads of less
than 1kΩcould degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX1358B features a software-programmable
shutdown mode for the DAC. Power down DACA or
DACB independently or simultaneously by clearing the
DAE and DBE bits (see the DACA_OP Register and
DACB_OP Register sections). DAC output OUTA and
OUTB go high impedance when powered down. The
DACs are normally powered down at power-on reset.
Charge PumpThe charge pump provides > 3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DVDD. See Figures 5 and 6 for block diagrams of
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (fCLK=
32.768kHz/2), switch resistances (RSWITCH = 5Ω), and
the external capacitors (10µF) along with their respec-
tive ESRs, as shown below.RfCRESRESRIIESR
DROOPOUTOUT
OUTCLKFSWITCHCC
RIPPLEOUT
CLKCPOUTOUTCCPOUT
CPOUT ++++24N
SINNf
SINf=⎜⎞⎟⎜⎞⎟⎢⎢⎢⎢⎥⎥⎥⎥
FREQUENCY (Hz)
GAIN (dB)
Figure 4. Filter Frequency Response
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Voltage SupervisorsThe MAX1358B provides voltage supervisors to monitor
DVDDand CPOUT. The first supervisor monitors the
DVDDsupply voltage. RESETasserts and sets the corre-
sponding LDVD status bit when DVDDfalls below the
1.8V threshold voltage. When the DVDDsupply voltage
rises above the threshold during power-up, RESET
deasserts after a nominal 1.5s timeout period to give the
crystal oscillator time to stabilize. Set the threshold hys-
teresis using the HYSE bit of the PS_VMONS register.
See the PS_VMONS Registersection for configuring hys-
teresis. There is no separate voltage monitor for AVDD,
but the analog supply is covered by the DVDDmonitor in
many applications where DVDDand AVDDare externally
connected together. Multiple supply applications where
AVDDand DVDDare not connected together require a
separate external voltage monitor for AVDD. See Figure 7
for a block diagram of the DVDD voltage supervisor.
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
AVDDmonitor in applications where the charge pump is
disabled and CPOUT is connected to AVDD. AVDD
must be greater or equal to DVDDwhen CPOUT is used
to monitor AVDD. See Figure 8 for a block diagram of the
CPOUT voltage supervisor.
Interrupt Generator (INT)The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default, and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
1.22V
1.65V
LINEAR 1.65V VOLTAGE REGULATOR
DVDD
REG
LDOE
LDOE
Figure 5. Linear-Regulator Block Diagram
CF+
CF-
CPOUT
REG
M32K
CHARGE-PUMP DOUBLER
NONOVERLAP
CLOCK GENERATOR
CPE
Figure 6. Charge-Pump Block Diagram
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Crystal OscillatorThe on-chip oscillator requires an external crystal (or
resonator) connected between 32KIN and 32KOUT
with a 32.768kHz operating frequency. This oscillator is
used for the RTC, alarm, PWM, watchdog, charge
pump, and FLL. In any crystal-based oscillator circuit,
the oscillator frequency is sensitive to the capacitive
load (CL). CLis the capacitance that the crystal needs
from the oscillator circuit and not the capacitance of the
crystal. The input capacitance across 32KIN and
32KOUT is 6pF. Choose a crystal with a 32.768kHz
oscillation frequency and a 6pF capacitive load such
as the C-002RX32-E from Epson Crystal. Using a crys-
tal with a CLthat is larger than the load capacitance of
the oscillator circuit causes the oscillator to run faster
than the specified nominal frequency of the crystal or to
not start up. See Figures 9 and 10 for block diagrams
of the crystal oscillator and the CLK32K I/O.
Real-Time Clock (RTC)The integrated RTC provides the current time information
from a 32-bit counter and subsecond counts from an
8-bit ripple counter. An internally generated reference
clock of 256Hz (derived from the 32.768kHz crystal) dri-
ves the 8-bit subsecond counter. An overflow of the 8-bit
subsecond counter inputs a 1Hz clock to increment the
32-bit second counter. The RTC 32-bit second counter is
translatable to calendar format with firmware. All 40 bits
(32-bit second counter and 8-bit subsecond counter)
must be clocked in or out for valid data. The RTC and
the 32.768kHz crystal oscillator consume less than 1µA
when the rest of the device is powered down.
Time-of-Day AlarmProgram the AL_DAY register with a 20-bit value, which
corresponds to a time 1s to 12 days later than the cur-
rent time with a 1s resolution. The alarm status bit, ALD,
asserts when the 20 bits of the AL_DAY register match-
es the 20 LSBs of the 32-bit second counter. The ADE
bit automatically clears when the time-of-day alarm
trips. The time-of-day alarm causes the device to exit
sleep mode.
CMP
ANALOG
2:1 MUXCONTROL
LOGIC
RESET
DVDD
1.25V
1.8VTH
2.0VTH
LDVD
LSDE
LSDE
HYSEPORRSTE
DVDD (1.8V) VOLTAGE MONITOR
WDTO
Figure 7. DVDDVoltage-Supervisor Block Diagram
CMP
CPOUT
1.25V
2.7VTH
LCPD
CPDE
CPDE
CPOUT (2.7V) VOLTAGE MONITOR
Figure 8. CPOUT Voltage-Supervisor Block Diagram
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
WatchdogEnable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESETfor 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
High-Frequency ClockAn internal oscillator and an FLL are used to generate a
4.9152MHz ±1% high-frequency clock. This clock and
derivatives are used internally by the ADC, analog
switches, and PWM. This clock signal outputs to CLK.
When the FLL is enabled, the high- frequency clock is
locked to the 32.768kHz reference. If the FLL is dis-
abled, the high-frequency clock is free-running. At
power-up, the CLK pin defaults to a 2.4576MHz clock
output, which is compatible with most µCs. See Figure
12 for a block diagram of the high-frequency clock.
User-Programmable I/OsThe MAX1358B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DVDD. UPIO_ outputs can be referenced to DVDD
or CPOUT. See the UPIO__CTRL Registerand
UPIO_SPI Registersections for more details on config-
uring the UPIO_ pins.
32KIN
32KOUT
32.768kHz OSCILLATOR
32kHz
OSCILLATOR
OSCE
32K
Figure 9. 32kHz Crystal-Oscillator Block Diagram
IO32E
CLK32K
CK32E
OSCE
CLK32K I/O CONTROL
2:1
MUX
IO32E
IO32E
32K
M32K
Figure 10. CLK32K I/O Block DiagramQQDIVIDE-
BY-8192
32K
WDE
POR
WDWWATCHDOG TIMER
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
4Hz
WDTO
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorProgram each UPIO1–UPIO4 as one of the following:General-purpose inputPower-mode controlAnalog switch (SPST) and SPDT control inputADC data-ready outputGeneral-purpose outputPWM outputAlarm outputSPI pass-through
Internal and External (Remote)
Temperature SensorsAn internal transistor or a remote transistor (or diode) is
used with the ADC and a programmable current source
to measure the ambient temperature. Depending on the
method, either two or four currents are passed through
the PN junction. The voltage across the PN junction is
measured at each current. For each current, the voltage
across a series resistor is also measured. Measuring the
voltage across the resistor allows the user to determine
the precise current ratios. A microcontroller can then
use the diode equation to calculate the temperature.
The four-current method eliminates errors caused by
parasitic resistance in series with the diode, which
increases the apparent voltage across the PN junction.
When measuring temperature using the internal transis-
tor for a sensor, the two-current method is usually ade-
quate although the four-current method can also be
used. Refer to Application Note 4296: Measuring
Temperature with the MAX1358 Data Acquisition System
for details on the measurement procedure.
M32KTUNE<8:0>
HFCEFLLE
CRDY
HFCLK
1, 2, 4, 8
DIVIDER
2:1
MUXCLK
CLKE
CKSEL<1:0>
CKSEL2
4.9152MHz HF OSCILLATOR AND FLL
4.9152MHz
32.768kHz
FREQUENCY
COMPARE
FREQ
ERRORDIGITALLY
CONTROLLED
OSCILLATOR
FREQUENCY
INTEGRATOR
Figure 12. High-Frequency Clock and FLL Block Diagram
Figure 13. Temperature-Sensor Measurement Block Diagram
CURRENT
SOURCE
1:3
DEMUX
IVAL<1:0>
IMUX<1:0>
AIN1
AIN2
AIN1
AIN2
TEMP+
TEMP-
PROGRAMMABLE CURRENT SOURCE
TEMP SENSOR
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorThe temperature equations for the two-current and four-
current methods are as follows:
Two-current method:
T = q(VBE2- VBE1)/(n k ln(VR2/VR1))
Four-current method:
T = q(VBE2+ VBE3- VBE1- VBE4)/(n k ln((VR2 x
VR3)/(VR1 x VR4))
where T is the temperature in degrees Kelvin, VBEXis
the base to emitter voltage at current X, VRXis the volt-
age across the current-sensing resistor at current X, q
is the charge on an electron, k is Boltzmann’s constant,
and n is the ideality factor for the diode. From a practi-
cal standpoint, it is easiest to combine all the constants
into one constant that also includes the voltage resolu-
tion of the ADC in unipolar mode. This requires intro-
ducing the term VREF, which is the reference voltage of
the ADC. An N prefix on a term indicates that it is the
integer value read directly from the ADC.
Two-current method:
T = 0.1771 x VREF(NVBE2- NVBE1)/ln(NVR2/NVR1)
Four-current method:
T = 0.1771 x VREF((NVBE2+ NVBE3- NVBE1-
NVBE4)/ln(NVR2 xNVR3/NVR1/NVR4)
The natural log function (ln) is eliminated from the cal-
culation by using an approximation. Due to the small
part-to-part variation in current ratios, this approxima-
tion is extremely accurate.
Two-current method without an ln function:
T = 0.1771 x VREF(NVBE2– NVBE1)/(2.7081 +
2_(NVR2/NVR1- 15)/(NVR2/NVR1+ 15)
Four-current method without an ln function:
T = 0.1771 x VREF(NVBE2+ NVBE3- NVBE1-
NVBE4)/(2.0794 + 2(NVR2 x NVR3/NVR1/NVR4- 8)/
(NVR2 x NVR3/NVR1/NVR4+ 8)
q = electron charge = 1.60219 x 10-19coulombs
n = diode ideality = 1.000 (typ)
k = Boltzmann's constant = 1.3807 x10-23Joules/Kelvin
I1 = Nominal current (4µA)
I2 = Nominal current ng (60µA)
I3 = Nominal current (64µA)
I4 = Nominal current (120µA)
To convert the measured temperature in Kelvin to
degrees Celsius, the following formula is used:
°C = K - 273.15
For the external temperature measurement, a transistor
such as the 2N3904is recommended.
Voltage Reference and BufferAn internal 1.25V bandgap reference has a buffer with
a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, result-
ing in nominally 1.25V, 2.048V, or 2.5V reference volt-
age at REF. The ADC and DACs use this reference
voltage. The state of the internal voltage reference
output buffer at POR is disabled so it can be driven, at
REF, with an external reference between AGND and
AVDD. The MAX1358B reference has an initial toler-
ance of ±1%. Program the reference buffer through
the serial interface. Bypass REF with a 4.7µF capaci-
tor to AGND.
Uncommitted Operational
Amplifiers (Op Amps)The MAX1358B includes one op amp. The op amp fea-
tures rail-to-rail outputs, near rail-to-rail inputs, and has
an 80kHz (1nF load) input bandwidth. The DACA_OP
(DACB_OP) register controls the power state of the op
amps. When powered down, the outputs of the op
amps is high impedance.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Single-Pole/Double-Throw (SPDT) SwitchesThe MAX1358B provides two uncommitted SPDT switch-
es. Each switch has a typical 35Ω on-resistance. Control
the switches through the SW_CTRL register, the PWM
output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
Pulse-Width Modulator (PWM)A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX1358B PWM is more
flexible by allowing the UPIO outputs to be driven to
DVDDor regulated CPOUT logic-high voltage levels.
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is avail-
able independent of µC power state. The FLL is typical-
ly disabled in sleep-override mode.
Serial InterfaceThe MAX1358B features a 4-wire serial interface con-
sisting of a chip select (CS), serial clock (SCLK), data
in (DIN), and data out (DOUT). CSmust be low to allow
data to be clocked into or out of the device. DOUT is
high impedance while CSis high. The data is clocked
in at DIN on the rising edge of SCLK. Data is clocked
out at DOUT on the falling edge of SCLK. The serial
interface is compatible with SPI modes CPOL = 0,
CPHA = 0 and CPOL = 1, CPHA = 1. A write operation
to the MAX1358B takes effect on the last rising edge of
SCLK. If CSgoes high before the complete transfer, the
write is ignored. Every data transfer is initiated by the
command byte. The command byte consists of a start
bit (MSB), R/Wbit, and 6 address bits. The start bit
must be 1 to perform data transfers to the device.
Zeros clocked in are ignored. For SPI pass-through
mode, see the UPIO_SPI Register section. An address
byte identifies each register. Table 4 shows the com-
plete register address map for this family of DAS.
Figures 14, 15, and 16 provide timing diagrams for
read and write commands.
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp SensorSCLK
DIN
DOUT
X = DON’T CARE.0A5A4A3A2A1A0DNDN -1DN-2DN-3D2D1D0XX
Figure 14. Serial-Interface Register Write with 8-Bit Control Word, Followed by a Variable Length Data Write
SCLK
DIN
DOUT1A5A4A3A2A1A0XXXXXXXXXDN-1DN-2DN-3D2D1D0
X = DON’T CARE.
Figure 15. Serial-Interface Register Read with 8-Bit Control Word, Followed by a Variable Length Data Read
SCLK
DIN
DOUT0A4A3A2A1
DRDYA0D7D6D5D4D3D2D1XD15D14D13D12D11D10D9D8D7D6D5D4D3D2D11A4A3A2A1A0X
ADC
CONV
CHANGES
X = DON’T CARE.
Figure 16. Performing an ADC Conversion (DRDYFunction Can Be Accessed at UPIO Pins)
MAX1358B
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
REGISTER
NAMESTARTCTL
(R/W)
ADR<5:0>
(ADDRESS)
D<39:0>, D<23:0>, D<15:0> OR D<7:0>
(DATA)ADCE STRT BIP POL CONT ADCREF GAIN<1:0>
ADC1 R/W 0 0 0 0 0 X RATE<2:0> MODE<2:0> X X
MUX 1 R/W 0 0 0 0 1 S MUXP<3:0> MUXN<3:0>
DATA 1 R 0 0 0 1 0 X ADC<15:0>
OFFSET CAL 1 R/W 0 0 0 1 1 X OFFSET<23:0>
GAIN CAL 1 R/W 0 0 1 0 0 X GAIN<23:0>
RESERVED 1 R/W 0 0 1 0 1 X Reserved. Do not use.
DAE DBE OP1E X X X DACA<9:8>
DACA_OP 1 R/W 0 0 1 1 0 X
DACA<7:0>
DAE DBE OP1E X X X DACB<9:8>
DACB_OP 1 R/W 0 0 1 1 1 X
DACB<7:0>
REF_SDC 1 R/W 0 1 0 0 0 X REFV<1:0> AOFF AON SDCE TSEL<2:0>
ASEC<19:4>
AL_DAY 1 R/W 0 1 0 0 1 X ASEC<3:0> X X X X
RESERVED 1 R/W 0 1 0 1 0 X Reserved. Do not use.
AWE ADE X RWE RTCE OSCE FLLE HFCE
CLK_CTRL 1 R/W 0 1 0 1 1 X CKSEL<2:0> IO32E CK32E CLKE INTP WDE
SEC<31:0>
RTC 1 R/W 0 1 1 0 0 X SUB<7:0>
PWME FSEL<2:0> SWAH SWAL SWBH SWBL
PWM_CTRL 1 R/W 0 1 1 0 1 X SPD1 SPD2 X X X X X X
PWMTH<7:0>
PWM_THTP 1 R/W 0 1 1 1 0 X PWMTP<7:0>
WATCHDOG 1W 0 1 1 1 1 X X X X X X X X X
NORM_MD 1W 1 0 0 0 0 X X X X X X X X X
SLEEP 1W 1 0 0 0 1 X X X X X X X X X
SLEEP_CFG 1 R/W 1 0 0 1 0 SLP SOSCE SCK32E SPWME SHDN X X X X
UPIO4_CTRL 1 R/W 1 0 0 1 1 X UP4MD<3:0> PUP4 SV4 ALH4 LL4
UPIO3_CTRL 1 R/W 1 0 1 0 0 X UP3MD<3:0> PUP3 SV3 ALH3 LL3
UPIO2_CTRL 1 R/W 1 0 1 0 1 X UP2MD<3:0> PUP2 SV2 ALH2 LL2
UPIO1_CTRL 1 R/W 1 0 1 1 0 X UP1MD<3:0> PUP1 SV1 ALH1 LL1
UPIO_SPI 1 R/W 1 0 1 1 1 X UP4S UP3S UP2S UP1S X X X X
SW_CTRL 1 R/W 1 1 0 0 0 X SWA SWB SPDT1<1:0> SPDT2<1:0> X X
TEMP_CTRL 1 R/W 1 1 0 0 1 X IMUX<1:0> IVAL<1:0> X X X X
RESERVED 1 R 1 1 0 1 0 X Reserved. Do not use.
MLDVD MLCPD MADO MSDC MCRDY MADD MALD X
IMSK 1 R/W 1 1 0 1 1 X MUPR<4:1> MUPF<4:1>
RESERVED 1 R/W 1 1 1 0 0 X Reserved. Do not use.
PS_VMONS 1 R/W 1 1 1 0 1 X LDOE CPE LSDE CPDE HYSE RSTE X X
RESERVED 1 R/W 1 1 1 1 0 X Reserved. Do not use.
LDVD LCPD ADOU SDC CRDY ADD ALD X
STATUS 1 R 1 1 1 1 1 X UPR<4:1> UPF<4:1>
Register Definitions
Table 4. Register Address Map
