MAX1322ECM ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input RangesELECTRICAL CHARACTERISTICS(AV = +5V, DV = +3V, AGND = DGND = 0V, V = V = +2.5V (external reference) ..
MAX1322ECM+ ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesMAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX132619-3157; Rev 4; 10/088-/4-/2-Channel, 14-Bit, Simult ..
MAX13235EETP+T ,3Mbps RS-232 Transceivers with Low-Voltage Interface, ±15kV HBM ESDApplicationsFunctional Diagrams• Telematics• GPS Systems1.62V to VCC 3.0V to 5.5V• Industrial Syste ..
MAX1324ECM ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input RangesFeaturesThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324– ♦ 8-/4-/2-Channel, 14-Bit ADCsMAX1326 14-bit, ..
MAX1324ECM+ ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesApplications♦ Internal or External ClockMultiphase Motor Control ♦ +2.5V Internal Reference or +2.0 ..
MAX1325ECM ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input Rangesfeatures include a 10MHzT/H input bandwidth, internal clock, internal (+2.5V) or♦ High Throughputex ..
MAX394CWP ,Low-Voltage, Quad, SPDT, CMOS Analog SwitchFeatures' Low On-Resistance, < 17Ω Typical (35Ω max)The MAX394 is a precision, low-voltage, quad, s ..
MAX394CWP+ ,Low-Voltage, Quad, SPDT, CMOS Analog Switch—Replaces MAX333AFeatures♦♦ Low On-Resistance, < 17Ω Typical (35Ω max)The MAX394 is a precision, low-voltage, quad, ..
MAX394EAP+ ,Low-Voltage, Quad, SPDT, CMOS Analog Switch—Replaces MAX333AELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V, ..
MAX394EPP ,Low-Voltage, Quad, SPDT, CMOS Analog SwitchMAX39419-0391; Rev 0; 5/95Low-Voltage, Quad, SPDT, CMOS Analog Switch_______________
MAX394EWP ,Low-Voltage, Quad, SPDT, CMOS Analog SwitchApplications* Contact factory for dice specifications.Test Equipment Portable Instruments ** Contac ..
MAX394EWP ,Low-Voltage, Quad, SPDT, CMOS Analog SwitchGeneral Description ________
MAX1316ECM-MAX1317ECM-MAX1318ECM-MAX1320ECM-MAX1321ECM-MAX1322ECM-MAX1324ECM-MAX1325ECM-MAX1326ECM
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input Ranges
General DescriptionThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–
MAX1326 14-bit, analog-to-digital converters (ADCs) offer
two, four, or eight independent input channels.
Independent track/hold (T/H) circuitry provides simultane-
ous sampling for each channel. The MAX1316/
MAX1317/MAX1318 have a 0 to +5V input range with
±6.0V fault-tolerant inputs. The MAX1320/MAX1321/
MAX1322 have a ±5V input range with ±16.5V fault-toler-
ant inputs. The MAX1324/MAX1325/MAX1326 have a
±10V input range with ±16.5V fault-tolerant inputs. These
ADCs convert two channels in 2µs, and up to eight chan-
nels in 3.8µs, and have an 8-channel throughput of
250ksps per channel. Other features include a 10MHz
T/H input bandwidth, internal clock, internal (+2.5V) or
external (+2.0V to +3.0V) reference, and power-
saving modes.
A 16.6MHz, 14-bit, bidirectional, parallel interface pro-
vides the conversion results and accepts digital config-
uration inputs.
These devices operate from a +4.75V to +5.25V analog
supply and a separate +2.7V to +5.25V digital supply,
and consume less than 50mA total supply current.
These devices come in a 48-pin TQFP package and oper-
ate over the extended -40°C to +85°C temperature range.
ApplicationsMultiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring and Correction
Vibration and Waveform Analysis
Features8-/4-/2-Channel, 14-Bit ADCs
±1.5 LSB INL, ±1 LSB DNL, No Missing Codes
90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dB
SNR at 100kHz InputOn-Chip T/H Circuit for Each Channel
10ns Aperture Delay
50ps Channel-to-Channel T/H MatchingFast Conversion Time
One Channel in 1.6µs
Two Channels in 1.9µs
Four Channels in 2.5µs
Eight Channels in 3.7µsHigh Throughput
526ksps/ch for One Channel
455ksps/ch for Two Channels
357ksps/ch for Four Channels
250ksps/ch for Eight ChannelsFlexible Input Ranges
0 to +5V (MAX1316/MAX1317/MAX1318)
±5V (MAX1320/MAX1321/MAX1322)
±10V (MAX1324/MAX1325/MAX1326)No Calibration Needed14-Bit, High-Speed, Parallel InterfaceInternal or External Clock+2.5V Internal Reference or +2.0V to +3.0V
External Reference+5V Analog Supply, +3V to +5V Digital Supply
46mA Analog Supply Current (typ)
1.6mA Digital Supply Current (max)
Shutdown and Power-Saving Modes48-Pin TQFP Package (7mm ✕7mm Footprint)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Ordering Information19-3157; Rev 2; 8/04
Pin Configurations and Typical Operating Circuits appear at
end of data sheet. *Future product—contact factory for availability.
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND.........................................................-0.3V to +6V
DVDDto DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, I.C. to AGND (MAX1316/MAX1317/MAX1318)...±6.0V
CH0–CH7, I.C. to AGND (MAX1320/MAX1321/MAX1322).±16.5V
CH0–CH7, I.C. to AGND (MAX1324/MAX1325/MAX1326).±16.5V
INTCLK/EXTCLKto AGND.......................-0.3V to (AVDD + 0.3V)
EOC, EOLC, WR, RD, CSto DGND.........-0.3V to (DVDD + 0.3V)
CONVST, CLK, SHDN,
ALLON to DGND..................................-0.3V to (DVDD + 0.3V)
MSV, REFMS, REF to AGND.....................-0.3V to (AVDD + 0.3V)
REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)
D0–D13 to DGND....................................-0.3V to (DVDD+ 0.3V)
Maximum Current into Any Pin Except AVDD, DVDD,
AGND, DGND...............................................................±50mA
Continuous Power Dissipation
TQFP (derate 22.7mW/°C above +70°C)...................1818mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
ues are at TA= +25°C.)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)(AVDD= +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
ues are at TA= +25°C.)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Note 1:For the MAX1316/MAX1317/MAX1318, VIN= 0 to +5V. For the MAX1320/MAX1321/MAX1322, VIN= -5V to +5V. For the
MAX1324/MAX1325/MAX1326, VIN= -10V to +10V.
Note 2:All channel performance is guaranteed by correlation to a single channel test.
Note 3:Offset nulled.
Note 4:The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:
for VCHwithin the input voltage range.
Note 5:Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK= 10MHz). See the Data
Throughputsection for more information.
Note 6:All analog inputs are driven with an FS 100kHz sine wave.
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)
Note 7:Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi-
cation is due to automatic test equipment limitations.
Note 8:Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.
Note 9:CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor
droop.
Note 10:CS-to-WRand CS-to-RDpins are internally AND together. Setup and hold times do not apply.
Note 11:Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 12:To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the ris-
ing edge of CONVST, and have a minimum clock frequency of 100kHz.
Typical Operating Characteristics(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
ypical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ypical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ypical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Detailed DescriptionThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324-
MAX1326 are 14-bit ADCs. They offer two, four, or eight
(independently selectable) input channels, each with its
own T/H circuitry. Simultaneous sampling of all active
channels preserves relative phase information, making
these devices ideal for motor control and power monitor-
ing. These devices are available with 0 to +5V, ±5V, and
±10V input ranges. The 0 to +5V devices feature ±6V
fault-tolerant inputs. The ±5V and ±10V devices feature
±16.5V fault-tolerant inputs. Two channels convert in 2µs;
all eight channels convert in 3.8µs, with a maximum 8-
channel throughput of 263ksps per channel. Internal or
external reference and internal- or external-clock capabil-
ity offer great flexibility and ease of use. A write-only con-
figuration register can mask out unused channels, and a
shutdown feature reduces power. A 16.6MHz, 14-bit, par-
allel data bus outputs the conversion result. Figure 1
shows the functional diagram of these devices.
Analog Inputs
T/HTo preserve phase information across these multichan-
nel devices, each input channel has a dedicated
T/H amplifier.
Use a low-input source impedance to minimize gain-
error harmonic distortion. The time required for the T/H
to acquire an input signal depends on the input source
impedance. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. The acquisition
time (t1) is the maximum time the device takes to
acquire the signal. Use the following formula to calcu-
late acquisition time:= 10 (RS+ RIN) x 6pF
where RIN= 2.2kΩ, RS= the input signal’s source
impedance, and t1is never less than 180ns. A source
impedance of less than 100Ωdoes not significantly
affect the ADC’s performance.
Figure 1. Functional Diagram
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input RangesTo improve the input-signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. The aperture-
delay mismatch between T/Hs of 50ps allows the relative
phase information of up to eight different inputs to be
preserved. Figure 2 shows a simplified equivalent input
circuit, illustrating the ADC’s sampling architecture.
Input BandwidthThe input tracking circuitry has a 12MHz small-signal
bandwidth, making it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Input Range and ProtectionThese devices provide ±10V, ±5V, or 0 to +5V analog
input voltage ranges. Figure 2 shows the equivalent input
circuit. Overvoltage protection circuitry at the analog
input provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
devices. This fault-protection circuit limits the current
going into or out of the device to less than 50mA, provid-
ing an added layer of protection from momentary over-
voltage or undervoltage conditions at the analog input.
Power-Saving Modes
Shutdown ModeDuring shutdown, the analog and digital circuits in the
device power down and the device draws less than
100µA from AVDD, and less than 100µA from DVDD.
Select shutdown mode using the SHDN input. Set SHDN
high to enter shutdown mode. After coming out of shut-
down, allow a 1ms wake-up time before making the first
conversion. When using an external clock, apply at least
20 clock cycles with CONVST high before making the first
conversion. When using internal-clock mode, wait at least
2µs before making the first conversion.
ALLONALLON is useful when some of the analog input channels
are selected (see theConfiguration Registersection).
Drive ALLON high to power up all input channel circuits,
regardless of whether they are selected as active by the
configuration register. Drive ALLON low or connect to
ground to power only the input channels selected as
active by the configuration register, saving 2mA per
channel (typ). The wake-up time for any channel turned
on with the configuration register is 2µs (typ) when
ALLON is low. The wake-up time with ALLON high is
only 0.01µs. New configuration-register information
does not become active until the next CONVST falling
edge. Therefore, when using software to control power
states (ALLON = 0), pulse CONVST low once before
applying the actual CONVST signal (Figure 3). With an
external clock, apply at least 15 clock cycles before
the second CONVST. If using internal-clock mode, wait
at least 1.5µs or until the first EOCbefore generating
the second CONVST.
