MAX1317ECM+ ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesELECTRICAL CHARACTERISTICS(V = +5V, V = +3V, V = V = 0, V = V = +2.5V (external reference), C = C = ..
MAX13182EELB+ ,+5.0V, ±15kV ESD-Protected, Half-Duplex/Full-Duplex, RS-485 Transceiver in µDFNApplicationsV RO H/F DE DI V RO RE DE DICC CCµDFN µDFNIndustrial Control Security SystemPin Configu ..
MAX13183EELB+ ,+5.0V, ±15kV ESD-Protected, Half-Duplex/Full-Duplex, RS-485 Transceiver in µDFNELECTRICAL CHARACTERISTICS(V = +5V ±10%, T =T to T , unless otherwise noted. Typical values are at ..
MAX1318ECM ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input RangesFeaturesThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324– ♦ 8-/4-/2-Channel, 14-Bit ADCsMAX1326 14-bit, ..
MAX1318ECM+ ,8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesFeaturesThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324– ♦ 8-/4-/2-Channel, 14-Bit ADCsMAX1326 14-bit, ..
MAX131ACQH ,3 Digit A/D Converters with Bandgap RefrenceFeatures
. Pin Compatible Upgrade for iCL7106 and ICL7136
t High Stability Bandgap Reference
..
MAX393CSE+ ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX393CUE+ ,Precision, Quad, SPST Analog SwitchesApplicationsMAX391CUE 0°C to +70°C 16 TSSOP U16-2Battery-Operated Systems Sample-and-Hold Circuit ..
MAX393ESE ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX393ESE ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX393ESE/T ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, ♦ Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX393ESE+ ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX1316ECM+-MAX1317ECM+-MAX1318ECM+-MAX1320ECM+-MAX1320ECM+T-MAX1321ECM+-MAX1322ECM+-MAX1324ECM+-MAX1325ECM+-MAX1326ECM+
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges
General DescriptionThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–
MAX1326 14-bit, analog-to-digital converters (ADCs) offer
two, four, or eight independent input channels.
Independent track/hold (T/H) circuitry provides simultane-
ous sampling for each channel. The MAX1316/
MAX1317/MAX1318 have a 0 to +5V input range with
±6.0V fault-tolerant inputs. The MAX1320/MAX1321/
MAX1322 have a ±5V input range with ±16.5V fault-toler-
ant inputs. The MAX1324/MAX1325/MAX1326 have a
±10V input range with ±16.5V fault-tolerant inputs. These
ADCs convert two channels in 2µs, and up to eight chan-
nels in 3.8µs, and have an 8-channel throughput of
250ksps per channel. Other features include a 10MHz
T/H input bandwidth, internal clock, internal (+2.5V) or
external (+2.0V to +3.0V) reference, and power-
saving modes.
A 16.6MHz, 14-bit, bidirectional, parallel interface pro-
vides the conversion results and accepts digital config-
uration inputs.
These devices operate from a +4.75V to +5.25V analog
supply and a separate +2.7V to +5.25V digital supply,
and consume less than 50mA total supply current.
These devices come in a 48-pin LQFP package and oper-
ate over the extended -40°C to +85°C temperature range.
ApplicationsMultiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring and Correction
Vibration and Waveform Analysis
Features8-/4-/2-Channel, 14-Bit ADCs
±1.5 LSB INL, ±1 LSB DNL, No Missing Codes
90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dB
SNR at 100kHz InputOn-Chip T/H Circuit for Each Channel
10ns Aperture Delay
50ps Channel-to-Channel T/H MatchingFast Conversion Time
One Channel in 1.6µs
Two Channels in 1.9µs
Four Channels in 2.5µs
Eight Channels in 3.7µsHigh Throughput
526ksps/ch for One Channel
455ksps/ch for Two Channels
357ksps/ch for Four Channels
250ksps/ch for Eight ChannelsFlexible Input Ranges
0 to +5V (MAX1316/MAX1317/MAX1318)
±5V (MAX1320/MAX1321/MAX1322)
±10V (MAX1324/MAX1325/MAX1326)No Calibration Needed14-Bit, High-Speed, Parallel InterfaceInternal or External Clock+2.5V Internal Reference or +2.0V to +3.0V
External Reference+5V Analog Supply, +3V to +5V Digital Supply
46mA Analog Supply Current (typ)
1.6mA Digital Supply Current (max)
Shutdown and Power-Saving Modes48-Pin LQFP Package (7mm x 7mm Footprint)
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Ordering Information
Selector Guide19-3157; Rev 4; 10/08
Pin Configurations and Typical Operating Circuits appear at
PARTTEMP RANGEPIN-PACKAGE
MAX1316ECM-40°C to +85°C48 LQFP
MAX1317ECM-40°C to +85°C48 LQFP
MAX1318ECM-40°C to +85°C48 LQFP
MAX1320ECM-40°C to +85°C48 LQFP
MAX1321ECM-40°C to +85°C48 LQFP
MAX1322ECM-40°C to +85°C48 LQFP
MAX1324ECM-40°C to +85°C48 LQFP
MAX1325ECM-40°C to +85°C48 LQFP
MAX1326ECM-40°C to +85°C48 LQFP
PARTINPUT RANGE (V)CHANNEL COUNTMAX1316ECM0 to +58
MAX1317ECM0 to +54
MAX1318ECM0 to +52
MAX1320ECM±58
MAX1321ECM±54
MAX1322ECM±52
MAX1324ECM±108
MAX1325ECM±104
MAX1326ECM±102
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= +5V, VDVDD= +3V, VAGND= VDGND= 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
ues are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND.........................................................-0.3V to +6V
DVDDto DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, I.C. to AGND (MAX1316/MAX1317/MAX1318)...±6.0V
CH0–CH7, I.C. to AGND (MAX1320/MAX1321/MAX1322).±16.5V
CH0–CH7, I.C. to AGND (MAX1324/MAX1325/MAX1326).±16.5V
INTCLK/EXTCLKto AGND.......................-0.3V to (AVDD + 0.3V)
EOC, EOLC, WR, RD, CSto DGND.........-0.3V to (DVDD + 0.3V)
CONVST, CLK, SHDN,
ALLON to DGND..................................-0.3V to (DVDD + 0.3V)
MSV, REFMS, REF to AGND.....................-0.3V to (AVDD + 0.3V)
REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)
D0–D13 to DGND....................................-0.3V to (DVDD+ 0.3V)
Maximum Current into Any Pin Except AVDD, DVDD,
AGND, DGND...............................................................±50mA
Continuous Power Dissipation
LQFP (derate 22.7mW/°C above +70°C)...................1818mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCE (Note 1)ResolutionN14Bits
Integral NonlinearityINL(Note 2)±0.8±2.0LSB
Differential NonlinearityDNLNo missing codes (Note 2)±0.5±1LSB
Unipolar devices±40Offset ErrorBipolar devices±40LSB
Unipolar devices-4Offset DriftBipolar devices-4ppm/°C
Unipolar devices between all channels3580Channel Offset MatchingBipolar devices between all channels2560LSB
Gain Error(Note 3)±8±40LSB
Channel Gain-Error MatchingBetween all channels25LSB
Gain Temperature Coefficient3ppm/°C
DYNAMIC PERFORMANCE (at fIN = 100kHz, -0.4dB FS)Unipolar74.576Signal-to-Noise RatioSNRBipolar7576.5dB
Unipolar74.576Signal-to-Noise and Distortion
RatioSINADBipolar7576.5dB
Spurious-Free Dynamic RangeSFDR8393dBc
Total Harmonic DistortionTHD-90-83dBc
Channel-to-Channel Isolation83dB
ANALOG INPUTS (CH0–CH7)MAX1316/MAX1317/MAX13180+5
MAX1320/MAX1321/MAX1322-5+5Input Voltage Range
MAX1324/MAX1325/MAX1326-10+10
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= +5V, VDVDD= +3V, VAGND= VDGND= 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
ues are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVIN = +5V0.540.72MAX1316/MAX1317/MAX1318VIN = 0V-0.157-0.12
VIN = +5V0.290.39MAX1320/MAX1321/MAX1322VIN = -5V-1.16-0.87
VIN = +10V0.560.74
Input Current (Note 4)
MAX1324/MAX1325/MAX1326VIN = -10V-1.13-0.85
MAX1316/MAX1317/MAX13187.58
MAX1320/MAX1321/MAX13228.66Input Resistance (Note 4)
MAX1324/MAX1325/MAX132614.26
Input Capacitance15pF
TRACK/HOLDOne channel526
Two channels455
Four channels357
External-Clock Throughput Rate
(Note 5)
Eight channels250
ksps
One channel (INTCLK/EXTCLK = AVDD)526
Two channels (INTCLK/EXTCLK = AVDD)455
Four channels (INTCLK/EXTCLK = AVDD)357
Internal-Clock Throughput Rate
(Note 5)
Eight channels (INTCLK/EXTCLK = AVDD)250
ksps
Small-Signal Bandwidth10MHz
Full-Power Bandwidth10MHz
Aperture Delay16ns
Aperture Jitter50psRMS
Aperture-Delay Matching100ps
INTERNAL REFERENCEREFMS VoltageVREFMS2.4752.5002.525V
REF VoltageVREF2.4752.5002.525V
REF Temperature Coefficient30ppm/°C
EXTERNAL REFERENCE (REFMS AND REF EXTERNALLY DRIVEN)Input Current-250+250µA
REFMS Input Voltage RangeVREFMSUnipolar devices2.02.53.0V
REF Voltage Input RangeVREF2.02.53.0V
REF Input Capacitance15pF
REFMS Input Capacitance15pF
DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, ALLON, CONVST)Input-Voltage HighVIH0.7 x
DVDDV
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= +5V, VDVDD= +3V, VAGND= VDGND= 0, VREF= VREFMS= +2.5V (external reference), CREF= CREFMS= 0.1µF, CREF+=
CREF-= 0.1µF, CREF+-to-REF-= 2.2µF || 0.1µF, CCOM= 2.2µF || 0.1µF, CMSV= 2.2µF || 0.1µF (unipolar devices, MAX1316/
MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), fCLK = 10MHz,
50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = TMINto TMAX, unless otherwise noted. Typical val-
ues are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput-Voltage LowVIL0.3 x
DVDDV
Input Hysteresis15mV
Input CapacitanceCIN15pF
Input CurrentIINVIN = 0V or DVDD±1µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)Input-Voltage High0.7 x
AVDDV
Input-Voltage Low0.3 x
AVDDV
DIGITAL OUTPUTS (D0–D13, EOC, EOLC)Output-Voltage HighVOHISOURCE = 0.8mADVDD -
0.6V
Output-Voltage LowVOLISINK = 1.6mA0.4V
Tri-State Leakage CurrentRD ≥ VIH or CS ≥ VIH0.061µA
Tri-State Output CapacitanceRD ≥ VIH or CS ≥ VIH15pF
POWER SUPPLIESAnalog-Supply VoltageAVDD4.755.25V
Digital-Supply VoltageDVDD2.705.25V
Analog-Supply CurrentIAVDDAll channels selected4656mA
Digital-Supply CurrentIDVDDCLOAD = 100pF, all channels selected
(Note 6)11.6mA
IAVDDVSHDN = DVDD, VCH = float10Shutdown Current (Note 7)IDVDDV RD = V WR = DVDD, VSHDN = DVDD0.12µA
Power-Supply Rejection RatioPSRRAVDD = +4.75V to +5.75V (Note 8)50dB
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Note 1:For the MAX1316/MAX1317/MAX1318, VIN= 0 to +5V. For the MAX1320/MAX1321/MAX1322, VIN= -5V to +5V. For the
MAX1324/MAX1325/MAX1326, VIN= -10V to +10V.
Note 2:All channel performance is guaranteed by correlation to a single channel test.
Note 3:Offset nulled.
Note 4:The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:
for VCHwithin the input voltage range.
Note 5:Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK= 10MHz). See the Data
Throughputsection for more information.
Note 6:All analog inputs are driven with an FS 100kHz sine wave.VVCHBIAS_−
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInternal clock1.61.8µs
Time-to-First-Conversion ResulttCONVExternal clock, Figure 616Clock
cycles
Internal clock0.30.36µs
Time-to-Next-Conversion ResulttNEXTExternal clock, Figure 63Clock
cycles
CONVST Pulse-Width Low
(Acquisition Time)tACQ(Note 9)0.16100µs
CS Pulse Widtht230ns
RD Pulse-Width Lowt330ns
RD Pulse-Width Hight430ns
WR Pulse-Width Lowt530ns
CS to WRt6(Note 10)ns
WR to CSt7(Note 10)ns
CS to RDt8(Note 10)ns
RD to CSt9(Note 10)ns
Data-Access Time
(RD Low to Valid Data)t1030ns
Bus-Relinquish Time (RD High)t1130ns
Internal clock80ns
EOC Pulse Widtht12External clock, Figure 61Clock
cycles
Input-Data Setup Timet1410ns
Input-Data Hold Timet1510ns
External-Clock Periodt160.0810.00µs
External-Clock High Periodt17Logic sensitive to rising edges20ns
External-Clock Low Periodt18Logic sensitive to rising edges20ns
External-Clock Frequency(Note 11)0.112.5MHz
Internal-Clock Frequency10MHz
CONVST High to CLK Edget1920(Note 12)ns
EOC Low to RDt200ns
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1316 toc01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1316 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1316 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
fSAMPLE = 250ksps
ALL 8 CHANNELS
DRIVEN WITH FULL-
SCALE SINE WAVES
ANALOG SUPPLY CURRENT
vs. TEMPERATUREMAX1316 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
fSAMPLE = 250ksps
ALL 8 CHANNELS
DRIVEN WITH FULL-
SCALE SINE WAVES
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGEMAX1316 toc05
SHUTDOWN CURRENT (
ANALOG
SHUTDOWN
CURRENT
DIGITAL
SHUTDOWN
CURRENT
SHUTDOWN CURRENT
vs. TEMPERATUREMAX1316 toc06
SHUTDOWN CURRENT (3510-15
ANALOG
SHUTDOWN
CURRENT
DIGITAL
SHUTDOWN
CURRENT
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)
Note 7:Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi-
cation is due to automatic test equipment limitations.
Note 8:Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.
Note 9:CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor
droop.
Note 10:CS-to-WRand CS-to-RDpins are internally AND together. Setup and hold times do not apply.
Note 11:Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 12:To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the ris-
ing edge of CONVST, and have a minimum clock frequency of 100kHz.
Typical Operating Characteristics(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGEMAX1316 toc07
AVDD (V)
REF
(V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1316 toc08
TEMPERATURE (°C)
REF
(V)35-1510
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1316 toc09
AVDD (V)
OFFSET ERROR (LSB)
NORMALIZED AT TA = +25°C
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
OFFSET ERROR vs. TEMPERATUREMAX1316 toc10
TEMPERATURE (°C)
OFFSET ERROR (%FSR)35-1510
NORMALIZED AT TA = +25°C
GAIN ERROR vs. SUPPLY VOLTAGEMAX1316 toc11
AVDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1316 toc12
TEMPERATURE (°C)
GAIN ERROR (%FSR)35-1510
-4085
Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
FFTMAX1316 toc13
FREQUENCY (MHz)
AMPLITUDE (dB)
fANALOG_IN = 103kHz
fSAMPLE = 490kHz
fCLK = 10MHz
SINAD = 76.7dB
SNR = 77.0dB
THD = -88.3dB
SFDR = 91.0dB
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCYMAX1316 toc14
fCLK (MHz)
SNR (dB)16141210
fIN = 100kHz
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCYMAX1316 toc15
fCLK (MHz)
SINAD (dB)16141210
fIN = 100kHz
EFFECTIVE NUMBER OF BITS
vs. CLOCK FREQUENCYMAX1316 toc16
fCLK (MHz)
ENOB (BITS)16141210820
fIN = 100kHz
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCYMAX1316 toc17
fCLK (MHz)
THD (dB)16141210820
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
MAX1316 toc17b
fCLK (MHz)
SFDR (dB)16141210820
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
OUTPUT HISTOGRAM
(DC INPUT)MAX1316 toc20
DIGITAL OUTPUT CODE
COUNTS
CONVERSION TIME
vs. TEMPERATURE
MAX1316 toc19
TEMPERATURE (°C)
CONVERSION TIME (3510-15
tNEXT
tCONVINTERNAL CLOCK
CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGEMAX1316 toc18
ANALOG SUPPLY VOLTAGE (V)
CONVERSION TIME (
tNEXT
tCONVINTERNAL CLOCK
Typical Operating Characteristics (continued)(AVDD = +5V, DVDD= +3V, AGND = DGND = 0V, VREF= VREFMS= +2.5V (external reference), see the Typical Operating Circuits sec-
tion, fCLK = 10MHz, 50% duty cycle, INTCLK/EXTCLK= AGND (external clock), SHDN = DGND, TA = +25°C, unless otherwise noted.)
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAMEFUNCTION1, 15, 171, 15, 171, 15, 17AVDD
Analog Supply Input. AVDD is the power input for the analog section
of the converter. Apply 4.75V to 5.25V to AVDD. Bypass AVDD to
AGND (pin 14 to pin 15, pin 16 to pin 17, pin 1 to pin 2) with a 0.1µF
capacitor at each AVDD input.
2, 3, 14, 16, 232, 3, 14, 16, 232, 3, 14, 16, 23AGNDAnalog Ground. AGND is the power return for AVDD. Connect all
AGNDs together.44CH0Channel 0 Analog Input55CH1Channel 1 Analog Input6MSV
Midscale Voltage Bypass. For the MAX1316/MAX1317/MAX1318,
connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the
MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326,
connect MSV directly to AGND.7—CH2Channel 2 Analog Input8—CH3Channel 3 Analog Input——CH4Channel 4 Analog Input
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAMEFUNCTION——CH5Channel 5 Analog Input——CH6Channel 6 Analog Input——CH7Channel 7 Analog Input1313INTCLK/
EXTCLK
Clock-Mode Select Input. Use INTCLK/EXTCLK to select the internal
or external conversion clock. Connect INTCLK/EXTCLK to AVDD to
select the internal clock. Connect INTCLK/EXTCLK to AGND to use
an external clock connected to CLK.1818REFMS
Midscale Reference Bypass or Input. REFMS is the bypass point for
an internally generated reference voltage. For the MAX1316/
MAX1317/MAX1318, connect a 0.1µF capacitor from REFMS to
AGND. For the MAX1320/MAX1321/MAX1322/MAX1324/
MAX1325/MAX1326, connect REFMS directly to REF and bypass
with a 0.1µF capacitor from REFMS to AGND.1919REF
ADC Reference Bypass or Input. REF is the bypass point for an
internally generated reference voltage. Bypass REF with a 0.01µF
capacitor to AGND. REF can be driven externally by a precision
external voltage reference.2020REF+
Positive Reference Bypass. REF+ is the bypass point for an
internally generated reference voltage. Bypass REF+ with a 0.1µF
capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a
0.1µF capacitor.2121COM
Reference Common Bypass. COM is the bypass point for an
internally generated reference voltage. Bypass COM to AGND with
a 2.2µF and a 0.1µF capacitor.2222REF-
Negative Reference Bypass. REF- is the bypass point for an
internally generated reference voltage. Bypass REF- with a 0.1µF
capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a
0.1µF capacitor.2424D0Digital I/O Bit 0 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.2525D1Digital I/O Bit 1 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.2626D2Digital I/O Bit 2 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAMEFUNCTION2727D3Digital I/O Bit 3 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.2828D4Digital I/O Bit 4 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.2929D5Digital I/O Bit 5 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3030D6Digital I/O Bit 6 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3131D7Digital I/O Bit 7 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3232D8Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3333D9Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3434D10Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3535D11Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3636D12Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3737D13Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.3838DVDDDigital-Supply Input. Apply +2.7V to +5.25V to DVDD. Bypass DVDD
to DGND with a 0.1µF capacitor.3939DGND
Digital-Supply GND. DGND is the power return for DVDD. Connect
DGND to AGND at only one point (see the Layout, Grounding, and
Bypassing section).4040EOCEnd-of-Conversion Output. EOC goes low to indicate the end of a
conversion. EOC returns high after one clock period.
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAMEFUNCTION4141EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end
of the last conversion. EOLC returns high when CONVST goes low
for the next conversion sequence.4242RD
Read Input. When RD and CS go low, the device initiates a read
command of the parallel data buses, D0–D13. D0–D13 are high
impedance while either RD or CS is high.4343WRWrite Input. The write command initiates when WR and CS go low. A
write command loads the configuration byte on D0–D7.4444CSChip-Select Input. Pulling CS low activates the digital interface.
D0–D13 are high impedance while either CS or RD is high.4545CONVST
Convert-Start Input. Driving CONVST high places the device in hold
mode and initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST. When CONVST is low, the
analog inputs are tracked.4646CLK
External-Clock Input. CLK accepts an external-clock signal up to
15MHz. Connect CLK to DGND for internally clocked conversions.
To select external-clock mode, set INTCLK/EXTCLK = 0.4747SHDNShutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1
for shutdown mode.4848ALLON
Enable-All-Channels Input. Drive ALLON high to enable all input
channels. When ALLON is low, only input channels selected as
active are powered. Select channels as active using the
configuration register.9–127–12I.C.Internally Connected. Connect I.C. to AGND. For factory use only.
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Detailed DescriptionThe MAX1316–MAX1318/MAX1320–MAX1322/MAX1324-
MAX1326 are 14-bit ADCs. They offer two, four, or eight
(independently selectable) input channels, each with its
own T/H circuitry. Simultaneous sampling of all active
channels preserves relative phase information, making
these devices ideal for motor control and power monitor-
ing. These devices are available with 0 to +5V, ±5V, and
±10V input ranges. The 0 to +5V devices feature ±6V
fault-tolerant inputs. The ±5V and ±10V devices feature
±16.5V fault-tolerant inputs. Two channels convert in 2µs;
all eight channels convert in 3.8µs, with a maximum 8-
channel throughput of 263ksps per channel. Internal or
external reference and internal- or external-clock capabil-
ity offer great flexibility and ease of use. A write-only con-
figuration register can mask out unused channels, and a
shutdown feature reduces power. A 16.6MHz, 14-bit, par-
allel data bus outputs the conversion result. Figure 1
shows the functional diagram of these devices.
Analog Inputs
T/HTo preserve phase information across these multichan-
nel devices, each input channel has a dedicated
T/H amplifier.
Use a low-input source impedance to minimize gain-
error harmonic distortion. The time required for the T/H
to acquire an input signal depends on the input source
impedance. If the input signal’s source impedance is
high, the acquisition time lengthens and more time
must be allowed between conversions. The acquisition
time (t1) is the maximum time the device takes to
acquire the signal. Use the following formula to calcu-
late acquisition time:= 10 (RS+ RIN) x 6pF
where RIN= 2.2kΩ, RS= the input signal’s source
impedance, and t1is never less than 180ns. A source
impedance of less than 100Ωdoes not significantly
affect the ADC’s performance.
Figure 1. Functional Diagram
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
CONVST
D13
MSV
DGND
AVDD
SHDN
CLK
CH0
INTERFACE
AND
CONTROL
8 x 1
MUX
14-BIT
ADC
CH7D0
DVDD
AGND
ALLON
REFMS
REF
REF+
COM
REF-
S/H
S/H
8 x 14
SRAM
OUTPUT
DRIVERS
5kΩ
5kΩ
CONFIGURATION
REGISTER
2.500V
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
INTCLK/EXTCLK
EOC
EOLC
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input RangesTo improve the input-signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. The aperture-
delay mismatch between T/Hs of 50ps allows the relative
phase information of up to eight different inputs to be
preserved. Figure 2 shows a simplified equivalent input
circuit, illustrating the ADC’s sampling architecture.
Input BandwidthThe input tracking circuitry has a 12MHz small-signal
bandwidth, making it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Input Range and ProtectionThese devices provide ±10V, ±5V, or 0 to +5V analog
input voltage ranges. Figure 2 shows the equivalent input
circuit. Overvoltage protection circuitry at the analog
input provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
devices. This fault-protection circuit limits the current
going into or out of the device to less than 50mA, provid-
ing an added layer of protection from momentary over-
voltage or undervoltage conditions at the analog input.
Power-Saving Modes
Shutdown ModeDuring shutdown, the analog and digital circuits in the
device power down and the device draws less than
100µA from AVDD, and less than 100µA from DVDD.
Select shutdown mode using the SHDN input. Set SHDN
high to enter shutdown mode. After coming out of shut-
down, allow a 1ms wake-up time before making the first
conversion. When using an external clock, apply at least
20 clock cycles with CONVST high before making the first
conversion. When using internal-clock mode, wait at least
2µs before making the first conversion.
ALLONALLON is useful when some of the analog input channels
are selected (see theConfiguration Registersection).
Drive ALLON high to power up all input channel circuits,
regardless of whether they are selected as active by the
configuration register. Drive ALLON low or connect to
ground to power only the input channels selected as
active by the configuration register, saving 2mA per
channel (typ). The wake-up time for any channel turned
on with the configuration register is 2µs (typ) when
ALLON is low. The wake-up time with ALLON high is
only 0.01µs. New configuration-register information
does not become active until the next CONVST falling
edge. Therefore, when using software to control power
states (ALLON = 0), pulse CONVST low once before
applying the actual CONVST signal (Figure 3). With an
external clock, apply at least 15 clock cycles before
the second CONVST. If using internal-clock mode, wait
at least 1.5µs or until the first EOCbefore generating
the second CONVST.
CH_
VBIAS
CPAR
1pF
5pF
MAX1316–MAX1318
MAX1320–MAX1322
MAX1324–MAX1326
INPUT RANGE (V)0 TO +5
±10
R1 (kΩ) R2 (kΩ)
VBIAS (V)
Table 1. Conversion Times Using the
Internal Clock
NUMBER OF CHANNELSINTERNAL-CLOCK
CONVERSION TIME1.61.92.22.52.83.13.43.7
