MAX13103EETL+T ,16-Channel Buffered CMOS Logic-Level TranslatorsApplications *EXPOSED PAD CONNECTED TO GROUNDTQFNCMOS Logic-Level PDAsPin Configurations continued ..
MAX1310ECM ,8-/4-/2-Channel / 12-Bit / Simultaneous-Sampling ADCs with 10V / 5V / and 0 to +5V Analog Input RangesELECTRICAL CHARACTERISTICS(AV = +5V, DV = +3V, AGND = DGND = 0, V = V = +2.5V (external reference), ..
MAX1310ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Rangesfeatures include a 20MHz T/H • 1075ksps/Channel for One Channel input bandwidth, internal clock, in ..
MAX1312ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesFeatures● Up to Eight Channels of Simultaneous Sampling The MAX1304–MAX1306/MAX1308–MAX1310/MAX1312 ..
MAX1313ECM ,8-/4-/2-Channel / 12-Bit / Simultaneous-Sampling ADCs with 10V / 5V / and 0 to +5V Analog Input RangesMAX1304–MAX1306/MAX1308–MAX1310/MAX1312–MAX131419-3052; Rev 3; 8/048-/4-/2-Channel, 12-Bit, Simulta ..
MAX1313ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesEVALUATION KIT AVAILABLEMAX1304–MAX1306 8-/4-/2-Channel, 12-Bit, Simultaneous- MAX1308–MAX1310 Samp ..
MAX392ESE ,Precision / Quad / SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX392ESE+ ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX392ESE+T ,Precision, Quad, SPST Analog SwitchesMAX391/MAX392/MAX393Precision, Quad, SPST Analog Switches_______________
MAX392EUE ,Precision / Quad / SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX392EUE+ ,Precision, Quad, SPST Analog SwitchesGeneral Description ________
MAX392MJE ,Precision / Quad / SPST Analog SwitchesMAX391/MAX392/MAX39319-0236; Rev 1; 6/99Precision, Quad, SPST Analog Switches
MAX13103EETL+T
16-Channel Buffered CMOS Logic-Level Translators
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
General DescriptionThe MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-bit bidirectional CMOS logic-level translators pro-
vide the level shifting necessary to allow data transfer in
multivoltage systems. These devices are inherently
bidirectional due to their design and do not require the
use of a direction input. Externally applied voltages,
VCCand VL, set the logic levels on either side of the
devices. Logic signals present on the VL side of the
device appear as a higher voltage logic signal on the
VCCside of the device, and vice-versa.
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when low, reduces the VCCandsupply currents to less than 2µA. The MAX13108E
features a multiplexing input (MULT) that selects one
byte between the two, thus allowing multiplexing of the
signals. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E have ±15kV ESD protection on the I/O VCC
side for greater protection in applications that route sig-
nals externally. Three different output configurations are
available during shutdown, allowing the I/O on the VCC
side or the VLside to be put in a high-impedance state
or pulled to ground through an internal 6kΩresistor.
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
accept VCCvoltages from +1.65V to +5.5V and VL
voltages from +1.2V to VCC, making them ideal for data
transfer between low-voltage ASICs/PLDs and higher
voltage systems. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E are available in 36-bump
WLP and 40-pin TQFN packages, and operate over the
extended -40°C to +85°C temperature range. See the
Ordering Information.
Applications
FeaturesWide Supply Voltage Range
VCCRange of 1.65V to 5.5VRange of 1.2V to VCCESD Protection on I/O VCCLines
±15kV Human Body ModelUp to 20Mbps ThroughputLow 0.03µA Typical Quiescent CurrentWLP and TQFN Packages
Pin Configurations
Ordering Information/Selector Guide continued at end of data sheet.
Ordering Information/Selector Guide
PARTPIN-PACKAGEDATA
RATE (Mbps)
I/O VL STATE
DURING SHUTDOWN
I/O VCC STATE
DURING SHUTDOWN
MULTIPLEXER
FEATUREMAX13101EETL+40 TQFN-EP*
5mm x 5mm x 0.8mm20High impedance6kΩ to GNDNo
Note:All devices are specified over the -40°C to +85°C operating temperature range.
MAX13101E
MAX13102E
MAX13103E
TQFNTOP VIEW OF BOTTOM LEADS43
I/O VL14
I/O VL16
VCC
I/O VCC16
I/O VL13
I/O VL3
I/O VL1
I/O VL4
VCC
I/O VCC1
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O VL15I/O VL213
I/O V
L10
I/O V
*EXPOSED PAD CONNECTED TO GROUND
I/O V
L11
I/O V
L12
I/O V
GND10
I/O V
I/O V
I/O V
I/O V
GND252728242322212930
I/O VCC15
I/O VCC14
I/O VCC13
I/O VCC2
I/O VCC3
I/O VCC4
GND
*EP
CMOS Logic-Level
Translation
Portable Equipment
Cell Phones
PDAs
Digital Still Cameras
Smart Phones
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configurations continued at end of data sheet.
Typical Operating Circuit appears at end of data sheet.
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), = TMINto TMAX, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC...........................................................................-0.3V to +6V
VL...........................................................................................-0.3V to +6V
I/O VCC_......................................................-0.3V to (VCC+ 0.3V)
I/O VL_.....................................................................-0.3V to (VL+ 0.3V)
EN, MULT.................................................................-0.3V to +6V
Short-Circuit Duration I/O VL_, I/O VCC_to GND.......Continuous
Continuous Power Dissipation (TA= +70°C)
36-Bump WLP (derate 17.0mW/°C above +70°C).....1361mW
40-Pin TQFN (derate 35.7mW/°C above +70°C).......2857mW
Operating Temperature Range...........................-40°C to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIESVL Supply RangeVL1.2VCCV
VCC Supply RangeVCC1.655.50V
Supply Current from VCCIQVCC
I/O VCC_ = GND, I/O VL _ = GND
or I/O VCC_ = VCC, I/O VL _ = VL,
EN = VL, MULT = GND or VL
0.0310µA
Supply Current from VLIQVL
I/O VCC_ = GND, I/O VL _ = GND
or I/O VCC_ = VCC, I/O VL _ = VL,
EN = VL, MULT = GND or VL
0.0320µA
VCC Shutdown Supply CurrentISHDN-VCC
TA = +25°C, EN = GND, I/O VCC_ = GND,
I/O VL _ = GND,
MAX13101E/MAX13102E/MAX13103E
0.031µA
VL Shutdown Supply CurrentISHDN-VL
TA = +25°C, EN = GND, I/O VCC_ = GND,
I/O VL _ = GND,
MAX13101E/MAX13102E/MAX13103E
0.032µA
TA = +25°C, EN = GND,
MAX13102E/MAX13103E0.021
I/O VCC_ Tri-State Output
Leakage CurrentTA = + 25°C , M U LT = GN D (I/O V C C 1 - I/O V C C 8)
or M U LT = VL ( I/O VC C 9 - I/O V C C 16)AX13108E
TA = +25°C, EN = GND, MAX13101E/
MAX13103E0.021
I/O VL _ Tri-State Output Leakage
CurrentTA = +25°C, MULT = GND (I/O VL1 - I/O
VL8) or MULT = VL (I/OVL9 - I/O VL16)
MAX13108E
I/O VL _ Pulldown Resistance
During ShutdownEN = GND, MAX13102E410kΩ
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
ELECTRICAL CHARACTERISTICS (continued)(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), = TMINto TMAX, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSI/O VCC_ Pulldown Resistance
During ShutdownEN = GND, MAX13101E410kΩ
EN or MULT Input Leakage
CurrentTA = +25°C1µA
LOGIC-LEVEL THRESHOLDSI/O VL _ Input-Voltage High
ThresholdVIHL2/3 xV
I/O VL _ Input-Voltage Low
ThresholdVILL1/3 xV
I/O VCC_ Input-Voltage High
ThresholdVIHC2/3 x
VCCV
I/O VCC_ Input-Voltage Low
ThresholdVILC1/3 x
VCCV
EN, MULT Input-Voltage High
ThresholdVIH-SHDNVL - 0.4V
EN, MULT Input-Voltage Low
ThresholdVIL-SHDN0.4V
I/O VL _ Output-Voltage HighVOHLI/O V L _ sour ce cur r ent = 20µA, I/O V C C _ ≥ V IH C VL - 0.4V
I/O VL _ Output-Voltage LowVOLLI/O VL _ sink current = 20µA, I/O VCC_ ≤ VILC0.4V
I/O VCC_ Output-Voltage HighVOHCI/O V C C _ sour ce cur r ent = 20µA, I/O V L _ ≥ V IH L V C C - 0.4V
I/O VCC_ Output-Voltage LowVOLCI/O VCC_ sink current = 20µA, I/O VL _ ≤ VILL0.4V
RISE/FALL-TIME ACCELERATOR STAGEI/O VCC sideVCC / 2Transition-Detect ThresholdI/O VL sideVL / 2V
Accelerator Pulse DurationVL = 1.2V, VCC = 1.65V20ns
VL = 1.2V, VCC = 1.65V60I/O VL _ Output-Accelerator Sink
ImpedanceVL = 5V, VCC = 5V5 Ω
VL = 1.2V, VCC = 1.65V15I/O VCC_ Output-Accelerator Sink
ImpedanceVL = 5V, VCC = 5V5Ω
VL = 1.2V, VCC = 1.65V30I/O VL _ Output-Accelerator
Source ImpedanceVL = 5V, VCC = 5V5Ω
VL = 1.2V, VCC = 1.65V20I/O VCC_ Output-Accelerator
Source ImpedanceVL = 5V, VCC = 5V7Ω
ESD PROTECTIONI/O VCC_Human Body Model±15kV
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
TIMING CHARACTERISTICS(VCC= +1.65V to +5.5V, VL= +1.2V to VCC, EN = VL(MAX13101E/MAX13102E/MAX13103E), MULT = VLor GND (MAX13108E), = TMINto TMAX, unless otherwise noted. Typical values are at VCC= +1.65V, VL= +1.2V, TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSI/O VL _ Rise TimetRVLRS = 50Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)15ns
I/O VL _ Fall TimetFVLRS = 50Ω, CI/OVL_ = 15pF, tFALL ≤ 3ns,
(Figures 2a, 2b)15ns
I/O VCC_ Rise TimetRVCCRS = 50Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)15ns
I/O VCC_ Fall TimetFVCCRS = 50Ω, CI/OVCC_ = 50pF, tFALL ≤ 3ns,
(Figures 1a, 1b)15ns
Propagation Delay
(Driving I/O VL _)tPVL-VCCRS = 50Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)20ns
Propagation Delay
(Driving I/O VCC_)tPVCC-VLRS = 50Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)20ns
Channel-to-Channel SkewtSKEWRS = 50Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE ≤ 3ns5ns
Part-to-Part SkewtPPSKEWRS = 50Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE ≤ 3ns, ΔTA = +20°C (Notes 3, 4)10ns
Propagation Delay from
I/O VL _ to I/O VCC_ After ENtEN-VCCCI/OVCC_ = 50pF (Figure 3)1µs
Propagation Delay from
I/O VCC_ to I/O VL _ After ENtEN-VLCI/OVL_ = 15pF (Figure 4)1µs
Maximum Data RateRSOURCE = 50Ω, CI/OVCC_ = 50pF,
CI/OVL_ = 15pF, tRISE ≤ 3ns20Mbps
Note 1:All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2:For normal operation, ensure that VL< (VCC+ 0.3V). During power-up, VL> (VCC+ 0.3V) does not damage the device.
Note 3:VCCfrom device 1 must equal VCCof device 2. VLfrom device 1 must equal VLof device 2.
Note 4:Guaranteed by design, not production tested.
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translatorsest Circuits/Timing DiagramsMAX13101E
MAX13102E
MAX13103E
MAX13108E
SOURCERS
6kΩ
6kΩ
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND
I/O VL_
EN/(MULT)
VCC
I/O VCC_
CI/OVCC_
( ) ARE FOR THE MAX13108E
tPHL
tPLH
50%
90%
10%
I/O VCC_
I/O VL_
90%
50%
10%
90%
50%
10%
tRISE/FALL ≤ 3ns
tFVCC
tPVL-VCC = tPHL or tPLH
tRVCC
SOURCE
I/O VL_
EN/(MULT)
VCC
I/O VCC_CI/OVL_
MAX13101E
MAX13102E
MAX13103E
MAX13108E
6kΩ
6kΩ
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND
( ) ARE FOR THE MAX13108E
tPHL
tPLH
I/O VL_
I/O VCC_
90%
50%
10%
90%
50%
10%
50%
90%
10%
tRISE/FALL ≤ 3ns
tFVLtRVL
tPVCC-VL = tPHL or tPLH
Figure 1a. Driving I/O VL_Figure 1b. Timing for Driving I/O VL_
Figure 2a. Driving I/O VCC_Figure 2b. Timing for Driving I/O VCC_
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translatorsest Circuits/Timing Diagrams (continued)SOURCE
I/O VCC_
100kΩ
I/O VL_
CI/OVCC
EN/(MULT)
I/O VL_
I/O VCC_
tEN-VCC
VCC
VCC
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
( ) ARE FOR THE MAX13108E
6kΩ
6kΩ
Figure 3. Propagation Delay from I/O VL_to I/O VCC_After EN
I/O VCC_
I/O VL_
CI/OVL100kΩ
VCC
EN/(MULT)
I/O VL_
I/O VCC_
tEN-VL
VCC
SOURCE
MAX13101E
MAX13102E
MAX13103E
MAX13108E
EN/(MULT)
( ) ARE FOR THE MAX13108E
6kΩ
6kΩ
Figure 4. Propagation Delay from I/O VCC_to I/O VL_After EN
VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
(DRIVING I/0 VL_, VL = 1.8V)VCC SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
MAX13101-3/8E toc01
DRIVING ONE I/O VL
FIGURE 1a
CI/OVCC_ = 15pF
VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING I/0 VCC_, VCC = 5.5V)VL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
DRIVING ONE I/O VCC
FIGURE 2a
CI/OVL_ = 15pF
MAX13101-3/8E toc02
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING I/0 VCC_, VCC = 5.5V)VL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
MAX13101-3/8 toc04
DRIVING ONE I/O VCC
FIGURE 2a
CI/OVL_ = 15pF
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
(DRIVING I/0 VL_, VL = 1.8V)VCC SUPPLY VOLTAGE (V)
CC
SUPPLY CURRENT (
MAX13101-3/8 toc03
DRIVING ONE I/O VL
FIGURE 1a
CI/OVCC_ = 15pF
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC_)TEMPERATURE (°C)
L SUPPLY CURRENT (
MAX13101-3/8E toc05
DRIVING ONE I/O VCC
FIGURE 2a
CI/OVL_ = 15pF
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC_)TEMPERATURE (°C)
SUPPLY CURRENT (
MAX13101-3/8 toc06
DRIVING ONE I/O VCC
FIGURE 2a
CI/OVL_ = 15pF
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Typical Operating Characteristics(VCC= 3.3V, VL= 1.8V, data rate = 20Mbps, TA = +25°C, unless otherwise noted.)
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
RISE/FALL TIME vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
MAX13101-3/8E toc1020304050
tFVLtRVL
FIGURES 2a, 2b
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O VCC_ (DRIVING I/O VL_)CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
MAX13101-3/8E toc1120304050
tPLH
tPHL
FIGURES 1a, 1b
VL SUPPLY CURRENT vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)CAPACITIVE LOAD (pF)
L SUPPLY CURRENT (
MAX13101-3/8E toc0720304050
DRIVING ONE I/O VCC
FIGURE 2a
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD
ON I/O VCC_ (DRIVING I/O VL_)CAPACITIVE LOAD (pF)
SUPPLY CURRENT (
MAX13101-3/8E toc0820304050
DRIVING ONE I/O VL
FIGURE 1a
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VCC_ (DRIVING I/O VL_)CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
MAX13101-3/8E toc0920304050
tRVCC
tFVCC
FIGURES 1a, 1b
Typical Operating Characteristics (continued)(VCC= 3.3V, VL= 1.8V, datarate = 20Mbps, TA = +25°C, unless otherwise noted.)
MAX13101E/MAX13102E/
MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Pin Description—MAX13101E/MAX13102E/MAX13103E
PIN
TQFNWLPNAMEFUNCTION1, 21, 30D6GNDGroundC2I/O VL5Input/Output 5. Referenced to VL.A3I/O VL6Input/Output 6. Referenced to VL.B3I/O VL7Input/Output 7. Referenced to VL.C3I/O VL8Input/Output 8. Referenced to VL.A4I/O VL9Input/Output 9. Referenced to VL.B4I/O VL10Input/Output 10. Referenced to VL.C4I/O VL11Input/Output 11. Referenced to VL.A5I/O VL12Input/Output 12. Referenced to VL.C6ENGlobal Enable Input. Pull EN low for shutdown. Drive EN to VCC or VL for normal operation.B5I/O VL13Input/Output 13. Referenced to VL.C5I/O VL14Input/Output 14. Referenced to VL.A6I/O VL15Input/Output 15. Referenced to VL.B6I/O VL16Input/Output 16. Referenced to VL.
15, 36A1VLLogic Supply Voltage, +1.2V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor.
16, 35F1VCC
VCC Supply Voltage, +1.65V ≤ VCC ≤ +5.5V. Bypass VCC to GND with a 0.1µF capacitor.
For full ESD protection, connect a 1.0µF capacitor from VCC to GND, located as close to the
VCC input as possible.E6I/O VCC16Input/Output 16. Referenced to VCC.F6I/O VCC15Input/Output 15. Referenced to VCC.
RAIL-TO-RAIL DRIVING (DRIVING I/O VL)10ns/div
MAX13101E-3/8E toc13
I/0 VL_
1V/div
I/0 VCC_
2V/div
GND
GND
CI/OVCC_= 50pF
Typical Operating Characteristics (continued)(VCC= 3.3V, VL= 1.8V, datarate = 20Mbps, TA = +25°C, unless otherwise noted.)
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
MAX13101-3/8E toc1220304050
tPHL
tPLH
FIGURES 2a, 2b
