MAX1308ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesElectrical Characteristics(V = +5V, V = +3V, V = V = 0V, V = V = +2.5V (external reference), C = C ..
MAX1308ECM-T ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Rangesfeatures include a 20MHz T/H • 1075ksps/Channel for One Channel input bandwidth, internal clock, in ..
MAX1309ECM ,8-/4-/2-Channel / 12-Bit / Simultaneous-Sampling ADCs with 10V / 5V / and 0 to +5V Analog Input Rangesfeatures include a 20MHz T/HEight Channels in 1.98µsinput bandwidth, internal clock, internal (+2.5 ..
MAX1309ECM+ ,8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input RangesEVALUATION KIT AVAILABLEMAX1304–MAX1306 8-/4-/2-Channel, 12-Bit, Simultaneous- MAX1308–MAX1310 Samp ..
MAX130ACPL ,3 Digit A/D Converters with Bandgap RefrenceGeneral Description
The MAX130 and MAX131 are 3% digit A/D converters
with onboard LCD display ..
MAX130ACPL+ ,3 1/2 Digit ADC with Bandgap ReferenceELECTRICAL CHARACTERISTICS (MAX130, MAX130A)
nal muons or the smem-non 75 nor
mmmns CONDITION ..
MAX391MJE ,Precision / Quad / SPST Analog SwitchesApplicationsMAX391CUE 0°C to +70°C 16 TSSOPMAX391C/D 0°C to +70°C Dice*Battery-Operated Systems Sam ..
MAX392CPE ,Precision / Quad / SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX392CPE+ ,Precision, Quad, SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, ♦ Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX392CSE ,Precision / Quad / SPST Analog SwitchesFeaturesThe MAX391/MAX392/MAX393 are precision, quad, Low On-Resistance, 20Ω Typicalsingle-pole/s ..
MAX392CSE ,Precision / Quad / SPST Analog SwitchesApplicationsMAX391CUE 0°C to +70°C 16 TSSOPMAX391C/D 0°C to +70°C Dice*Battery-Operated Systems Sam ..
MAX392CSE+ ,Precision, Quad, SPST Analog SwitchesELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = 2.4V, V = 0.8V ..
MAX1304ECM+-MAX1305ECM+-MAX1308ECM+-MAX1308ECM-T-MAX1309ECM+-MAX1310ECM+-MAX1312ECM+-MAX1313ECM+
8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V, and 0 to +5V Analog Input Ranges
General DescriptionThe MAX1304–MAX1306/MAX1308–MAX1310/MAX1312
–MAX1314 12-bit, analog-to-digital converters (ADCs)
offer eight, four, or two independent input channels.
Independent track-and-hold (T/H) circuitry provides simul-
taneous sampling for each channel. The MAX1304/
MAX1305/MAX1306 provide a 0 to +5V input range
with ±6V fault-tolerant inputs. The MAX1308/MAX1309/
MAX1310 provide a ±5V input range with ±16.5V fault-
tolerant inputs. The MAX1312/MAX1313/MAX1314 have
a ±10V input range with ±16.5V fault-tolerant inputs. These ADCs convert two channels in 0.9μs, and up to eight channels in 1.98μs, with an 8-channel throughput of
456ksps per channel. Other features include a 20MHz T/H
input bandwidth, internal clock, internal (+2.5V) or external
(+2.0V to +3.0V) reference, and power-saving modes.
A 20MHz, 12-bit, bidirectional parallel data bus provides
the conversion results and accepts digital inputs that acti-
vate each channel individually.
All devices operate from a +4.75V to +5.25V analog sup-
ply and a +2.7V to +5.25V digital supply and consume
57mA total supply current when fully operational.
Each device is available in a 48-pin 7mm x 7mm LQFP
package and operates over the extended -40°C to +85°C
temperature range.
Applications●SIN/COS Position Encoder●Multiphase Motor Control●Multiphase Power Monitoring●Power-Grid Synchronization●Power-Factor Monitoring●Vibration and Waveform Analysis
Features●Up to Eight Channels of Simultaneous Sampling 8ns Aperture Delay 100ps Channel-to-Channel T/H Match●Extended Input Ranges 0 to +5V (MAX1304/MAX1305/MAX1306) -5V to +5V (MAX1308/MAX1309/MAX1310) -10V to +10V (MAX1312/MAX1313/MAX1314)●Fast Conversion Time • One Channel in 0.72μs • Two Channels in 0.9μs • Four Channels in 1.26μs • Eight Channels in 1.98μs●High Throughput 1075ksps/Channel for One Channel 901ksps/Channel for Two Channels 680ksps/Channel for Four Channels 456ksps/Channel for Eight Channels●±1 LSB INL, ±0.9 LSB DNL (max)●84dBc SFDR, -86dBc THD, 71dB SINAD,
fIN = 500kHz at 0.4dBFS●12-Bit, 20MHz, Parallel Interface●Internal or External Clock●+2.5V Internal Reference or +2.0V to +3.0V
External Reference●+5V Analog Supply, +3V to +5V Digital Supply 55mA Analog Supply Current 1.3mA Digital Supply Current Shutdown and Power-Saving Modes●48-Pin LQFP Package (7mm x 7mm Footprint)
Pin Configurations appear at end of data sheet.+Denotes lead(Pb)-free/RoHS-compliant package.
PARTTEMP RANGEPIN-PACKAGE
MAX1304ECM+-40°C to +85°C48 LQFP
MAX1305ECM+-40°C to +85°C48 LQFP
MAX1306ECM+-40°C to +85°C48 LQFP
MAX1308ECM+-40°C to +85°C48 LQFP
MAX1309ECM+-40°C to +85°C48 LQFP
MAX1310ECM+-40°C to +85°C48 LQFP
MAX1312ECM+-40°C to +85°C48 LQFP
MAX1313ECM+-40°C to +85°C48 LQFP
MAX1314ECM+-40°C to +85°C48 LQFP
PARTINPUT RANGE (V)CHANNEL COUNTMAX1304ECM0 to +58
MAX1305ECM0 to +54
MAX1306ECM0 to +52
MAX1308ECM±58
MAX1309ECM±54
MAX1310ECM±52
MAX1312ECM±108
MAX1313ECM±104
MAX1314ECM±102
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Ordering Information
Selector Guide
EVALUATION KIT AVAILABLE
AVDD to AGND.........................................................-0.3V to +6V
DVDD to DGND........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, I.C. to AGND (MAX1304/MAX1305/MAX1306)........±6V
CH0–CH7, I.C. to AGND (MAX1308/MAX1309/MAX1310)...±16.5V
CH0–CH7, I.C. to AGND (MAX1312/MAX1313/MAX1314)..±16.5V
D0–D11 to DGND..................................-0.3V to (VDVDD + 0.3V)
EOC, EOLC, RD, WR, CS to DGND......-0.3V to (VDVDD + 0.3V)
CONVST, CLK, SHDN, CHSHDN to DGND -0.3V to (VDVDD + 0.3V)
INTCLK/EXTCLK to AGND .....................-0.3V to (VAVDD + 0.3V)
REFMS, REF, MSV to AGND ...................-0.3V to (VAVDD + 0.3V)
REF+, COM, REF- to AGND ...................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin Except AVDD, DVDD, AGND,
DGND................. ...........................................................±50mA
Continuous Power Dissipation (TA = +70°C)
LQFP (derate 22.7mW/°C above +70°C).................1818.2mW
Operating Temperature Range...............................-40°C to +85°C
Junction Temperature.........................................................+150°C
Storage Temperature Range ................................-65°C to +150°C
Lead Temperature (soldering, 10s)....................................+300°C
Soldering Temperature (reflow)..........................................+260°C
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF, CREF+
= CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV = AGND
(bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
STATIC PERFORMANCE (Note 1)ResolutionN12Bits
Integral NonlinearityINL(Note 2)±0.5±1.0LSB
Differential NonlinearityDNLNo missing codes (Note 2)±0.3±0.9LSB
Offset ErrorUnipolar, 0x000 to 0x001±3±16LSB
Bipolar, 0xFFF to 0x000±3±16
Offset-Error MatchingUnipolar, between all channels±9±20LSBBipolar, between all channels±9±20
Offset-Error Temperature DriftUnipolar, 0x000 to 0x0017ppm/°CBipolar, 0xFFF to 0x0007
Gain Error±2±16LSB
Gain-Error MatchingBetween all channels±3±14LSB
Gain-Error Temperature Drift4ppm/°C
DYNAMIC PERFORMANCE at fIN = 500kHz, AIN = -0.4dBFS (Note 2)Signal-to-Noise RatioSNR6871dB
Signal-to-Noise Plus DistortionSINAD6871dB
Total Harmonic DistortionTHD-86-80dBc
Spurious-Free Dynamic RangeSFDR84dBc
Channel-to-Channel Isolation8086dB
ANALOG INPUTS (CH0 through CH7)Input VoltageVCH
MAX1304/MAX1305/MAX13060+5MAX1308/MAX1309/MAX1310-5+5
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF, CREF+
= CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV = AGND
(bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput Resistance
(Note 3)RCH
MAX1304/MAX1305/MAX13067.58MAX1308/MAX1309/MAX13108.66
MAX1312/MAX1313/MAX131414.26
Input Current
(Note 3)ICH
MAX1304/MAX1305/MAX1306VCH = +5V0.540.72
VCH = 0V-0.157-0.12
MAX1308/MAX1309/MAX1310VCH = +5V0.290.39
VCH = -5V-1.16-0.87
MAX1312/MAX1313/MAX1314VCH = +10V0.560.74
VCH = -10V-1.13-0.85
Input CapacitanceCCH15pF
TRACK/HOLDExternal-Clock Throughput Rate
(Note 4)fTH
One channel selected for conversion1075
kspsTwo channels selected for conversion901
Four channels selected for conversion680
Eight channels selected for conversion456
Internal-Clock Throughput Rate
(Note 4, Table 1)fTH
One channel selected for conversion983
kspsTwo channels selected for conversion821
Four channels selected for conversion618
Eight channels selected for conversion413
Small-Signal Bandwidth20MHz
Full-Power Bandwidth20MHz
Aperture DelaytAD8ns
Aperture-Delay Matching100ps
Aperture JittertAJ50psRMS
INTERNAL REFERENCEREF Output VoltageVREF2.4752.5002.525V
Reference Output-Voltage
Temperature Drift30ppm/°C
REFMS Output VoltageVREFMS2.4752.5002.525V
REF+ Output VoltageVREF+3.850V
COM Output VoltageVCOM2.600V
REF- Output VoltageVREF-1.350V
Differential Reference VoltageVREF+ -
VREF-2.500V
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Electrical Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF, CREF+
= CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV = AGND
(bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCE (REF and REFMS are externally driven)REF Input Voltage RangeVREF2.02.53.0V
REF Input ResistanceRREF(Note 5)5kΩ
REF Input Capacitance15pF
REFMS Input Voltage RangeVREFMS2.02.53.0V
REFMS Input ResistanceRREFMS(Note 6)5kΩ
REFMS Input Capacitance15pF
REF+ Output VoltageVREF+VREF = +2.5V3.850V
COM Output VoltageVCOMVREF = +2.5V2.600V
REF- Output VoltageVREF-VREF = +2.5V1.350V
Differential Reference
Voltage
VREF+ -
VREF-VREF = +2.5V2.500V
DIGITAL INPUTS (D0–D7, RD, WR, CS, CLK, SHDN, CHSHDN, CONVST)Input-Voltage HighVIH0.7 x VDVDDV
Input-Voltage LowVIL0.3 x VDVDDV
Input Hysteresis20mV
Input CapacitanceCIN15pF
Input CurrentIINVIN = 0V or VDVDD0.02±1µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)Input-Voltage HighVIH0.7 x VAVDDV
Input-Voltage LowVIL0.3 x VAVDDV
DIGITAL OUTPUTS (D0–D11, EOC, EOLC)Output-Voltage HighVOHISOURCE = 0.8mA, Figure 1VDVDD - 0.6V
Output-Voltage LowVOLISINK = 1.6mA, Figure 10.4V
D0–D11 Tri-State Leakage
CurrentRD = high or CS = high0.061µA
D0–D11 Tri-State Output
CapacitanceRD = high or CS = high15pF
POWER SUPPLIESAnalog Supply Voltage AVDD4.755.25V
Digital Supply VoltageDVDD2.705.25V
Analog Supply CurrentIAVDD
MAX1304/MAX1305/MAX1306,
all channels selected5560MAX1308/MAX1309/MAX1310,
all channels selected5460
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Electrical Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF, CREF+
= CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV = AGND
(bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDigital Supply Current
(CLOAD = 100pF) (Note 7)IDVDD
MAX1304/MAX1305/MAX1306,
all channels selected1.32.6MAX1308/MAX1309/MAX1310,
all channels selected1.32.6
MAX1312/MAX1313/MAX1314,
all channels selected1.32.6
Shutdown Current
(Note 8)
IAVDD SHDN = DVDD, VCH = open0.610µAIDVDDSHDN = DVDD, RD = WR = high0.021
Power-Supply Rejection RatioPSRRVAVDD = +4.75V to +5.25V50dB
TIMING CHARACTERISTICS (Figure 1)Time to First Conversion ResulttCONV
Internal clock, Figure 7800900ns
External clock, Figure 812CLK
Cycles
Time to Subsequent
ConversionstNEXT
Internal clock, Figure 7200225ns
External clock, Figure 83CLK
Cycles
CONVST Pulse-Width Low
(Acquisition Time)tACQ(Note 9) Figures 6–100.11000.0µs
CS Pulse WidthtCSFigure 630ns
RD Pulse-Width LowtRDLFigures 7, 8, 930ns
RD Pulse-Width HightRDHFigures 7, 8, 930ns
WR Pulse-Width LowtWRLFigure 630ns
CS to WRtCTWFigure 6(Note 10)ns
WR to CStWTCFigure 6(Note 10)ns
CS to RDtCTRFigures 7, 8, 9(Note 10)ns
RD to CStRTCFigures 7, 8, 9(Note 10)ns
Data Access Time
(RD Low to Valid Data)tACCFigures 7, 8, 930ns
Bus Relinquish Time (RD High)tREQFigures 7, 8, 9530ns
CLK Rise to EOC DelaytEOCDFigure 820ns
CLK Rise to EOLC Fall DelaytEOLCDFigure 820ns
CONVST Fall to EOLC Rise
DelaytCVEOLCDFigures 7, 8, 920ns
EOC Pulse WidthtEOC
Internal clock, Figure 750ns
External clock, Figure 81CLK
Cycle
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Electrical Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF, CREF+
= CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV = AGND
(bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C. See Figures 3 and 4.)
Note 1: For the MAX1304/MAX1305/MAX1306, VIN = 0 to +5V. For the MAX1308/MAX1309/MAX1310, VIN = -5V to +5V. For the
MAX1312/MAX1313/MAX1314, VIN = -10V to +10V.
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
CH_BIAS
CH_CH_IR−=for VCH_ within the input voltage range.
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (fCLK). The external clock throughput
rate is specified with fCLK = 16.67MHz and the internal clock throughput rate is specified with fCLK = 15MHz. See the Data
Throughput section for more information.
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
REFREF
REF2.5VIR−=for VREF within the input voltage range.
Note 6: The REFMS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REFMS input current using:
REFMSREFMS
REFMS2.5VIR−=for VREFMS within the input voltage range.
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input unconnected. The large amplitude of the maximum shutdown current
specification is due to automated test equipment limitations.
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST and the falling edge of EOLC to a maximum of 1ms
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput-Data Setup Time tDTWFigure 610ns
Input-Data Hold Time tWTDFigure 610ns
External CLK PeriodtCLKFigures 8, 90.0510.00µs
External CLK High PeriodtCLKHLogic sensitive to rising edges,
Figures 8, 920ns
External CLK Low PeriodtCLKLLogic sensitive to rising edges,
Figures 8, 920ns
External Clock FrequencyfCLK(Note 11)0.120MHz
Internal Clock FrequencyfINT15MHz
CONVST High to CLK EdgetCNTCFigures 8, 920ns
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Electrical Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1304 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
MAX1304 toc03
VAVDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR
vs. TEMPERATURE
MAX1304 toc04
TEMPERATURE (°C)
OFFSET ERROR (LSB)35-1510
MAX1304 toc05
GAIN ERROR (LSB)
GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1304 toc01
DIGITAL OUTPUT CODE
INL (LSB)
GAIN ERROR
vs. TEMPERATURE
MAX1304 toc06
GAIN ERROR (LSB)
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)
LARGE-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCYMAX1304 toc08
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)1
AIN = -0.5dBFS
FFT PLOT
(2048-POINT DATA RECORD)MAX1304 toc09
FREQUENCY (kHz)
AMPLITUDE (dBFS)
fTH = 1.04167Msps
fIN = 500kHz
AIN = -0.05dBFS
SNR = 70.7dB
SINAD = 70.6dB
THD = -87.5dBc
SFDR = 87.1dBc
OUTPUT HISTOGRAM (DC INPUT)MAX1304 toc10
DIGITAL OUTPUT CODE
COUNTS
SMALL-SIGNAL BANDWIDTH
vs. ANALOG INPUT FREQUENCY
MAX1304 toc07
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)1
AIN = -20dBFS
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)105152025
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCYMAX1304 toc12
fCLK (MHz)
SINAD (dB)
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
MAX1304 toc13
fCLK (MHz)
THD (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
MAX1304 toc14
fCLK (MHz)
SFDR (dBc)105152025
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCYMAX1304 toc11
fCLK (MHz)
SNR (dB)
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. REFERENCE VOLTAGEMAX1304 toc16
VREF (V)
SINAD (dB)
TOTAL HARMONIC DISTORTION
vs. REFERENCE VOLTAGE
MAX1304 toc17
VREF (V)
THD (dBc)
SPURIOUS-FREE DYNAMIC RANGE
vs. REFERENCE VOLTAGE
MAX1304 toc18
VREF (V)
SFDR (dBc)
SIGNAL-TO-NOISE RATIO
vs. REFERENCE VOLTAGE
MAX1304 toc15
VREF (V)
SNR (dB)
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGEMAX1304 toc20
VDVDD (V)
DVDD
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
CLOAD = 50pF
MAX1304 toc21
VAVDD (V)
AVDD
(nA)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1304 toc22
VDVDD (V)
DVDD
(nA)
ANALOG SUPPLY CURRENT
vs. NUMBER OF CHANNELS SELECTED
MAX1304 toc23
IAVDD
(mA)
CHSHDN = 0
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1304 toc19
VAVDD (V)
AVDD
(mA)
TA = +85°C
TA = +25°C
TA = -40°C
DIGITAL SUPPLY CURRENT
vs. NUMBER OF CHANNELS SELECTEDMAX1304 toc24
IDVDD
(mA)
CHSHDN = 0
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics (continued)
(VAVDD = +5V, VDVDD = +3V, VAGND = VDGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1μF,
CREF+ = CREF- = 0.1μF, CREF+-to-REF- = 2.2μF || 0.1μF, CCOM = 2.2μF || 0.1μF, CMSV = 2.2μF || 0.1μF (unipolar devices), MSV =
AGND (bipolar devices), fCLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), fIN = 500kHz, AIN = -0.4dBFS.
TA = +25°C, unless otherwise noted.) (Figures 3 and 4)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATUREMAX1304 toc26
TEMPERATURE (°C)
REF
(V)35-1510
INTERNAL CLOCK CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
MAX1304 toc27
VAVDD (V)
TIME (ns)
tNEXT
tCONV
INTERNAL CLOCK CONVERSION TIME
vs. TEMPERATUREMAX1304 toc28
TEMPERATURE (°C)
TIME (ns)3510-15
tNEXT
tCONV
MAX1304 toc29
ICH_
(mA)
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
MAX1304/MAX1305/MAX1306
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGEMAX1304 toc25
VAVDD (V)
REF
(V)
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
MAX1304 toc30
CH_
(mA)
MAX1308/MAX1309/MAX1310
ANALOG INPUT CHANNEL CURRENT
vs. ANALOG INPUT CHANNEL VOLTAGE
MAX1304 toc31
ICH_
(mA)
MAX1312/MAX1313/MAX1314
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Typical Operating Characteristics (continued)
PIN
NAMEFUNCTIONMAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX13141, 15, 171, 15, 171, 15, 17AVDD
Analog Power Input. AVDD is the power input for the analog section of the
converter. Apply +5V to AVDD. Connect all AVDD pins together. See the
Layout, Grounding, and Bypassing section for additional information.
2, 3, 14,
16, 23
2, 3, 14,
16, 23
2, 3, 14,
16, 23AGNDAnalog Ground. AGND is the power return for AVDD. Connect all AGND
pins together.44CH0Channel 0 Analog Input 55CH1Channel 1 Analog Input66MSV
Midscale Voltage Bypass. For the unipolar MAX1304/MAX1305/MAX1306,
connect a 2.2µF and a 0.1µF capacitor from MSV to AGND. For the bipolar
MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314, connect
MSV to AGND.7—CH2Channel 2 Analog Input8—CH3Channel 3 Analog Input——CH4Channel 4 Analog Input——CH5Channel 5 Analog Input——CH6Channel 6 Analog Input——CH7Channel 7 Analog Input1313INTCLK/
EXTCLK
Clock-Mode Select Input. Connect INTCLK/EXTCLK to AVDD to select the
internal clock. Connect INTCLK/EXTCLK to AGND to use an external clock
connected to CLK.1818REFMS
Midscale Reference Bypass or Input. REFMS connects through a 5kΩ resistor
to the internal +2.5V bandgap reference buffer.
For the MAX1304/MAX1305/MAX1306 unipolar devices, VREFMS is the input
to the unity-gain buffer that drives MSV. MSV sets the midpoint of the input
voltage range. For internal reference operation, bypass REFMS with a ≥ 0.01µF capacitor to AGND. For external reference operation, drive REFMS
with an external voltage from +2V to +3V.
For the MAX1308/MAX1309/MAX1310/MAX1312/MAX1313/MAX1314 bipolar
devices, connect REFMS to REF. For internal reference operation, bypass the
REFMS/REF node with a ≥ 0.01µF capacitor to AGND. For external reference
operation, drive the REFMS/REF node with an external voltage from +2V to +3V.1919REF
ADC Reference Bypass or Input. REF connects through a 5kΩ resistor to the
internal +2.5V bandgap reference buffer. For internal reference operation, bypass REF with a ≥ 0.01µF capacitor.
For external reference operation with the MAX1304/MAX1305/MAX1306
unipolar devices, drive REF with an external voltage from +2V to +3V.
For external reference operation with the MAX1308/MAX1309/MAX1310/
MAX1312/MAX1313/MAX1314 bipolar devices, connect REFMS to REF and
drive the REFMS/REF node with an external voltage from +2V to +3V.
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Pin Description
PIN
NAMEFUNCTIONMAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX13142020REF+
Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND.
Also bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.
VREF+ = VCOM + VREF/2.2121COMReference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF
capacitor. VCOM = 13/25 x AVDD.2222REF-
Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND.
Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.
VREF- = VCOM - VREF/2.
24, 3924, 3924, 39DGNDDigital Ground. DGND is the power return for DVDD. Connect all DGND
pins together.
25, 3825, 3825, 38DVDD
Digital Power Input. DVDD powers the digital section of the converter, including
the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND
with a 0.1µF capacitor. Connect all DVDD pins together.2626D0Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.2727D1Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.2828D2Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.2929D3Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.3030D4Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.3131D5Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.3232D6Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.3333D7Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.3434D8Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.3535D9Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.3636D10Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.3737D11Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.4040EOCEnd-of-Conversion Output. EOC goes low to indicate the end of a conversion. It
returns high on the next rising CLK edge or the falling CONVST edge. 4141EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the
last conversion. It returns high when CONVST goes low for the next
conversion sequence.4242RDRead Input. Pulling RD low initiates a read command of the parallel data bus.4343WRWrite Input. Pulling WR low initiates a write command for coniguring the
device with D0–D7.
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Pin Description (continued)
Detailed DescriptionThe MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314 are 12-bit ADCs. The devices offer 8, 4, or 2
independently selectable input channels, each with dedi-
cated T/H circuitry. Simultaneous sampling of all active
channels preserves relative phase information making
these devices ideal for motor control and power monitoring.
Three input ranges are available, 0 to +5V, ±5V and ±10V.
The 0 to +5V devices provide ±6V fault-tolerant inputs.
The ±5V and ±10V devices provide ±16.5V fault-tolerant
inputs. Two-channel conversion results are available in 0.9μs. Conversion results from all eight channels are avail-able in 1.98μs. The 8-channel throughput is 456ksps per
channel. Internal or external reference and clock capability
offer great flexibility, and ease of use. A write-only con-
figuration register can mask out unused channels and a
shutdown feature reduces power. A 20MHz, 12-bit, parallel
data bus outputs the conversion results. Figure 2 shows
the functional diagram of these ADCs.Figure 1. Digital Load Test Circuit
PIN
NAMEFUNCTIONMAX1304
MAX1308
MAX1312
MAX1305
MAX1309
MAX1313
MAX1306
MAX1310
MAX13144444CSChip-Select Input. Pulling CS low activates the digital interface. Forcing CS
high places D0–D11 in high-impedance mode.4545CONVSTConversion Start Input. Driving CONVST high initiates the conversion process.
The analog inputs are sampled on the rising edge of CONVST.4646CLK
External Clock Input. For external clock operation, connect INTCLK/EXTCLK
to AGND and drive CLK with an external clock signal from 100kHz to 20MHz.
For internal clock operation, connect INTCLK/EXTCLK to AVDD and connect
CLK to DGND.4747SHDNShutdown Input. Driving SHDN high initiates device shutdown. Connect SHDN
to DGND for normal operation.4848CHSHDN
Active-Low Analog-Input Channel-Shutdown Input. Drive CHSHDN low
to power down analog inputs that are not selected for conversion in the coniguration register. Drive CHSHDN high to power up all analog input
channels regardless of whether they are selected for conversion in the coniguration register. See the Channel Shutdown (CHSHDN) section for more
information.9, 10,
11, 12
7, 8, 9,
10, 11, 12I.C.Internally connected. Connect I.C. to AGND.
100pF
DEVICE PIN
VDD
IOL = 1.6mA
IOH = 0.8mA
1.6V
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Pin Description (continued)
Figure 2. Functional Diagram
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314CONVST
D11
MSV
DGND
AVDD
SHDN
INTCLK/EXTCLK
CLK
CH0
INTERFACE
AND
CONTROL
8 x 1
MUX
12-BIT
ADC
CH7D0
DVDD
AGND
CHSHDNREFMS
REF
REF+
COM
REF-
T/H
T/H
8 x 12
SRAM
OUTPUT
DRIVERS
5kΩ
5kΩ
CONFIGURATION
REGISTER
2.500V
*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES
EOC
EOLC
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Figure 3. Typical Bipolar Operating Circuit
MAX1308
MAX1312CH0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
D10
D11
AVDD
AGND
DVDD
DGND
MSV
REFMS
REF
REF+
COM
REF-
+5V
GND
+2.7V TO +5.25V
GND
BIPOLAR
ANALOG
INPUTS
PARALLEL
DIGITAL
OUTPUT
CONVST
DIGITAL
INTERFACE
AND
CONTROL
2, 3, 14, 16, 23
25, 3832
24, 39
AVDD
AVDD150.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
0.1µF
2.2µF
2.2µF
BIPOLAR
CONFIGURATION
CHSHDN
SHDN
CLK
EOLC
EOC
INTCLK/EXTCLK13
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Figure 4. Typical Unipolar Operating Circuit
MAX1304CH0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
D10
D11
AVDD
AGND
DVDD
DGND
MSV
REFMS
REF
REF+
COM
REF-
+5V
GND
+2.7V TO +5.25V
GND
UNIPOLAR
ANALOG
INPUTS
PARALLEL
DIGITAL
OUTPUT
CONVST
DIGITAL
INTERFACE
AND
CONTROL
2, 3, 14, 16, 23
25, 3832
24, 39
AVDD
AVDD150.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.01µF
0.1µF
2.2µF
2.2µF
UNIPOLAR
CONFIGURATION
0.1µF
2.2µF
CHSHDN
SHDN
CLK
EOLC
EOC
INTCLK/EXTCLK13
0.01µF
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
Analog Inputs
Track and Hold (T/H)To preserve phase information across the multichannel
MAX1304–MAX1306/MAX1308–MAX1310/MAX1312–
MAX1314, all input channels have dedicated T/H amplifi-
ers. Figure 5 shows the equivalent analog input T/H circuit
for one channel.
The input T/H circuit is controlled by the CONVST input.
When CONVST is low, the T/H circuit tracks the analog
input. When CONVST is high the T/H circuit holds the
analog input. The rising edge of CONVST is the analog
input sampling instant. There is an aperture delay (tAD)
of 8ns and a 50psRMS aperture jitter (tAJ). The aperture
delay of each dedicated T/H input is matched within
100ps of each other.
To settle the charge on CSAMPLE to 12-bit accuracy, use
a minimum acquisition time (tACQ) of 100ns. Therefore,
CONVST must be low for at least 100ns. Although longer
acquisition times allow the analog input to settle to its
final value more accurately, the maximum acquisition time
must be limited to 1ms. Accuracy with conversion times
longer than 1ms cannot be guaranteed due to capacitor
droop in the input circuitry.
Due to the analog input resistive divider formed by R1
and R2 in Figure 5, any significant analog input source
resistance (RSOURCE) results in gain error. Furthermore,
RSOURCE causes distortion due to nonlinear analog input
currents. Limit RSOURCE to a maximum of 100Ω.
Selecting an Input BufferTo improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (> 50MHz)
that can drive the ADC’s input capacitance (15pF) and
settle quickly. For example, the MAX4431 or the MAX4265
can be used for the 0 to +5V unipolar devices, or the
MAX4350 can be used for ±5V bipolar inputs.
Most applications require an input buffer to achieve 12-bit
accuracy. Although slew rate and bandwidth are impor-
tant, the most critical input buffer specification is settling
time. The simultaneous sampling of multiple channels
requires an acquisition time of 100ns. At the beginning of
the acquisition, the ADC internal sampling capacitor array
connects to the analog inputs, causing some disturbance.
Ensure the amplifier is capable of settling to at least 12-bit
accuracy during this interval. Use a low-noise, low-distor-
tion, wideband amplifier that settles quickly and is stable
with the ADC’s 15pF input capacitance.
See the Maxim website at
www.maximintegrated.com for application notes on how to choose the optimum buffer
amplifier for your ADC application.
Input BandwidthThe input-tracking circuitry has a 20MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid high-frequency sig-
nals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Input Range and ProtectionThe MAX1304/MAX1305/MAX1306 provide a 0 to +5V
input voltage range with fault protection of ±6V. The
MAX1308/MAX1309/MAX1310 provide a ±5V input volt-
age range with fault protection of ±16.5V. The MAX1312/
MAX1313/MAX1314 provide a ±10V input voltage range
with fault protection of ±16.5V. Figure 5 shows the single-
channel equivalent input circuit.
Figure 5. Single-Channel, Equivalent Analog Input T/H Circuit
CH_
UNDERVOLTAGE
PROTECTION
CLAMP
OVERVOLTAGE
PROTECTION
CLAMP2.5pF
AVDD
CSAMPLE
CHOLD
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314R1 | | R2 = 2kΩ
VBIAS
*RSOURCE
ANALOG
SIGNAL
SOURCE
*MINIMIZE RSOURCE TO AVOID GAIN ERROR AND DISTORTION.
INPUT RANGE (V)PART0 TO +5
MAX1304
MAX1305
MAX1306
MAX1308
MAX1309
MAX1310
MAX1312
MAX1313
MAX1314
±10
R1 (kΩ) R2 (kΩ) VBIAS (V)
2.06
MAX1304–MAX1306
MAX1308–MAX1310
MAX1312–MAX1314
8-/4-/2-Channel, 12-Bit, Simultaneous-
Sampling ADCs with ±10V, ±5V, and 0 to +5V
Analog Input Ranges
